Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	324393692	1			T1	352286		T2	196606		T3	917504
instr_valid_dis	278170413	1			T1	352286		T2	196606		T3	917504
instr_en	31743933	1			T7	30850		T145	165440		T21	196700

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18016101	1			T1	96800		T7	552840		T28	122848
sram_ifetch_valid_disable	277576999	1			T1	58252		T2	196606		T3	917504
sram_ifetch_enable	28800592	1			T1	197234		T7	781772		T28	175018

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	324393692	1			T1	352286		T2	196606		T3	917504
hw_debug_en_valid_off	278624429	1			T1	210490		T2	196606		T3	917504
hw_debug_en_on	35129943	1			T1	116688		T7	958478		T28	117620

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	277576999	1			T1	58252		T2	196606		T3	917504
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	262596379	1			T1	58252		T2	196606		T3	917504
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10407476	1			T145	140648		T21	111860		T152	58962
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5806106	1			T1	43606		T7	104076		T28	66558
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2061974	1			T1	43606		T147	112546		T153	33524
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2874282	1			T84	18630		T150	134420		T154	31556
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	10109557	1			T1	53194		T7	373770		T145	14710
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1452388	1			T1	53194		T145	14710		T22	28344
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3986361	1			T153	18496		T154	121544		T146	11032
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10501824	1			T1	29524		T7	267424		T28	62522
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5068982	1			T1	29524		T145	13432		T21	15290
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3585890	1			T145	67900		T152	19414		T84	78026

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13599460	1			T7	30850		T145	24792		T21	66028
lc_exec_en	14518562	1			T1	33970		T7	317284		T28	55098
valid_exec_dis	274121329	1			T1	221898		T2	196606		T3	917504
invalid_exec_dis	46816693	1			T1	294034		T7	133461		T28	297866