Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	131406006	1			T1	71905		T2	98303		T3	458752
triple_byte_access	2851941	1			T1	1520		T4	3207		T5	3704
halfword_access	4368493	1			T1	2072		T4	5052		T5	5592
byte_access	6102292	1			T1	2837		T4	6779		T5	7403
zero_access	1841440	1			T1	737		T4	1734		T5	1911

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73063519

1

T1

43808

T2

32768

T3

229376

auto[1]

73506653

1

T1

35263

T2

65535

T3

229376

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	65336815	1			T1	39879		T2	32768		T3	229376
auto[0]	triple_byte_access	1363435	1			T1	833		T4	1575		T5	1835
auto[0]	halfword_access	2137622	1			T1	1137		T4	2515		T5	2764
auto[0]	byte_access	3128911	1			T1	1528		T4	3484		T5	3645
auto[0]	zero_access	1096736	1			T1	431		T4	858		T5	925
auto[1]	word_access	66069191	1			T1	32026		T2	65535		T3	229376
auto[1]	triple_byte_access	1488506	1			T1	687		T4	1632		T5	1869
auto[1]	halfword_access	2230871	1			T1	935		T4	2537		T5	2828
auto[1]	byte_access	2973381	1			T1	1309		T4	3295		T5	3758
auto[1]	zero_access	744704	1			T1	306		T4	876		T5	986