| T794 |
/workspace/coverage/default/46.sram_ctrl_bijection.23747812 |
|
|
Aug 13 05:40:29 PM PDT 24 |
Aug 13 06:00:12 PM PDT 24 |
50966208195 ps |
| T795 |
/workspace/coverage/default/36.sram_ctrl_partial_access.226719108 |
|
|
Aug 13 05:39:24 PM PDT 24 |
Aug 13 05:39:37 PM PDT 24 |
5635726596 ps |
| T104 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3515546416 |
|
|
Aug 13 05:38:18 PM PDT 24 |
Aug 13 05:39:46 PM PDT 24 |
13903171761 ps |
| T796 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.3419535717 |
|
|
Aug 13 05:40:31 PM PDT 24 |
Aug 13 05:40:44 PM PDT 24 |
2851062984 ps |
| T797 |
/workspace/coverage/default/47.sram_ctrl_partial_access.993325076 |
|
|
Aug 13 05:40:30 PM PDT 24 |
Aug 13 05:41:02 PM PDT 24 |
3960410573 ps |
| T798 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.4279012764 |
|
|
Aug 13 05:38:25 PM PDT 24 |
Aug 13 05:39:51 PM PDT 24 |
11190402806 ps |
| T799 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3996470264 |
|
|
Aug 13 05:39:55 PM PDT 24 |
Aug 13 05:47:19 PM PDT 24 |
6006164654 ps |
| T800 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2995250824 |
|
|
Aug 13 05:38:07 PM PDT 24 |
Aug 13 05:38:30 PM PDT 24 |
13970161942 ps |
| T801 |
/workspace/coverage/default/21.sram_ctrl_regwen.4155556059 |
|
|
Aug 13 05:38:27 PM PDT 24 |
Aug 13 05:55:31 PM PDT 24 |
12890080214 ps |
| T802 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3915468370 |
|
|
Aug 13 05:38:27 PM PDT 24 |
Aug 13 05:40:40 PM PDT 24 |
3171430414 ps |
| T803 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.639529330 |
|
|
Aug 13 05:38:09 PM PDT 24 |
Aug 13 05:42:02 PM PDT 24 |
3266331968 ps |
| T804 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2469664892 |
|
|
Aug 13 05:38:28 PM PDT 24 |
Aug 13 05:40:11 PM PDT 24 |
17298570892 ps |
| T805 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2107159136 |
|
|
Aug 13 05:38:16 PM PDT 24 |
Aug 13 05:39:32 PM PDT 24 |
6350944815 ps |
| T806 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3607541674 |
|
|
Aug 13 05:38:24 PM PDT 24 |
Aug 13 05:40:00 PM PDT 24 |
1597391467 ps |
| T807 |
/workspace/coverage/default/14.sram_ctrl_executable.3088400789 |
|
|
Aug 13 05:38:24 PM PDT 24 |
Aug 13 05:40:12 PM PDT 24 |
1489515550 ps |
| T808 |
/workspace/coverage/default/27.sram_ctrl_regwen.1687433255 |
|
|
Aug 13 05:38:55 PM PDT 24 |
Aug 13 06:06:25 PM PDT 24 |
61313333091 ps |
| T809 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.585060860 |
|
|
Aug 13 05:38:51 PM PDT 24 |
Aug 13 05:51:14 PM PDT 24 |
44732153903 ps |
| T810 |
/workspace/coverage/default/29.sram_ctrl_executable.875164843 |
|
|
Aug 13 05:39:05 PM PDT 24 |
Aug 13 05:48:08 PM PDT 24 |
13254609618 ps |
| T811 |
/workspace/coverage/default/39.sram_ctrl_bijection.4273238056 |
|
|
Aug 13 05:39:44 PM PDT 24 |
Aug 13 06:02:11 PM PDT 24 |
331720640049 ps |
| T812 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2814320151 |
|
|
Aug 13 05:39:59 PM PDT 24 |
Aug 13 05:40:37 PM PDT 24 |
2171906941 ps |
| T813 |
/workspace/coverage/default/23.sram_ctrl_alert_test.477061360 |
|
|
Aug 13 05:38:38 PM PDT 24 |
Aug 13 05:38:39 PM PDT 24 |
26011813 ps |
| T814 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1381954007 |
|
|
Aug 13 05:38:49 PM PDT 24 |
Aug 13 05:54:17 PM PDT 24 |
7878517791 ps |
| T815 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3440872319 |
|
|
Aug 13 05:40:01 PM PDT 24 |
Aug 13 05:40:43 PM PDT 24 |
6718852735 ps |
| T816 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.3800695440 |
|
|
Aug 13 05:38:26 PM PDT 24 |
Aug 13 05:38:30 PM PDT 24 |
651735013 ps |
| T817 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1350104571 |
|
|
Aug 13 05:39:04 PM PDT 24 |
Aug 13 05:39:33 PM PDT 24 |
2978018936 ps |
| T818 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2988445541 |
|
|
Aug 13 05:38:41 PM PDT 24 |
Aug 13 05:40:50 PM PDT 24 |
808777193 ps |
| T819 |
/workspace/coverage/default/37.sram_ctrl_bijection.1466262363 |
|
|
Aug 13 05:39:38 PM PDT 24 |
Aug 13 05:48:30 PM PDT 24 |
93132983491 ps |
| T820 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.610868068 |
|
|
Aug 13 05:40:06 PM PDT 24 |
Aug 13 05:41:12 PM PDT 24 |
10413124414 ps |
| T821 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.1839699796 |
|
|
Aug 13 05:37:48 PM PDT 24 |
Aug 13 05:40:52 PM PDT 24 |
10772324834 ps |
| T822 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1891213064 |
|
|
Aug 13 05:39:40 PM PDT 24 |
Aug 13 05:40:07 PM PDT 24 |
1945486331 ps |
| T823 |
/workspace/coverage/default/0.sram_ctrl_smoke.1240052962 |
|
|
Aug 13 05:37:36 PM PDT 24 |
Aug 13 05:37:43 PM PDT 24 |
2769478353 ps |
| T824 |
/workspace/coverage/default/4.sram_ctrl_executable.2372484848 |
|
|
Aug 13 05:37:50 PM PDT 24 |
Aug 13 05:53:39 PM PDT 24 |
13342514176 ps |
| T825 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1228704359 |
|
|
Aug 13 05:39:20 PM PDT 24 |
Aug 13 05:42:14 PM PDT 24 |
7036963919 ps |
| T826 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1213277335 |
|
|
Aug 13 05:38:41 PM PDT 24 |
Aug 13 05:39:20 PM PDT 24 |
5750612131 ps |
| T827 |
/workspace/coverage/default/8.sram_ctrl_smoke.3168745832 |
|
|
Aug 13 05:38:16 PM PDT 24 |
Aug 13 05:39:01 PM PDT 24 |
406619955 ps |
| T828 |
/workspace/coverage/default/14.sram_ctrl_regwen.3518721855 |
|
|
Aug 13 05:38:20 PM PDT 24 |
Aug 13 05:40:59 PM PDT 24 |
5210901761 ps |
| T829 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.213856058 |
|
|
Aug 13 05:39:55 PM PDT 24 |
Aug 13 05:39:59 PM PDT 24 |
1410427479 ps |
| T830 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1024129272 |
|
|
Aug 13 05:39:03 PM PDT 24 |
Aug 13 05:39:06 PM PDT 24 |
1352177005 ps |
| T831 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3787893454 |
|
|
Aug 13 05:38:07 PM PDT 24 |
Aug 13 05:44:21 PM PDT 24 |
26219959357 ps |
| T832 |
/workspace/coverage/default/44.sram_ctrl_smoke.1416017291 |
|
|
Aug 13 05:40:13 PM PDT 24 |
Aug 13 05:42:13 PM PDT 24 |
982826321 ps |
| T833 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1118137128 |
|
|
Aug 13 05:39:26 PM PDT 24 |
Aug 13 05:39:49 PM PDT 24 |
2581649988 ps |
| T834 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2389058748 |
|
|
Aug 13 05:38:18 PM PDT 24 |
Aug 13 05:39:49 PM PDT 24 |
16218579298 ps |
| T835 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2007774662 |
|
|
Aug 13 05:39:44 PM PDT 24 |
Aug 13 05:41:58 PM PDT 24 |
7901277516 ps |
| T836 |
/workspace/coverage/default/2.sram_ctrl_executable.1579268873 |
|
|
Aug 13 05:37:45 PM PDT 24 |
Aug 13 05:50:38 PM PDT 24 |
22705151230 ps |
| T837 |
/workspace/coverage/default/41.sram_ctrl_executable.4178706100 |
|
|
Aug 13 05:39:56 PM PDT 24 |
Aug 13 06:06:58 PM PDT 24 |
15052863529 ps |
| T838 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3076631742 |
|
|
Aug 13 05:40:05 PM PDT 24 |
Aug 13 05:46:01 PM PDT 24 |
5692756013 ps |
| T839 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2526898289 |
|
|
Aug 13 05:38:48 PM PDT 24 |
Aug 13 05:46:57 PM PDT 24 |
25986605120 ps |
| T840 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.3835351403 |
|
|
Aug 13 05:38:55 PM PDT 24 |
Aug 13 05:45:30 PM PDT 24 |
256499648402 ps |
| T841 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1983769814 |
|
|
Aug 13 05:38:40 PM PDT 24 |
Aug 13 05:44:17 PM PDT 24 |
66552455843 ps |
| T842 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3170249143 |
|
|
Aug 13 05:38:00 PM PDT 24 |
Aug 13 05:39:46 PM PDT 24 |
65870325992 ps |
| T843 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.517506236 |
|
|
Aug 13 05:38:50 PM PDT 24 |
Aug 13 05:43:23 PM PDT 24 |
10883028596 ps |
| T844 |
/workspace/coverage/default/41.sram_ctrl_partial_access.139859306 |
|
|
Aug 13 05:39:53 PM PDT 24 |
Aug 13 05:40:27 PM PDT 24 |
2381404187 ps |
| T845 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2971252536 |
|
|
Aug 13 05:38:15 PM PDT 24 |
Aug 13 05:38:18 PM PDT 24 |
1879040467 ps |
| T846 |
/workspace/coverage/default/22.sram_ctrl_regwen.697816929 |
|
|
Aug 13 05:38:34 PM PDT 24 |
Aug 13 05:43:25 PM PDT 24 |
1620306319 ps |
| T847 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3462149170 |
|
|
Aug 13 05:40:21 PM PDT 24 |
Aug 13 05:42:45 PM PDT 24 |
816033672 ps |
| T848 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2415961459 |
|
|
Aug 13 05:40:06 PM PDT 24 |
Aug 13 05:41:29 PM PDT 24 |
12752949278 ps |
| T849 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2093771510 |
|
|
Aug 13 05:38:10 PM PDT 24 |
Aug 13 05:38:37 PM PDT 24 |
3649011350 ps |
| T850 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3738893030 |
|
|
Aug 13 05:37:47 PM PDT 24 |
Aug 13 06:20:31 PM PDT 24 |
131238967177 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3293704218 |
|
|
Aug 13 05:37:52 PM PDT 24 |
Aug 13 05:38:02 PM PDT 24 |
232876025 ps |
| T852 |
/workspace/coverage/default/6.sram_ctrl_executable.826441620 |
|
|
Aug 13 05:37:50 PM PDT 24 |
Aug 13 05:47:06 PM PDT 24 |
22334657063 ps |
| T853 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1688528528 |
|
|
Aug 13 05:38:58 PM PDT 24 |
Aug 13 05:39:02 PM PDT 24 |
362858410 ps |
| T854 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1039717765 |
|
|
Aug 13 05:40:13 PM PDT 24 |
Aug 13 05:43:24 PM PDT 24 |
3502795369 ps |
| T855 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.994048925 |
|
|
Aug 13 05:39:57 PM PDT 24 |
Aug 13 05:42:23 PM PDT 24 |
1418295545 ps |
| T856 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.19235032 |
|
|
Aug 13 05:38:52 PM PDT 24 |
Aug 13 05:44:56 PM PDT 24 |
41338429830 ps |
| T857 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1939765624 |
|
|
Aug 13 05:39:05 PM PDT 24 |
Aug 13 05:39:15 PM PDT 24 |
1216148348 ps |
| T858 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2194437161 |
|
|
Aug 13 05:37:59 PM PDT 24 |
Aug 13 05:43:57 PM PDT 24 |
5738208397 ps |
| T859 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1851766590 |
|
|
Aug 13 05:38:05 PM PDT 24 |
Aug 13 05:41:31 PM PDT 24 |
21381157974 ps |
| T860 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3056285927 |
|
|
Aug 13 05:40:37 PM PDT 24 |
Aug 13 05:48:29 PM PDT 24 |
72835758437 ps |
| T861 |
/workspace/coverage/default/33.sram_ctrl_bijection.4285687016 |
|
|
Aug 13 05:39:19 PM PDT 24 |
Aug 13 05:53:07 PM PDT 24 |
93323122507 ps |
| T862 |
/workspace/coverage/default/16.sram_ctrl_alert_test.4264523374 |
|
|
Aug 13 05:38:27 PM PDT 24 |
Aug 13 05:38:28 PM PDT 24 |
71219041 ps |
| T863 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4289512709 |
|
|
Aug 13 05:37:58 PM PDT 24 |
Aug 13 05:39:14 PM PDT 24 |
26271284491 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_stress_all.711582370 |
|
|
Aug 13 05:38:27 PM PDT 24 |
Aug 13 07:24:14 PM PDT 24 |
251491158961 ps |
| T865 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1874032190 |
|
|
Aug 13 05:38:34 PM PDT 24 |
Aug 13 05:41:29 PM PDT 24 |
37346626478 ps |
| T866 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.33079488 |
|
|
Aug 13 05:38:46 PM PDT 24 |
Aug 13 05:52:02 PM PDT 24 |
54492936094 ps |
| T867 |
/workspace/coverage/default/6.sram_ctrl_stress_all.3482894830 |
|
|
Aug 13 05:37:59 PM PDT 24 |
Aug 13 06:08:10 PM PDT 24 |
282616017132 ps |
| T868 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3782416692 |
|
|
Aug 13 05:38:05 PM PDT 24 |
Aug 13 05:56:25 PM PDT 24 |
57473535360 ps |
| T869 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.321083813 |
|
|
Aug 13 05:40:09 PM PDT 24 |
Aug 13 05:40:12 PM PDT 24 |
722030745 ps |
| T870 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2014852112 |
|
|
Aug 13 05:37:51 PM PDT 24 |
Aug 13 05:37:55 PM PDT 24 |
3363768104 ps |
| T871 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3927645299 |
|
|
Aug 13 05:37:57 PM PDT 24 |
Aug 13 05:38:53 PM PDT 24 |
1834019503 ps |
| T872 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3396282172 |
|
|
Aug 13 05:38:40 PM PDT 24 |
Aug 13 05:39:34 PM PDT 24 |
1097058566 ps |
| T873 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.487328305 |
|
|
Aug 13 05:37:59 PM PDT 24 |
Aug 13 05:38:03 PM PDT 24 |
368876422 ps |
| T874 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1037858619 |
|
|
Aug 13 05:39:19 PM PDT 24 |
Aug 13 05:49:07 PM PDT 24 |
38421941323 ps |
| T875 |
/workspace/coverage/default/16.sram_ctrl_executable.1840367519 |
|
|
Aug 13 05:38:21 PM PDT 24 |
Aug 13 05:50:13 PM PDT 24 |
128390060833 ps |
| T876 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2775651574 |
|
|
Aug 13 05:37:59 PM PDT 24 |
Aug 13 05:38:00 PM PDT 24 |
18813486 ps |
| T877 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3438596485 |
|
|
Aug 13 05:37:56 PM PDT 24 |
Aug 13 05:38:54 PM PDT 24 |
3133169185 ps |
| T878 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3408665733 |
|
|
Aug 13 05:39:20 PM PDT 24 |
Aug 13 05:47:13 PM PDT 24 |
19028058834 ps |
| T879 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2416836185 |
|
|
Aug 13 05:38:22 PM PDT 24 |
Aug 13 05:43:52 PM PDT 24 |
15744999455 ps |
| T880 |
/workspace/coverage/default/38.sram_ctrl_smoke.6848732 |
|
|
Aug 13 05:39:39 PM PDT 24 |
Aug 13 05:39:48 PM PDT 24 |
3001125534 ps |
| T881 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.94456395 |
|
|
Aug 13 05:39:26 PM PDT 24 |
Aug 13 05:40:14 PM PDT 24 |
6342100102 ps |
| T882 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1825831456 |
|
|
Aug 13 05:38:30 PM PDT 24 |
Aug 13 05:38:42 PM PDT 24 |
728314000 ps |
| T883 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1330557171 |
|
|
Aug 13 05:38:31 PM PDT 24 |
Aug 13 05:55:07 PM PDT 24 |
14388235446 ps |
| T884 |
/workspace/coverage/default/3.sram_ctrl_regwen.1593489421 |
|
|
Aug 13 05:38:08 PM PDT 24 |
Aug 13 05:58:04 PM PDT 24 |
37019179951 ps |
| T885 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.4114419162 |
|
|
Aug 13 05:38:26 PM PDT 24 |
Aug 13 05:44:02 PM PDT 24 |
28815397371 ps |
| T886 |
/workspace/coverage/default/14.sram_ctrl_alert_test.2216532770 |
|
|
Aug 13 05:38:28 PM PDT 24 |
Aug 13 05:38:29 PM PDT 24 |
17689812 ps |
| T887 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2872841960 |
|
|
Aug 13 05:37:53 PM PDT 24 |
Aug 13 05:48:28 PM PDT 24 |
90278954355 ps |
| T888 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.382037390 |
|
|
Aug 13 05:38:10 PM PDT 24 |
Aug 13 05:38:19 PM PDT 24 |
718978378 ps |
| T889 |
/workspace/coverage/default/4.sram_ctrl_bijection.4248599083 |
|
|
Aug 13 05:37:52 PM PDT 24 |
Aug 13 06:10:39 PM PDT 24 |
123524865179 ps |
| T890 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3686476769 |
|
|
Aug 13 05:38:19 PM PDT 24 |
Aug 13 05:40:48 PM PDT 24 |
8725581659 ps |
| T891 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3459845767 |
|
|
Aug 13 05:38:09 PM PDT 24 |
Aug 13 05:39:18 PM PDT 24 |
3101577186 ps |
| T892 |
/workspace/coverage/default/19.sram_ctrl_bijection.2263695232 |
|
|
Aug 13 05:38:25 PM PDT 24 |
Aug 13 05:48:21 PM PDT 24 |
136678325031 ps |
| T893 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2856614785 |
|
|
Aug 13 05:39:09 PM PDT 24 |
Aug 13 05:41:25 PM PDT 24 |
8294470992 ps |
| T33 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2109627516 |
|
|
Aug 13 05:37:42 PM PDT 24 |
Aug 13 05:37:46 PM PDT 24 |
278547183 ps |
| T894 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1413198575 |
|
|
Aug 13 05:39:26 PM PDT 24 |
Aug 13 07:52:10 PM PDT 24 |
386506568841 ps |
| T895 |
/workspace/coverage/default/37.sram_ctrl_stress_all.619528471 |
|
|
Aug 13 05:39:41 PM PDT 24 |
Aug 13 07:03:58 PM PDT 24 |
112126854460 ps |
| T896 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.4292371799 |
|
|
Aug 13 05:39:06 PM PDT 24 |
Aug 13 05:46:21 PM PDT 24 |
13118940852 ps |
| T897 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1389483740 |
|
|
Aug 13 05:39:39 PM PDT 24 |
Aug 13 05:54:56 PM PDT 24 |
35842189604 ps |
| T898 |
/workspace/coverage/default/48.sram_ctrl_regwen.131784360 |
|
|
Aug 13 05:40:46 PM PDT 24 |
Aug 13 05:54:16 PM PDT 24 |
20551399431 ps |
| T899 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.576989829 |
|
|
Aug 13 05:38:57 PM PDT 24 |
Aug 13 05:39:10 PM PDT 24 |
283832360 ps |
| T900 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2451245370 |
|
|
Aug 13 05:39:39 PM PDT 24 |
Aug 13 05:50:21 PM PDT 24 |
15502587489 ps |
| T901 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.984203816 |
|
|
Aug 13 05:40:29 PM PDT 24 |
Aug 13 05:42:03 PM PDT 24 |
15530152520 ps |
| T902 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3908579768 |
|
|
Aug 13 05:40:04 PM PDT 24 |
Aug 13 07:21:04 PM PDT 24 |
907525500132 ps |
| T903 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1195488349 |
|
|
Aug 13 05:40:38 PM PDT 24 |
Aug 13 05:41:43 PM PDT 24 |
3902627846 ps |
| T904 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1804277807 |
|
|
Aug 13 05:38:26 PM PDT 24 |
Aug 13 05:38:30 PM PDT 24 |
1536131074 ps |
| T905 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1628788555 |
|
|
Aug 13 05:39:03 PM PDT 24 |
Aug 13 05:44:56 PM PDT 24 |
6630839902 ps |
| T906 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.4241539345 |
|
|
Aug 13 05:38:47 PM PDT 24 |
Aug 13 05:39:52 PM PDT 24 |
3859804616 ps |
| T907 |
/workspace/coverage/default/10.sram_ctrl_regwen.1408880845 |
|
|
Aug 13 05:38:12 PM PDT 24 |
Aug 13 05:43:16 PM PDT 24 |
13489664414 ps |
| T908 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.416922495 |
|
|
Aug 13 05:40:30 PM PDT 24 |
Aug 13 05:42:59 PM PDT 24 |
3329466863 ps |
| T909 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3295612765 |
|
|
Aug 13 05:38:30 PM PDT 24 |
Aug 13 05:38:49 PM PDT 24 |
7813725190 ps |
| T910 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1530516016 |
|
|
Aug 13 05:38:50 PM PDT 24 |
Aug 13 05:39:15 PM PDT 24 |
1031084317 ps |
| T911 |
/workspace/coverage/default/6.sram_ctrl_bijection.1627617135 |
|
|
Aug 13 05:38:23 PM PDT 24 |
Aug 13 05:46:02 PM PDT 24 |
14666105115 ps |
| T912 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1944402068 |
|
|
Aug 13 05:38:51 PM PDT 24 |
Aug 13 05:40:52 PM PDT 24 |
13271883895 ps |
| T913 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2579146059 |
|
|
Aug 13 05:38:23 PM PDT 24 |
Aug 13 05:38:47 PM PDT 24 |
6399261766 ps |
| T914 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3422079757 |
|
|
Aug 13 05:40:21 PM PDT 24 |
Aug 13 05:48:46 PM PDT 24 |
22041316941 ps |
| T915 |
/workspace/coverage/default/30.sram_ctrl_smoke.447924526 |
|
|
Aug 13 05:38:50 PM PDT 24 |
Aug 13 05:39:07 PM PDT 24 |
924420785 ps |
| T916 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2276529350 |
|
|
Aug 13 05:39:44 PM PDT 24 |
Aug 13 05:45:25 PM PDT 24 |
72799678461 ps |
| T917 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1589815445 |
|
|
Aug 13 05:38:47 PM PDT 24 |
Aug 13 05:59:00 PM PDT 24 |
75154925410 ps |
| T918 |
/workspace/coverage/default/38.sram_ctrl_alert_test.899392673 |
|
|
Aug 13 05:39:44 PM PDT 24 |
Aug 13 05:39:45 PM PDT 24 |
23572955 ps |
| T919 |
/workspace/coverage/default/29.sram_ctrl_bijection.3752615981 |
|
|
Aug 13 05:38:47 PM PDT 24 |
Aug 13 06:00:14 PM PDT 24 |
38936239957 ps |
| T920 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2998640517 |
|
|
Aug 13 05:39:06 PM PDT 24 |
Aug 13 05:41:33 PM PDT 24 |
2743888089 ps |
| T921 |
/workspace/coverage/default/13.sram_ctrl_bijection.261281767 |
|
|
Aug 13 05:38:20 PM PDT 24 |
Aug 13 06:17:36 PM PDT 24 |
103233834185 ps |
| T922 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2546835463 |
|
|
Aug 13 05:40:48 PM PDT 24 |
Aug 13 05:40:49 PM PDT 24 |
23397519 ps |
| T923 |
/workspace/coverage/default/41.sram_ctrl_bijection.3359483373 |
|
|
Aug 13 05:39:49 PM PDT 24 |
Aug 13 06:03:50 PM PDT 24 |
250091342673 ps |
| T924 |
/workspace/coverage/default/25.sram_ctrl_smoke.904942619 |
|
|
Aug 13 05:38:57 PM PDT 24 |
Aug 13 05:39:02 PM PDT 24 |
359791159 ps |
| T925 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1094291697 |
|
|
Aug 13 05:37:53 PM PDT 24 |
Aug 13 05:57:28 PM PDT 24 |
67217914210 ps |
| T926 |
/workspace/coverage/default/40.sram_ctrl_stress_all.1579556478 |
|
|
Aug 13 05:39:51 PM PDT 24 |
Aug 13 06:16:14 PM PDT 24 |
73515472253 ps |
| T927 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1528066758 |
|
|
Aug 13 05:39:45 PM PDT 24 |
Aug 13 05:41:07 PM PDT 24 |
9424310223 ps |
| T928 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1392555579 |
|
|
Aug 13 05:38:27 PM PDT 24 |
Aug 13 05:38:30 PM PDT 24 |
743245604 ps |
| T929 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3502980221 |
|
|
Aug 13 05:37:55 PM PDT 24 |
Aug 13 05:37:56 PM PDT 24 |
36464612 ps |
| T930 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3507149488 |
|
|
Aug 13 05:40:37 PM PDT 24 |
Aug 13 05:40:43 PM PDT 24 |
2618353879 ps |
| T931 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1893114244 |
|
|
Aug 13 05:39:08 PM PDT 24 |
Aug 13 05:41:43 PM PDT 24 |
3209645592 ps |
| T932 |
/workspace/coverage/default/42.sram_ctrl_bijection.788726092 |
|
|
Aug 13 05:39:55 PM PDT 24 |
Aug 13 05:57:39 PM PDT 24 |
47745346306 ps |
| T933 |
/workspace/coverage/default/26.sram_ctrl_regwen.2925615789 |
|
|
Aug 13 05:39:01 PM PDT 24 |
Aug 13 05:44:47 PM PDT 24 |
23262654555 ps |
| T934 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3591046241 |
|
|
Aug 13 05:38:01 PM PDT 24 |
Aug 13 05:38:52 PM PDT 24 |
3213048675 ps |
| T935 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.788699331 |
|
|
Aug 13 05:39:26 PM PDT 24 |
Aug 13 05:45:39 PM PDT 24 |
14045863985 ps |
| T936 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3889502202 |
|
|
Aug 13 05:39:24 PM PDT 24 |
Aug 13 06:49:49 PM PDT 24 |
206858760519 ps |
| T937 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3657614742 |
|
|
Aug 13 05:38:37 PM PDT 24 |
Aug 13 05:40:09 PM PDT 24 |
18839498650 ps |
| T938 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1742223763 |
|
|
Aug 13 05:38:05 PM PDT 24 |
Aug 13 06:36:16 PM PDT 24 |
197911884868 ps |
| T939 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1585868646 |
|
|
Aug 13 05:39:39 PM PDT 24 |
Aug 13 05:39:40 PM PDT 24 |
17525646 ps |
| T940 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3678949478 |
|
|
Aug 13 05:38:12 PM PDT 24 |
Aug 13 05:52:03 PM PDT 24 |
10092570361 ps |
| T941 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2885236151 |
|
|
Aug 13 05:38:43 PM PDT 24 |
Aug 13 05:40:12 PM PDT 24 |
787476096 ps |
| T71 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.382178101 |
|
|
Aug 13 05:36:44 PM PDT 24 |
Aug 13 05:37:12 PM PDT 24 |
3909489130 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.538837303 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:37:10 PM PDT 24 |
11937405927 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1843809869 |
|
|
Aug 13 05:36:57 PM PDT 24 |
Aug 13 05:37:01 PM PDT 24 |
344027365 ps |
| T73 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1733199029 |
|
|
Aug 13 05:36:56 PM PDT 24 |
Aug 13 05:36:56 PM PDT 24 |
15631937 ps |
| T943 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2825294755 |
|
|
Aug 13 05:37:02 PM PDT 24 |
Aug 13 05:37:03 PM PDT 24 |
15341504 ps |
| T114 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.420807391 |
|
|
Aug 13 05:36:59 PM PDT 24 |
Aug 13 05:37:00 PM PDT 24 |
77174987 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2957190192 |
|
|
Aug 13 05:36:40 PM PDT 24 |
Aug 13 05:36:41 PM PDT 24 |
42655206 ps |
| T86 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3502248225 |
|
|
Aug 13 05:36:44 PM PDT 24 |
Aug 13 05:36:45 PM PDT 24 |
95672300 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3288514021 |
|
|
Aug 13 05:36:51 PM PDT 24 |
Aug 13 05:36:55 PM PDT 24 |
56534796 ps |
| T68 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3298953319 |
|
|
Aug 13 05:36:52 PM PDT 24 |
Aug 13 05:36:53 PM PDT 24 |
257117135 ps |
| T116 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1171939853 |
|
|
Aug 13 05:36:47 PM PDT 24 |
Aug 13 05:36:48 PM PDT 24 |
17474788 ps |
| T118 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3998519200 |
|
|
Aug 13 05:36:48 PM PDT 24 |
Aug 13 05:36:49 PM PDT 24 |
98043631 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1352338467 |
|
|
Aug 13 05:36:46 PM PDT 24 |
Aug 13 05:36:49 PM PDT 24 |
105501270 ps |
| T946 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3102581771 |
|
|
Aug 13 05:36:37 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
1179083982 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3938638975 |
|
|
Aug 13 05:36:51 PM PDT 24 |
Aug 13 05:36:52 PM PDT 24 |
24823815 ps |
| T88 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3267138657 |
|
|
Aug 13 05:36:53 PM PDT 24 |
Aug 13 05:37:19 PM PDT 24 |
3997019029 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3594979286 |
|
|
Aug 13 05:36:54 PM PDT 24 |
Aug 13 05:37:22 PM PDT 24 |
19405940269 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2948042262 |
|
|
Aug 13 05:36:48 PM PDT 24 |
Aug 13 05:36:49 PM PDT 24 |
26277025 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2874694168 |
|
|
Aug 13 05:36:38 PM PDT 24 |
Aug 13 05:36:39 PM PDT 24 |
13947842 ps |
| T91 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3153180087 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:37:39 PM PDT 24 |
28230428282 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3670704472 |
|
|
Aug 13 05:36:36 PM PDT 24 |
Aug 13 05:36:37 PM PDT 24 |
28651730 ps |
| T92 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1797992797 |
|
|
Aug 13 05:36:47 PM PDT 24 |
Aug 13 05:37:14 PM PDT 24 |
11873979650 ps |
| T69 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2237602118 |
|
|
Aug 13 05:36:45 PM PDT 24 |
Aug 13 05:36:48 PM PDT 24 |
257253823 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.301413662 |
|
|
Aug 13 05:36:50 PM PDT 24 |
Aug 13 05:36:54 PM PDT 24 |
275354427 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1374897131 |
|
|
Aug 13 05:36:55 PM PDT 24 |
Aug 13 05:36:59 PM PDT 24 |
362745258 ps |
| T70 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1892899693 |
|
|
Aug 13 05:37:05 PM PDT 24 |
Aug 13 05:37:08 PM PDT 24 |
622427059 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.926379095 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:36:40 PM PDT 24 |
17830773 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.869147312 |
|
|
Aug 13 05:36:37 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
466349752 ps |
| T136 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.718109355 |
|
|
Aug 13 05:36:50 PM PDT 24 |
Aug 13 05:36:52 PM PDT 24 |
91129101 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.488204034 |
|
|
Aug 13 05:36:53 PM PDT 24 |
Aug 13 05:36:54 PM PDT 24 |
20773893 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.913656584 |
|
|
Aug 13 05:36:46 PM PDT 24 |
Aug 13 05:36:46 PM PDT 24 |
24273490 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2997443981 |
|
|
Aug 13 05:36:41 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
20676850 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1300304007 |
|
|
Aug 13 05:36:48 PM PDT 24 |
Aug 13 05:36:51 PM PDT 24 |
363764059 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.117651671 |
|
|
Aug 13 05:36:38 PM PDT 24 |
Aug 13 05:36:39 PM PDT 24 |
26004855 ps |
| T138 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1544647823 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:36:41 PM PDT 24 |
427796917 ps |
| T94 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3537208045 |
|
|
Aug 13 05:36:40 PM PDT 24 |
Aug 13 05:37:38 PM PDT 24 |
14161073550 ps |
| T134 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3033978717 |
|
|
Aug 13 05:37:05 PM PDT 24 |
Aug 13 05:37:07 PM PDT 24 |
192755337 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1267144235 |
|
|
Aug 13 05:36:58 PM PDT 24 |
Aug 13 05:36:59 PM PDT 24 |
13202617 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2538292926 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:36:43 PM PDT 24 |
240832089 ps |
| T959 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2332021405 |
|
|
Aug 13 05:36:55 PM PDT 24 |
Aug 13 05:36:56 PM PDT 24 |
23670716 ps |
| T960 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.547436112 |
|
|
Aug 13 05:36:41 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
11145947 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.472471798 |
|
|
Aug 13 05:36:54 PM PDT 24 |
Aug 13 05:36:58 PM PDT 24 |
735614816 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3885886674 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:36:40 PM PDT 24 |
23265636 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2432675146 |
|
|
Aug 13 05:36:41 PM PDT 24 |
Aug 13 05:36:43 PM PDT 24 |
411259519 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1293561444 |
|
|
Aug 13 05:36:42 PM PDT 24 |
Aug 13 05:36:43 PM PDT 24 |
45613094 ps |
| T965 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2229836526 |
|
|
Aug 13 05:37:02 PM PDT 24 |
Aug 13 05:37:03 PM PDT 24 |
24592438 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2356057640 |
|
|
Aug 13 05:36:51 PM PDT 24 |
Aug 13 05:37:18 PM PDT 24 |
3765332384 ps |
| T142 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2768214550 |
|
|
Aug 13 05:36:45 PM PDT 24 |
Aug 13 05:36:47 PM PDT 24 |
122429475 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3739402874 |
|
|
Aug 13 05:36:38 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
1201518365 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2620874839 |
|
|
Aug 13 05:36:43 PM PDT 24 |
Aug 13 05:36:44 PM PDT 24 |
14469128 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4014817386 |
|
|
Aug 13 05:36:50 PM PDT 24 |
Aug 13 05:36:51 PM PDT 24 |
29241114 ps |
| T968 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2084437371 |
|
|
Aug 13 05:36:54 PM PDT 24 |
Aug 13 05:36:55 PM PDT 24 |
60792632 ps |
| T137 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2379065687 |
|
|
Aug 13 05:36:40 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
499381037 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1224127386 |
|
|
Aug 13 05:36:48 PM PDT 24 |
Aug 13 05:36:49 PM PDT 24 |
33866363 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1257933669 |
|
|
Aug 13 05:36:37 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
128951532 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.265345316 |
|
|
Aug 13 05:36:54 PM PDT 24 |
Aug 13 05:36:57 PM PDT 24 |
356472230 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3696891600 |
|
|
Aug 13 05:36:52 PM PDT 24 |
Aug 13 05:36:53 PM PDT 24 |
39969033 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.994112326 |
|
|
Aug 13 05:36:55 PM PDT 24 |
Aug 13 05:36:56 PM PDT 24 |
35734947 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3471181894 |
|
|
Aug 13 05:36:37 PM PDT 24 |
Aug 13 05:36:41 PM PDT 24 |
85406015 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.346050052 |
|
|
Aug 13 05:37:09 PM PDT 24 |
Aug 13 05:37:13 PM PDT 24 |
368982688 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2392810238 |
|
|
Aug 13 05:36:40 PM PDT 24 |
Aug 13 05:36:44 PM PDT 24 |
55656940 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3262082382 |
|
|
Aug 13 05:36:46 PM PDT 24 |
Aug 13 05:36:47 PM PDT 24 |
71239395 ps |
| T978 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2175674650 |
|
|
Aug 13 05:36:54 PM PDT 24 |
Aug 13 05:36:56 PM PDT 24 |
47677796 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.685355760 |
|
|
Aug 13 05:36:37 PM PDT 24 |
Aug 13 05:36:38 PM PDT 24 |
52007354 ps |
| T980 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.946994537 |
|
|
Aug 13 05:37:03 PM PDT 24 |
Aug 13 05:37:04 PM PDT 24 |
78782081 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2615079618 |
|
|
Aug 13 05:37:04 PM PDT 24 |
Aug 13 05:37:05 PM PDT 24 |
26571315 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1199220844 |
|
|
Aug 13 05:36:56 PM PDT 24 |
Aug 13 05:37:01 PM PDT 24 |
125365896 ps |
| T983 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1096623578 |
|
|
Aug 13 05:36:55 PM PDT 24 |
Aug 13 05:36:59 PM PDT 24 |
1635227281 ps |
| T97 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4294858371 |
|
|
Aug 13 05:37:06 PM PDT 24 |
Aug 13 05:38:17 PM PDT 24 |
54226077396 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.360711107 |
|
|
Aug 13 05:37:06 PM PDT 24 |
Aug 13 05:37:10 PM PDT 24 |
1433995990 ps |
| T105 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1403738696 |
|
|
Aug 13 05:36:47 PM PDT 24 |
Aug 13 05:37:43 PM PDT 24 |
26073782826 ps |
| T985 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3487297029 |
|
|
Aug 13 05:36:46 PM PDT 24 |
Aug 13 05:36:51 PM PDT 24 |
41860859 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2041051827 |
|
|
Aug 13 05:36:53 PM PDT 24 |
Aug 13 05:36:56 PM PDT 24 |
700106897 ps |
| T106 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2054083002 |
|
|
Aug 13 05:36:49 PM PDT 24 |
Aug 13 05:37:20 PM PDT 24 |
14756937842 ps |
| T987 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1422839313 |
|
|
Aug 13 05:36:53 PM PDT 24 |
Aug 13 05:36:54 PM PDT 24 |
62508368 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.873703151 |
|
|
Aug 13 05:36:46 PM PDT 24 |
Aug 13 05:37:37 PM PDT 24 |
7288711222 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3019919339 |
|
|
Aug 13 05:36:43 PM PDT 24 |
Aug 13 05:36:45 PM PDT 24 |
180836292 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.207681174 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:37:05 PM PDT 24 |
3693380065 ps |
| T989 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1479630667 |
|
|
Aug 13 05:37:04 PM PDT 24 |
Aug 13 05:37:07 PM PDT 24 |
209096872 ps |
| T109 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1842549471 |
|
|
Aug 13 05:36:54 PM PDT 24 |
Aug 13 05:36:55 PM PDT 24 |
39666359 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1467124962 |
|
|
Aug 13 05:36:42 PM PDT 24 |
Aug 13 05:36:45 PM PDT 24 |
369571473 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3241181777 |
|
|
Aug 13 05:36:41 PM PDT 24 |
Aug 13 05:36:42 PM PDT 24 |
37777905 ps |
| T135 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1004768152 |
|
|
Aug 13 05:36:43 PM PDT 24 |
Aug 13 05:36:45 PM PDT 24 |
482083209 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1753963378 |
|
|
Aug 13 05:36:39 PM PDT 24 |
Aug 13 05:36:40 PM PDT 24 |
30685967 ps |
| T993 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3602794651 |
|
|
Aug 13 05:36:58 PM PDT 24 |
Aug 13 05:37:00 PM PDT 24 |
143181259 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3633525959 |
|
|
Aug 13 05:36:34 PM PDT 24 |
Aug 13 05:36:36 PM PDT 24 |
594210749 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4171321802 |
|
|
Aug 13 05:37:05 PM PDT 24 |
Aug 13 05:37:09 PM PDT 24 |
1570728967 ps |
| T996 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3907228946 |
|
|
Aug 13 05:36:46 PM PDT 24 |
Aug 13 05:36:47 PM PDT 24 |
26213571 ps |
| T997 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1922763282 |
|
|
Aug 13 05:36:54 PM PDT 24 |
Aug 13 05:36:57 PM PDT 24 |
354725633 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2660759684 |
|
|
Aug 13 05:36:59 PM PDT 24 |
Aug 13 05:37:03 PM PDT 24 |
347626349 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3841258582 |
|
|
Aug 13 05:36:51 PM PDT 24 |
Aug 13 05:37:16 PM PDT 24 |
8334333426 ps |
| T110 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1780817077 |
|
|
Aug 13 05:36:52 PM PDT 24 |
Aug 13 05:36:53 PM PDT 24 |
11526152 ps |
| T1000 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3646915858 |
|
|
Aug 13 05:36:58 PM PDT 24 |
Aug 13 05:37:02 PM PDT 24 |
760350002 ps |
| T1001 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2351355798 |
|
|
Aug 13 05:36:50 PM PDT 24 |
Aug 13 05:36:52 PM PDT 24 |
839859755 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.809755632 |
|
|
Aug 13 05:36:45 PM PDT 24 |
Aug 13 05:36:46 PM PDT 24 |
17151062 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2889579533 |
|
|
Aug 13 05:36:37 PM PDT 24 |
Aug 13 05:36:38 PM PDT 24 |
52986094 ps |
| T111 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1789871936 |
|
|
Aug 13 05:36:37 PM PDT 24 |
Aug 13 05:37:31 PM PDT 24 |
7607071243 ps |
| T1004 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.157600317 |
|
|
Aug 13 05:37:12 PM PDT 24 |
Aug 13 05:38:12 PM PDT 24 |
32011581343 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3657853560 |
|
|
Aug 13 05:36:38 PM PDT 24 |
Aug 13 05:36:39 PM PDT 24 |
410285275 ps |
| T1006 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3123135666 |
|
|
Aug 13 05:36:57 PM PDT 24 |
Aug 13 05:36:58 PM PDT 24 |
22034510 ps |