Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	341010878	1			T1	171270		T2	2766		T3	374732
instr_valid_dis	305104200	1			T1	171270		T2	2766		T3	374732
instr_en	24030703	1			T20	296042		T56	358902		T133	128004

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	16990070	1			T18	53126		T26	24178		T20	59258
sram_ifetch_valid_disable	295552727	1			T1	171270		T2	2766		T3	374732
sram_ifetch_enable	28468081	1			T9	35910		T18	199880		T26	876

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	341010878	1			T1	171270		T2	2766		T3	374732
hw_debug_en_valid_off	300017161	1			T1	171270		T2	2766		T3	374732
hw_debug_en_on	30507617	1			T18	189834		T26	156890		T20	34900

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	295552727	1			T1	171270		T2	2766		T3	374732
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	284026884	1			T1	171270		T2	2766		T3	374732
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7970818	1			T20	55330		T56	147664		T133	76904
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3512340	1			T26	3714		T20	40090		T133	4040
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1444522	1			T26	3714		T143	21048		T135	11530
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1486152	1			T20	40090		T133	4040		T21	20164
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	10621476	1			T18	14940		T26	20464		T56	6192
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1829288	1			T18	14940		T26	20464		T37	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4660690	1			T56	6192		T21	30058		T135	9376
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8612852	1			T18	94446		T26	135550		T20	20262
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3963930	1			T18	94446		T26	135550		T133	51722
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3299886	1			T20	20262		T56	100246		T133	76842

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9043133	1			T20	181454		T56	192268		T133	47060
lc_exec_en	11273289	1			T18	80448		T26	876		T20	14638
valid_exec_dis	300011297	1			T1	171270		T2	2766		T3	374732
invalid_exec_dis	45458151	1			T9	35910		T18	253006		T26	25054