Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	141843902	1			T1	77850		T2	463		T3	170355
triple_byte_access	2828731	1			T1	1577		T2	7		T3	3345
halfword_access	4332188	1			T1	2353		T2	14		T3	5136
byte_access	6041909	1			T1	3135		T2	14		T3	6826
zero_access	1804707	1			T1	720		T2	8		T3	1704

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78172971

1

T1

42829

T2

232

T3

93539

auto[1]

78678466

1

T1

42806

T2

274

T3

93827

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70540351	1			T1	38928		T2	211		T3	85142
auto[0]	triple_byte_access	1354641	1			T1	802		T2	4		T3	1618
auto[0]	halfword_access	2120045	1			T1	1183		T2	10		T3	2554
auto[0]	byte_access	3089789	1			T1	1544		T2	5		T3	3397
auto[0]	zero_access	1068145	1			T1	372		T2	2		T3	828
auto[1]	word_access	71303551	1			T1	38922		T2	252		T3	85213
auto[1]	triple_byte_access	1474090	1			T1	775		T2	3		T3	1727
auto[1]	halfword_access	2212143	1			T1	1170		T2	4		T3	2582
auto[1]	byte_access	2952120	1			T1	1591		T2	9		T3	3429
auto[1]	zero_access	736562	1			T1	348		T2	6		T3	876