SRAM_CTRL/RET Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.763m	10.273ms	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	16.517us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	105.058us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.860s	322.856us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	16.157us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.570s	218.287us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	105.058us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	16.157us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.540s	3.627ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.630s	901.308us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	32.041m	15.127ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.043m	4.117ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.310m	10.185ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.649m	5.142ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.460s	1.564ms	50	50	100.00
V2	executable	sram_ctrl_executable	38.727m	31.051ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.628m	10.233ms	49	50	98.00
		sram_ctrl_partial_access_b2b	10.780m	25.185ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.738m	587.841us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.416m	619.339us	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.414m	114.059ms	47	50	94.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.510s	89.136us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.605h	16.104ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.690s	15.686us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.050s	1.646ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.050s	1.646ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	16.517us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	105.058us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	16.157us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	57.198us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	16.517us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	105.058us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	16.157us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	57.198us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	12.650s	480.533us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.900s	768.897us	5	5	100.00
		sram_ctrl_tl_intg_err	2.430s	269.458us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.900s	768.897us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.430s	269.458us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.414m	114.059ms	47	50	94.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	105.058us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	38.727m	31.051ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	38.727m	31.051ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	38.727m	31.051ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.460s	1.564ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	12.650s	480.533us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.763m	10.273ms	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.763m	10.273ms	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	38.727m	31.051ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.900s	768.897us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.460s	1.564ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.900s	768.897us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.900s	768.897us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.763m	10.273ms	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.900s	768.897us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.826h	5.252ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 4 failures:

Test sram_ctrl_regwen has 3 failures.

2.sram_ctrl_regwen.1086031846
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest/run.log

  UVM_FATAL @ 149815437335 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x2ca993fd
  UVM_INFO @ 149815437335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.sram_ctrl_regwen.4200686161
Line 253, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest/run.log

  UVM_FATAL @ 63934560150 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x17953011
  UVM_INFO @ 63934560150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test sram_ctrl_stress_all has 1 failures.

19.sram_ctrl_stress_all.2492402222
Line 259, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 72131779695 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x2575b261
  UVM_INFO @ 72131779695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:

Test sram_ctrl_partial_access has 1 failures.

37.sram_ctrl_partial_access.821062302
Line 241, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest/run.log

  UVM_FATAL @ 10233088873 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6cce14e2
  UVM_INFO @ 10233088873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sram_ctrl_smoke has 1 failures.

49.sram_ctrl_smoke.2262125453
Line 241, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10272776058 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xfb637df7
  UVM_INFO @ 10272776058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 0.sram_ctrl_stress_all.2053889580
    Line 245, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 21601647047 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xdb6031d4
  UVM_INFO @ 21601647047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```