SRAM_CTRL/RET Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.141m	4.822ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	15.803us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	38.404us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.590s	41.091us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	32.811us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.430s	43.036us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	38.404us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	32.811us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.650s	8.185ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.730s	169.567us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.251m	20.777ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.580m	16.546ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.421m	5.480ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.228m	8.211ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.100s	2.574ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.731m	200.000ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.697m	2.919ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.064m	27.828ms	49	50	98.00
V2	max_throughput	sram_ctrl_max_throughput	2.087m	456.292us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.368m	329.106us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.886m	35.833ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.270s	33.651us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.722h	61.520ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.720s	18.207us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.890s	1.067ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.890s	1.067ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	15.803us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	38.404us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	32.811us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	74.804us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	15.803us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	38.404us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	32.811us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	74.804us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	9.990s	4.064ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.560s	871.020us	5	5	100.00
		sram_ctrl_tl_intg_err	2.280s	1.894ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.560s	871.020us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.280s	1.894ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.886m	35.833ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	38.404us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.731m	200.000ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.731m	200.000ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.731m	200.000ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.100s	2.574ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	9.990s	4.064ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.141m	4.822ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.141m	4.822ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.731m	200.000ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.560s	871.020us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.100s	2.574ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.560s	871.020us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.560s	871.020us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.141m	4.822ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.560s	871.020us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.531h	2.134ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:

Test sram_ctrl_stress_all has 1 failures.

3.sram_ctrl_stress_all.4286110639
Line 256, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 48201621382 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x8b8a58c3
  UVM_INFO @ 48201621382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sram_ctrl_regwen has 1 failures.

42.sram_ctrl_regwen.1874571857
Line 255, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest/run.log

  UVM_FATAL @ 93573776776 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x1faea53c
  UVM_INFO @ 93573776776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_executable has 1 failures.
  - 10.sram_ctrl_executable.1560249198
    Line 321, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_partial_access_b2b has 1 failures.
  - 31.sram_ctrl_partial_access_b2b.1606136161
    Line 249, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```