SRAM_CTRL/RET Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.776m 3.007ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.770s 24.501us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.700s 12.050us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.950s 620.986us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.780s 15.943us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.090s 63.323us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.700s 12.050us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 15.943us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 10.710s 2.266ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.360s 409.663us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 23.182m 19.916ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.659m 44.543ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.538m 108.057ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 37.023m 86.068ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 19.550s 812.575us 50 50 100.00
V2 executable sram_ctrl_executable 26.377m 15.524ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.191m 429.395us 50 50 100.00
sram_ctrl_partial_access_b2b 9.203m 87.027ms 49 50 98.00
V2 max_throughput sram_ctrl_max_throughput 2.816m 154.532us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.699m 151.584us 50 50 100.00
V2 regwen sram_ctrl_regwen 23.034m 54.987ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.370s 37.519us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.600h 260.636ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.760s 19.856us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.510s 633.253us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.510s 633.253us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.770s 24.501us 5 5 100.00
sram_ctrl_csr_rw 0.700s 12.050us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 15.943us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.780s 157.446us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.770s 24.501us 5 5 100.00
sram_ctrl_csr_rw 0.700s 12.050us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 15.943us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.780s 157.446us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 10.420s 384.395us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.030s 819.740us 5 5 100.00
sram_ctrl_tl_intg_err 2.590s 435.395us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.030s 819.740us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.590s 435.395us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 23.034m 54.987ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.700s 12.050us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 26.377m 15.524ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 26.377m 15.524ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 26.377m 15.524ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 19.550s 812.575us 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 10.420s 384.395us 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.776m 3.007ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.776m 3.007ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 26.377m 15.524ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.030s 819.740us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 19.550s 812.575us 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.030s 819.740us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.030s 819.740us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.776m 3.007ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.030s 819.740us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.450h 2.245ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.26 99.16 93.54 100.00 70.00 97.41 99.70 100.00

Failure Buckets

Past Results