SRAM_CTRL/RET Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.950m 635.412us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.670s 37.996us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.670s 12.939us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.700s 292.561us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.700s 16.487us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.260s 79.135us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.670s 12.939us 20 20 100.00
sram_ctrl_csr_aliasing 0.700s 16.487us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 10.620s 3.963ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.730s 175.589us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 29.723m 44.032ms 48 50 96.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.933m 17.267ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.655m 54.065ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.632m 10.422ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 15.040s 1.887ms 50 50 100.00
V2 executable sram_ctrl_executable 32.477m 28.739ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.367m 684.871us 50 50 100.00
sram_ctrl_partial_access_b2b 9.427m 82.000ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.365m 229.037us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.704m 2.930ms 50 50 100.00
V2 regwen sram_ctrl_regwen 28.826m 98.510ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.210s 39.650us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.754h 68.317ms 50 50 100.00
V2 alert_test sram_ctrl_alert_test 0.680s 16.409us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.830s 1.253ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.830s 1.253ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.670s 37.996us 5 5 100.00
sram_ctrl_csr_rw 0.670s 12.939us 20 20 100.00
sram_ctrl_csr_aliasing 0.700s 16.487us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 88.118us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.670s 37.996us 5 5 100.00
sram_ctrl_csr_rw 0.670s 12.939us 20 20 100.00
sram_ctrl_csr_aliasing 0.700s 16.487us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 88.118us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 10.660s 397.403us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.140s 873.818us 5 5 100.00
sram_ctrl_tl_intg_err 2.930s 2.010ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.140s 873.818us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.930s 2.010ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.826m 98.510ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.670s 12.939us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 32.477m 28.739ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 32.477m 28.739ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 32.477m 28.739ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 15.040s 1.887ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 10.660s 397.403us 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.950m 635.412us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.950m 635.412us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 32.477m 28.739ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.140s 873.818us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 15.040s 1.887ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.140s 873.818us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.140s 873.818us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.950m 635.412us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.140s 873.818us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.891h 4.191ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1038 1040 99.81

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.26 99.16 93.54 100.00 70.00 97.41 99.70 100.00

Failure Buckets

Past Results