Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	115969663	1			T9	80		T18	40		T23	1554
instr_valid_dis	91531690	1			T9	57		T18	30		T23	1554
instr_en	16624509	1			T9	4		T1	131894		T13	474564

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	8864476	1			T1	104024		T11	88990		T13	85058
sram_ifetch_valid_disable	90392970	1			T9	80		T18	40		T23	1554
sram_ifetch_enable	16712217	1			T1	237274		T11	80532		T13	232794

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	115969663	1			T9	80		T18	40		T23	1554
hw_debug_en_valid_off	90633251	1			T9	80		T18	40		T23	1554
hw_debug_en_on	16045032	1			T1	172076		T11	211984		T13	219650

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	90392970	1			T9	80		T18	40		T23	1554
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	81048633	1			T9	57		T18	30		T23	1554
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	6250797	1			T9	4		T1	87944		T13	156760
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3556721	1			T11	2440		T13	28800		T16	53942
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1713914	1			T11	2440		T40	16094		T35	30018
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1334853	1			T13	28800		T16	53942		T49	31758
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3240599	1			T1	104024		T11	86550		T13	56258
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1266852	1			T1	14502		T11	86550		T49	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1412318	1			T13	56258		T16	53046		T40	4564
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6257907	1			T1	18812		T11	44902		T13	103832
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2580234	1			T11	44902		T49	34928		T35	55178
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2453332	1			T13	103832		T16	78364		T49	8236

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6915371	1			T1	43950		T13	232746		T16	338590
lc_exec_en	6546526	1			T1	49240		T11	80532		T13	59560
valid_exec_dis	87294669	1			T9	80		T18	40		T23	1554
invalid_exec_dis	25576693	1			T1	341298		T11	169522		T13	317852