Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg
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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
escalated_cp 2 0 2 100.00 100 1 1 2
key_seed_valid_cp 2 0 2 100.00 100 1 1 2


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_seed_valid_cross 4 0 4 100.00 100 1 1 0


Summary for Variable escalated_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for escalated_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6538 1 T9 21 T18 11 T1 14
auto[1] 682 1 T5 20 T6 10 T7 10



Summary for Variable key_seed_valid_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_seed_valid_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3673 1 T9 10 T18 8 T1 7
auto[1] 3547 1 T9 11 T18 3 T1 7



Summary for Cross key_seed_valid_cross

Samples crossed: key_seed_valid_cp escalated_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key_seed_valid_cross

Bins
key_seed_valid_cpescalated_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 3324 1 T9 10 T18 8 T1 7
auto[0] auto[1] 349 1 T5 9 T6 4 T7 6
auto[1] auto[0] 3214 1 T9 11 T18 3 T1 7
auto[1] auto[1] 333 1 T5 11 T6 6 T7 4

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