Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	35781789	1			T9	40		T18	20		T1	81557
triple_byte_access	1887517	1			T1	1575		T3	48		T4	95
halfword_access	2833305	1			T1	2477		T3	81		T4	161
byte_access	3781075	1			T1	3221		T3	125		T4	207
zero_access	951770	1			T1	826		T3	21		T4	49

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22574373

1

T9

40

T18

20

T1

44734

auto[1]

22661083

1

T1

44922

T2

3569

T3

1486

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	17851184	1			T9	40		T18	20		T1	40708
auto[0]	triple_byte_access	941709	1			T1	775		T3	31		T4	46
auto[0]	halfword_access	1414896	1			T1	1255		T3	43		T4	79
auto[0]	byte_access	1888642	1			T1	1591		T3	56		T4	111
auto[0]	zero_access	477942	1			T1	405		T3	12		T4	24
auto[1]	word_access	17930605	1			T1	40849		T2	3569		T3	1353
auto[1]	triple_byte_access	945808	1			T1	800		T3	17		T4	49
auto[1]	halfword_access	1418409	1			T1	1222		T3	38		T4	82
auto[1]	byte_access	1892433	1			T1	1630		T3	69		T4	96
auto[1]	zero_access	473828	1			T1	421		T3	9		T4	25