Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	142474186	1			T1	10956		T2	266338		T3	86016
instr_valid_dis	106119522	1			T1	10956		T2	266338		T3	86016
instr_en	26589772	1			T4	288168		T8	75658		T9	24548

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11234200	1			T4	108866		T8	81454		T9	31670
sram_ifetch_valid_disable	108515980	1			T1	10956		T2	266338		T3	86016
sram_ifetch_enable	22724006	1			T4	276298		T8	154164		T9	41026

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	142474186	1			T1	10956		T2	266338		T3	86016
hw_debug_en_valid_off	108208144	1			T1	10956		T2	266338		T3	86016
hw_debug_en_on	22039810	1			T4	276234		T8	165850		T9	14698

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	108515980	1			T1	10956		T2	266338		T3	86016
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	93806114	1			T1	10956		T2	266338		T3	86016
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10586526	1			T4	94372		T8	40800		T9	7954
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3782706	1			T4	52156		T9	31670		T23	16038
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1411972	1			T4	52156		T9	15158		T68	48602
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1742204	1			T70	9066		T24	26924		T108	2730
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5165896	1			T4	56710		T8	81454		T13	81392
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1951476	1			T8	81454		T23	4258		T70	82254
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2352338	1			T4	40798		T68	42066		T24	146166
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8344800	1			T4	65946		T8	52926		T9	14356
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3034278	1			T4	50022		T8	12126		T9	14356
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3699578	1			T4	13704		T8	40800		T69	44684

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10963224	1			T4	152998		T8	34858		T9	16594
lc_exec_en	8529114	1			T4	153578		T8	31470		T9	342
valid_exec_dis	103717528	1			T1	10956		T2	266338		T3	86016
invalid_exec_dis	33958206	1			T4	385164		T8	235618		T9	72696