Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42380734	1			T1	4985		T2	115486		T3	43008
triple_byte_access	2407455	1			T1	91		T2	2336		T4	2715
halfword_access	3619312	1			T1	155		T2	3449		T4	4138
byte_access	4829559	1			T1	192		T2	4719		T4	5391
zero_access	1216947	1			T1	55		T2	1148		T4	1374

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27185703

1

T1

2710

T2

63536

T3

21504

auto[1]

27268304

1

T1

2768

T2

63602

T3

21504

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21152093	1			T1	2461		T2	57683		T3	21504
auto[0]	triple_byte_access	1200593	1			T1	44		T2	1178		T4	1353
auto[0]	halfword_access	1806652	1			T1	92		T2	1748		T4	2073
auto[0]	byte_access	2413345	1			T1	91		T2	2340		T4	2750
auto[0]	zero_access	613020	1			T1	22		T2	587		T4	682
auto[1]	word_access	21228641	1			T1	2524		T2	57803		T3	21504
auto[1]	triple_byte_access	1206862	1			T1	47		T2	1158		T4	1362
auto[1]	halfword_access	1812660	1			T1	63		T2	1701		T4	2065
auto[1]	byte_access	2416214	1			T1	101		T2	2379		T4	2641
auto[1]	zero_access	603927	1			T1	33		T2	561		T4	692