Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	143089848	1			T1	1960		T2	1934		T3	579470
instr_valid_dis	110975849	1			T1	1960		T2	1934		T10	3910
instr_en	24023396	1			T3	579470		T13	82960		T8	184536

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11218600	1			T3	63944		T13	16698		T7	109042
sram_ifetch_valid_disable	110439144	1			T1	1960		T2	1934		T3	156868
sram_ifetch_enable	21432104	1			T3	358658		T13	62152		T8	211166

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	143089848	1			T1	1960		T2	1934		T3	579470
hw_debug_en_valid_off	110844590	1			T1	1960		T2	1934		T3	260468
hw_debug_en_on	20959468	1			T3	235688		T13	57898		T7	137190

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110439144	1			T1	1960		T2	1934		T3	156868
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	96796783	1			T1	1960		T2	1934		T10	3910
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10383712	1			T3	156868		T13	4110		T8	51152
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4264276	1			T3	44712		T7	16638		T8	32622
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1878084	1			T7	16638		T8	15362		T98	29890
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1730912	1			T3	44712		T8	17260		T23	14294
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4447556	1			T3	19232		T7	92404		T8	42960
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1967644	1			T7	92404		T23	18130		T101	33992
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1769910	1			T3	19232		T8	23690		T98	268452
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8220234	1			T3	56158		T13	4110		T7	44786
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3544620	1			T7	44786		T8	32288		T23	17182
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3471766	1			T3	56158		T13	4110		T8	30984

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9146798	1			T3	358658		T13	62152		T8	92434
lc_exec_en	8291678	1			T3	160298		T13	53788		T8	92528
valid_exec_dis	106368070	1			T1	1960		T2	1934		T3	52610
invalid_exec_dis	32650704	1			T3	422602		T13	78850		T7	109042