Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42547388	1			T1	57		T2	56		T3	104999
triple_byte_access	2460246	1			T1	124		T2	136		T3	2084
halfword_access	3696589	1			T1	214		T2	239		T3	3136
byte_access	4933426	1			T1	374		T2	370		T3	4182
zero_access	1243648	1			T1	211		T2	166		T3	1054

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27399156

1

T1

378

T2

372

T3

57622

auto[1]

27482141

1

T1

602

T2

595

T3

57833

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21237011	1			T1	3		T2	1		T3	52452
auto[0]	triple_byte_access	1227317	1			T1	19		T2	16		T3	1010
auto[0]	halfword_access	1844388	1			T1	48		T2	62		T3	1559
auto[0]	byte_access	2465389	1			T1	155		T2	161		T3	2096
auto[0]	zero_access	625051	1			T1	153		T2	132		T3	505
auto[1]	word_access	21310377	1			T1	54		T2	55		T3	52547
auto[1]	triple_byte_access	1232929	1			T1	105		T2	120		T3	1074
auto[1]	halfword_access	1852201	1			T1	166		T2	177		T3	1577
auto[1]	byte_access	2468037	1			T1	219		T2	209		T3	2086
auto[1]	zero_access	618597	1			T1	58		T2	34		T3	549