| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.26 | 100.00 | 97.48 | 100.00 | 100.00 | 99.14 | 99.70 | 98.52 |
| T802 | /workspace/coverage/default/12.sram_ctrl_executable.895489930 | Feb 21 01:19:17 PM PST 24 | Feb 21 01:34:16 PM PST 24 | 139991461950 ps | ||
| T803 | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.37675026 | Feb 21 01:19:16 PM PST 24 | Feb 21 01:23:41 PM PST 24 | 5572199549 ps | ||
| T804 | /workspace/coverage/default/44.sram_ctrl_stress_all.4236108050 | Feb 21 01:22:26 PM PST 24 | Feb 21 02:21:59 PM PST 24 | 47672585472 ps | ||
| T805 | /workspace/coverage/default/11.sram_ctrl_stress_all.835006076 | Feb 21 01:19:41 PM PST 24 | Feb 21 02:23:28 PM PST 24 | 258351968599 ps | ||
| T806 | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1043557476 | Feb 21 01:19:16 PM PST 24 | Feb 21 01:19:21 PM PST 24 | 234726889 ps | ||
| T807 | /workspace/coverage/default/31.sram_ctrl_alert_test.1043786275 | Feb 21 01:20:54 PM PST 24 | Feb 21 01:20:55 PM PST 24 | 31589863 ps | ||
| T808 | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.516694677 | Feb 21 01:20:31 PM PST 24 | Feb 21 01:20:36 PM PST 24 | 129464907 ps | ||
| T809 | /workspace/coverage/default/45.sram_ctrl_partial_access.2853377457 | Feb 21 01:22:24 PM PST 24 | Feb 21 01:22:42 PM PST 24 | 355145929 ps | ||
| T810 | /workspace/coverage/default/0.sram_ctrl_ram_cfg.928270146 | Feb 21 01:18:17 PM PST 24 | Feb 21 01:18:18 PM PST 24 | 211134169 ps | ||
| T811 | /workspace/coverage/default/39.sram_ctrl_bijection.1489379843 | Feb 21 01:21:24 PM PST 24 | Feb 21 01:22:10 PM PST 24 | 2700492900 ps | ||
| T812 | /workspace/coverage/default/11.sram_ctrl_smoke.2825130513 | Feb 21 01:19:30 PM PST 24 | Feb 21 01:20:19 PM PST 24 | 782532192 ps | ||
| T813 | /workspace/coverage/default/3.sram_ctrl_mem_walk.3581482094 | Feb 21 01:19:00 PM PST 24 | Feb 21 01:19:13 PM PST 24 | 6238815085 ps | ||
| T814 | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2312186503 | Feb 21 01:19:19 PM PST 24 | Feb 21 01:23:07 PM PST 24 | 2263966493 ps | ||
| T815 | /workspace/coverage/default/40.sram_ctrl_executable.3840749890 | Feb 21 01:21:34 PM PST 24 | Feb 21 01:37:47 PM PST 24 | 9051289845 ps | ||
| T816 | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2086538946 | Feb 21 01:22:27 PM PST 24 | Feb 21 01:27:55 PM PST 24 | 13017319033 ps | ||
| T817 | /workspace/coverage/default/22.sram_ctrl_regwen.1638118837 | Feb 21 01:19:57 PM PST 24 | Feb 21 01:31:58 PM PST 24 | 3185876183 ps | ||
| T818 | /workspace/coverage/default/18.sram_ctrl_ram_cfg.130244029 | Feb 21 01:20:03 PM PST 24 | Feb 21 01:20:04 PM PST 24 | 31510709 ps | ||
| T819 | /workspace/coverage/default/46.sram_ctrl_regwen.586839695 | Feb 21 01:22:30 PM PST 24 | Feb 21 01:38:23 PM PST 24 | 3002071330 ps | ||
| T820 | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2012234469 | Feb 21 01:21:47 PM PST 24 | Feb 21 01:40:56 PM PST 24 | 148077436390 ps | ||
| T821 | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2022731116 | Feb 21 01:19:37 PM PST 24 | Feb 21 01:33:29 PM PST 24 | 9257296265 ps | ||
| T822 | /workspace/coverage/default/22.sram_ctrl_smoke.2221207287 | Feb 21 01:19:56 PM PST 24 | Feb 21 01:21:38 PM PST 24 | 120759742 ps | ||
| T823 | /workspace/coverage/default/4.sram_ctrl_lc_escalation.2790742780 | Feb 21 01:18:58 PM PST 24 | Feb 21 01:19:04 PM PST 24 | 740981999 ps | ||
| T824 | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2077856975 | Feb 21 01:21:18 PM PST 24 | Feb 21 01:41:28 PM PST 24 | 42182972666 ps | ||
| T825 | /workspace/coverage/default/29.sram_ctrl_mem_walk.1486396163 | Feb 21 01:20:29 PM PST 24 | Feb 21 01:20:37 PM PST 24 | 140672083 ps | ||
| T826 | /workspace/coverage/default/26.sram_ctrl_max_throughput.3045736104 | Feb 21 01:20:19 PM PST 24 | Feb 21 01:20:21 PM PST 24 | 148766167 ps | ||
| T827 | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2875265714 | Feb 21 01:19:39 PM PST 24 | Feb 21 01:25:46 PM PST 24 | 58423978505 ps | ||
| T828 | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2934159706 | Feb 21 01:21:30 PM PST 24 | Feb 21 01:31:46 PM PST 24 | 2069290122 ps | ||
| T829 | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3538080296 | Feb 21 01:19:00 PM PST 24 | Feb 21 01:20:20 PM PST 24 | 126381767 ps | ||
| T830 | /workspace/coverage/default/37.sram_ctrl_bijection.405755577 | Feb 21 01:21:18 PM PST 24 | Feb 21 01:21:33 PM PST 24 | 1151931610 ps | ||
| T831 | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.4069911225 | Feb 21 01:19:56 PM PST 24 | Feb 21 01:29:21 PM PST 24 | 9635933881 ps | ||
| T832 | /workspace/coverage/default/24.sram_ctrl_lc_escalation.851933289 | Feb 21 01:20:10 PM PST 24 | Feb 21 01:20:20 PM PST 24 | 388944500 ps | ||
| T833 | /workspace/coverage/default/11.sram_ctrl_bijection.1193348135 | Feb 21 01:19:40 PM PST 24 | Feb 21 01:20:03 PM PST 24 | 5032611923 ps | ||
| T834 | /workspace/coverage/default/31.sram_ctrl_bijection.714089624 | Feb 21 01:20:43 PM PST 24 | Feb 21 01:21:14 PM PST 24 | 500619230 ps | ||
| T835 | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.521768245 | Feb 21 01:20:49 PM PST 24 | Feb 21 01:26:19 PM PST 24 | 4484366288 ps | ||
| T836 | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.969147898 | Feb 21 01:22:32 PM PST 24 | Feb 21 01:23:11 PM PST 24 | 217583798 ps | ||
| T837 | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4109474118 | Feb 21 01:18:46 PM PST 24 | Feb 21 01:22:19 PM PST 24 | 9064191749 ps | ||
| T838 | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1615510830 | Feb 21 01:19:04 PM PST 24 | Feb 21 01:24:35 PM PST 24 | 53694235224 ps | ||
| T839 | /workspace/coverage/default/4.sram_ctrl_bijection.1312167212 | Feb 21 01:18:44 PM PST 24 | Feb 21 01:19:34 PM PST 24 | 3212009881 ps | ||
| T840 | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3611588450 | Feb 21 01:21:54 PM PST 24 | Feb 21 01:40:35 PM PST 24 | 6558779677 ps | ||
| T841 | /workspace/coverage/default/0.sram_ctrl_alert_test.3396168233 | Feb 21 01:18:20 PM PST 24 | Feb 21 01:18:22 PM PST 24 | 60236769 ps | ||
| T842 | /workspace/coverage/default/35.sram_ctrl_lc_escalation.2931900945 | Feb 21 01:21:12 PM PST 24 | Feb 21 01:21:23 PM PST 24 | 1078570282 ps | ||
| T843 | /workspace/coverage/default/10.sram_ctrl_partial_access.1497690787 | Feb 21 01:19:18 PM PST 24 | Feb 21 01:19:50 PM PST 24 | 827633855 ps | ||
| T844 | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1949361548 | Feb 21 01:21:32 PM PST 24 | Feb 21 01:40:58 PM PST 24 | 20257959303 ps | ||
| T845 | /workspace/coverage/default/6.sram_ctrl_ram_cfg.2827747270 | Feb 21 01:19:15 PM PST 24 | Feb 21 01:19:17 PM PST 24 | 376702745 ps | ||
| T846 | /workspace/coverage/default/6.sram_ctrl_bijection.3309284243 | Feb 21 01:19:01 PM PST 24 | Feb 21 01:20:07 PM PST 24 | 1064815846 ps | ||
| T847 | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1306393657 | Feb 21 01:18:58 PM PST 24 | Feb 21 01:19:04 PM PST 24 | 1806048429 ps | ||
| T848 | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1928728763 | Feb 21 01:20:22 PM PST 24 | Feb 21 01:26:21 PM PST 24 | 4910020885 ps | ||
| T849 | /workspace/coverage/default/37.sram_ctrl_alert_test.1442796088 | Feb 21 01:21:17 PM PST 24 | Feb 21 01:21:18 PM PST 24 | 23121785 ps | ||
| T850 | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3246310170 | Feb 21 01:19:54 PM PST 24 | Feb 21 01:20:01 PM PST 24 | 345354645 ps | ||
| T851 | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2239183384 | Feb 21 01:19:45 PM PST 24 | Feb 21 01:24:32 PM PST 24 | 47080593462 ps | ||
| T852 | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.282540710 | Feb 21 01:19:58 PM PST 24 | Feb 21 01:27:24 PM PST 24 | 66161481677 ps | ||
| T853 | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.926112070 | Feb 21 01:22:28 PM PST 24 | Feb 21 01:26:41 PM PST 24 | 5247989476 ps | ||
| T854 | /workspace/coverage/default/30.sram_ctrl_stress_all.2496358225 | Feb 21 01:20:43 PM PST 24 | Feb 21 02:51:13 PM PST 24 | 122450553202 ps | ||
| T855 | /workspace/coverage/default/2.sram_ctrl_smoke.66413449 | Feb 21 01:19:01 PM PST 24 | Feb 21 01:19:16 PM PST 24 | 60466723 ps | ||
| T856 | /workspace/coverage/default/19.sram_ctrl_max_throughput.3124733914 | Feb 21 01:19:51 PM PST 24 | Feb 21 01:21:09 PM PST 24 | 934757291 ps | ||
| T857 | /workspace/coverage/default/21.sram_ctrl_executable.2639857248 | Feb 21 01:19:59 PM PST 24 | Feb 21 01:36:59 PM PST 24 | 35773629522 ps | ||
| T858 | /workspace/coverage/default/40.sram_ctrl_bijection.1159522126 | Feb 21 01:21:28 PM PST 24 | Feb 21 01:22:02 PM PST 24 | 12979338929 ps | ||
| T859 | /workspace/coverage/default/42.sram_ctrl_partial_access.2625671918 | Feb 21 01:21:38 PM PST 24 | Feb 21 01:21:53 PM PST 24 | 209712097 ps | ||
| T860 | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.227610228 | Feb 21 01:20:17 PM PST 24 | Feb 21 01:25:06 PM PST 24 | 2260043392 ps | ||
| T861 | /workspace/coverage/default/15.sram_ctrl_bijection.2774605377 | Feb 21 01:19:26 PM PST 24 | Feb 21 01:19:55 PM PST 24 | 6617694454 ps | ||
| T862 | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1077489629 | Feb 21 01:21:19 PM PST 24 | Feb 21 01:34:23 PM PST 24 | 9165487947 ps | ||
| T863 | /workspace/coverage/default/21.sram_ctrl_mem_walk.1885414859 | Feb 21 01:20:01 PM PST 24 | Feb 21 01:20:07 PM PST 24 | 284913130 ps | ||
| T864 | /workspace/coverage/default/20.sram_ctrl_ram_cfg.1874137393 | Feb 21 01:19:54 PM PST 24 | Feb 21 01:19:58 PM PST 24 | 25878956 ps | ||
| T865 | /workspace/coverage/default/40.sram_ctrl_regwen.3535001346 | Feb 21 01:21:33 PM PST 24 | Feb 21 01:50:46 PM PST 24 | 38935936909 ps | ||
| T866 | /workspace/coverage/default/9.sram_ctrl_alert_test.2280378924 | Feb 21 01:19:08 PM PST 24 | Feb 21 01:19:09 PM PST 24 | 32295010 ps | ||
| T867 | /workspace/coverage/default/10.sram_ctrl_mem_walk.3738713744 | Feb 21 01:19:30 PM PST 24 | Feb 21 01:19:39 PM PST 24 | 312127385 ps | ||
| T868 | /workspace/coverage/default/31.sram_ctrl_max_throughput.841605403 | Feb 21 01:20:44 PM PST 24 | Feb 21 01:22:14 PM PST 24 | 233248847 ps | ||
| T869 | /workspace/coverage/default/35.sram_ctrl_executable.3313073727 | Feb 21 01:21:09 PM PST 24 | Feb 21 01:36:30 PM PST 24 | 12147765856 ps | ||
| T870 | /workspace/coverage/default/12.sram_ctrl_ram_cfg.3679922603 | Feb 21 01:19:56 PM PST 24 | Feb 21 01:20:00 PM PST 24 | 85407264 ps | ||
| T871 | /workspace/coverage/default/34.sram_ctrl_regwen.3815096100 | Feb 21 01:21:05 PM PST 24 | Feb 21 01:25:40 PM PST 24 | 24035582305 ps | ||
| T872 | /workspace/coverage/default/7.sram_ctrl_partial_access.2866220293 | Feb 21 01:18:59 PM PST 24 | Feb 21 01:19:07 PM PST 24 | 500318005 ps | ||
| T873 | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1750060773 | Feb 21 01:19:24 PM PST 24 | Feb 21 01:19:37 PM PST 24 | 629191555 ps | ||
| T874 | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2340348576 | Feb 21 01:22:33 PM PST 24 | Feb 21 01:22:39 PM PST 24 | 688456896 ps | ||
| T875 | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3308168103 | Feb 21 01:20:21 PM PST 24 | Feb 21 01:20:23 PM PST 24 | 157576159 ps | ||
| T876 | /workspace/coverage/default/22.sram_ctrl_max_throughput.2487062880 | Feb 21 01:19:55 PM PST 24 | Feb 21 01:21:07 PM PST 24 | 118220218 ps | ||
| T35 | /workspace/coverage/default/1.sram_ctrl_sec_cm.1245319616 | Feb 21 01:18:55 PM PST 24 | Feb 21 01:18:57 PM PST 24 | 169963280 ps | ||
| T877 | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2874149761 | Feb 21 01:19:57 PM PST 24 | Feb 21 01:26:14 PM PST 24 | 56642774670 ps | ||
| T878 | /workspace/coverage/default/23.sram_ctrl_bijection.739257881 | Feb 21 01:19:57 PM PST 24 | Feb 21 01:20:48 PM PST 24 | 2199328497 ps | ||
| T879 | /workspace/coverage/default/45.sram_ctrl_alert_test.2236870557 | Feb 21 01:22:29 PM PST 24 | Feb 21 01:22:30 PM PST 24 | 42068456 ps | ||
| T880 | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.653804673 | Feb 21 01:18:56 PM PST 24 | Feb 21 01:21:35 PM PST 24 | 5277633893 ps | ||
| T881 | /workspace/coverage/default/44.sram_ctrl_executable.3683577822 | Feb 21 01:22:27 PM PST 24 | Feb 21 01:38:56 PM PST 24 | 12329721766 ps | ||
| T882 | /workspace/coverage/default/33.sram_ctrl_lc_escalation.2594646639 | Feb 21 01:20:55 PM PST 24 | Feb 21 01:20:58 PM PST 24 | 116406685 ps | ||
| T883 | /workspace/coverage/default/6.sram_ctrl_regwen.2815582547 | Feb 21 01:19:19 PM PST 24 | Feb 21 01:23:54 PM PST 24 | 821279445 ps | ||
| T884 | /workspace/coverage/default/20.sram_ctrl_bijection.3870560876 | Feb 21 01:19:52 PM PST 24 | Feb 21 01:20:17 PM PST 24 | 402130385 ps | ||
| T885 | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2364776914 | Feb 21 01:20:34 PM PST 24 | Feb 21 01:20:40 PM PST 24 | 325084187 ps | ||
| T886 | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1648915431 | Feb 21 01:21:27 PM PST 24 | Feb 21 01:21:29 PM PST 24 | 131299614 ps | ||
| T887 | /workspace/coverage/default/5.sram_ctrl_max_throughput.127332146 | Feb 21 01:18:44 PM PST 24 | Feb 21 01:19:23 PM PST 24 | 389480295 ps | ||
| T888 | /workspace/coverage/default/24.sram_ctrl_smoke.3165332933 | Feb 21 01:20:09 PM PST 24 | Feb 21 01:20:11 PM PST 24 | 135974632 ps | ||
| T889 | /workspace/coverage/default/18.sram_ctrl_multiple_keys.3596473852 | Feb 21 01:19:29 PM PST 24 | Feb 21 01:41:55 PM PST 24 | 5389897001 ps | ||
| T890 | /workspace/coverage/default/44.sram_ctrl_bijection.421210770 | Feb 21 01:21:46 PM PST 24 | Feb 21 01:22:19 PM PST 24 | 536895332 ps | ||
| T79 | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2645741871 | Feb 21 02:55:25 PM PST 24 | Feb 21 02:55:26 PM PST 24 | 95568368 ps | ||
| T87 | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3139359246 | Feb 21 02:55:29 PM PST 24 | Feb 21 02:55:33 PM PST 24 | 462884961 ps | ||
| T29 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4155816558 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:46 PM PST 24 | 1765467827 ps | ||
| T26 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1845751830 | Feb 21 02:55:30 PM PST 24 | Feb 21 02:55:32 PM PST 24 | 248277390 ps | ||
| T56 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.456782297 | Feb 21 02:55:44 PM PST 24 | Feb 21 02:55:46 PM PST 24 | 47648523 ps | ||
| T80 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.451962437 | Feb 21 02:55:57 PM PST 24 | Feb 21 02:56:00 PM PST 24 | 119466140 ps | ||
| T30 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2184039903 | Feb 21 02:56:10 PM PST 24 | Feb 21 02:56:14 PM PST 24 | 213977723 ps | ||
| T81 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.91757639 | Feb 21 02:55:48 PM PST 24 | Feb 21 02:55:50 PM PST 24 | 116808766 ps | ||
| T27 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2022229179 | Feb 21 02:56:00 PM PST 24 | Feb 21 02:56:04 PM PST 24 | 349100825 ps | ||
| T42 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1509866043 | Feb 21 02:56:11 PM PST 24 | Feb 21 02:56:16 PM PST 24 | 128979760 ps | ||
| T57 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.700975038 | Feb 21 02:56:06 PM PST 24 | Feb 21 02:56:16 PM PST 24 | 388925384 ps | ||
| T88 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2430882524 | Feb 21 02:55:27 PM PST 24 | Feb 21 02:55:28 PM PST 24 | 16632133 ps | ||
| T28 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1212034432 | Feb 21 02:55:43 PM PST 24 | Feb 21 02:55:47 PM PST 24 | 385382150 ps | ||
| T58 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.780220150 | Feb 21 02:55:43 PM PST 24 | Feb 21 02:55:45 PM PST 24 | 11778597 ps | ||
| T891 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.804524144 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:42 PM PST 24 | 15046723 ps | ||
| T43 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.948921486 | Feb 21 02:55:26 PM PST 24 | Feb 21 02:55:29 PM PST 24 | 29507723 ps | ||
| T50 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2352454038 | Feb 21 02:55:42 PM PST 24 | Feb 21 02:55:46 PM PST 24 | 347090899 ps | ||
| T59 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1858133679 | Feb 21 02:55:43 PM PST 24 | Feb 21 02:55:47 PM PST 24 | 710254117 ps | ||
| T89 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2244285146 | Feb 21 02:55:41 PM PST 24 | Feb 21 02:55:44 PM PST 24 | 29678345 ps | ||
| T60 | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.273933113 | Feb 21 02:56:03 PM PST 24 | Feb 21 02:56:11 PM PST 24 | 219214652 ps | ||
| T61 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.248423889 | Feb 21 02:56:01 PM PST 24 | Feb 21 02:56:03 PM PST 24 | 21561243 ps | ||
| T62 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.16984005 | Feb 21 02:56:05 PM PST 24 | Feb 21 02:56:11 PM PST 24 | 199559716 ps | ||
| T63 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2525753348 | Feb 21 02:56:09 PM PST 24 | Feb 21 02:56:13 PM PST 24 | 422738655 ps | ||
| T44 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2331829016 | Feb 21 02:55:56 PM PST 24 | Feb 21 02:55:59 PM PST 24 | 482576413 ps | ||
| T45 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1476295127 | Feb 21 02:55:59 PM PST 24 | Feb 21 02:56:03 PM PST 24 | 619741858 ps | ||
| T46 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1106500389 | Feb 21 02:56:01 PM PST 24 | Feb 21 02:56:04 PM PST 24 | 27035579 ps | ||
| T892 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.157947097 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:42 PM PST 24 | 13478002 ps | ||
| T55 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3695810982 | Feb 21 02:55:27 PM PST 24 | Feb 21 02:55:29 PM PST 24 | 1688269624 ps | ||
| T64 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4262303559 | Feb 21 02:56:00 PM PST 24 | Feb 21 02:56:05 PM PST 24 | 908813271 ps | ||
| T65 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.709864400 | Feb 21 02:55:54 PM PST 24 | Feb 21 02:55:55 PM PST 24 | 11369710 ps | ||
| T51 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1236359986 | Feb 21 02:55:43 PM PST 24 | Feb 21 02:55:46 PM PST 24 | 124261105 ps | ||
| T893 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.860109149 | Feb 21 02:56:02 PM PST 24 | Feb 21 02:56:04 PM PST 24 | 14135307 ps | ||
| T894 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1918784744 | Feb 21 02:55:38 PM PST 24 | Feb 21 02:55:40 PM PST 24 | 27268054 ps | ||
| T47 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1029246597 | Feb 21 02:55:58 PM PST 24 | Feb 21 02:56:02 PM PST 24 | 167355142 ps | ||
| T895 | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1532842690 | Feb 21 02:56:12 PM PST 24 | Feb 21 02:56:13 PM PST 24 | 135538205 ps | ||
| T896 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1317535024 | Feb 21 02:55:52 PM PST 24 | Feb 21 02:55:53 PM PST 24 | 16250690 ps | ||
| T897 | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1707939623 | Feb 21 02:56:04 PM PST 24 | Feb 21 02:56:05 PM PST 24 | 23234415 ps | ||
| T66 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3793153891 | Feb 21 02:55:23 PM PST 24 | Feb 21 02:55:29 PM PST 24 | 1650285191 ps | ||
| T67 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.664128260 | Feb 21 02:56:05 PM PST 24 | Feb 21 02:56:06 PM PST 24 | 30760298 ps | ||
| T48 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2544959866 | Feb 21 02:55:51 PM PST 24 | Feb 21 02:55:53 PM PST 24 | 106339996 ps | ||
| T49 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.908053139 | Feb 21 02:56:02 PM PST 24 | Feb 21 02:56:04 PM PST 24 | 112771298 ps | ||
| T898 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.99692534 | Feb 21 02:55:43 PM PST 24 | Feb 21 02:55:45 PM PST 24 | 15709897 ps | ||
| T899 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1993176629 | Feb 21 02:55:32 PM PST 24 | Feb 21 02:55:33 PM PST 24 | 15249311 ps | ||
| T96 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2016085556 | Feb 21 02:55:56 PM PST 24 | Feb 21 02:55:59 PM PST 24 | 188393901 ps | ||
| T93 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1528981525 | Feb 21 02:55:28 PM PST 24 | Feb 21 02:55:30 PM PST 24 | 149478494 ps | ||
| T52 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.328142246 | Feb 21 02:55:39 PM PST 24 | Feb 21 02:55:43 PM PST 24 | 333065587 ps | ||
| T68 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2667927197 | Feb 21 02:55:44 PM PST 24 | Feb 21 02:55:47 PM PST 24 | 18981791 ps | ||
| T90 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1256928833 | Feb 21 02:55:56 PM PST 24 | Feb 21 02:56:00 PM PST 24 | 165348327 ps | ||
| T900 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2435269108 | Feb 21 02:55:47 PM PST 24 | Feb 21 02:55:48 PM PST 24 | 10901340 ps | ||
| T53 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.440894307 | Feb 21 02:55:44 PM PST 24 | Feb 21 02:55:47 PM PST 24 | 463250114 ps | ||
| T54 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.980778867 | Feb 21 02:56:02 PM PST 24 | Feb 21 02:56:07 PM PST 24 | 378192272 ps | ||
| T901 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1310104424 | Feb 21 02:55:44 PM PST 24 | Feb 21 02:55:49 PM PST 24 | 273178760 ps | ||
| T902 | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2832285850 | Feb 21 02:55:41 PM PST 24 | Feb 21 02:55:46 PM PST 24 | 837678931 ps | ||
| T73 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1871522856 | Feb 21 02:56:12 PM PST 24 | Feb 21 02:56:13 PM PST 24 | 13946924 ps | ||
| T903 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.488482570 | Feb 21 02:55:39 PM PST 24 | Feb 21 02:55:40 PM PST 24 | 20797037 ps | ||
| T904 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1948576631 | Feb 21 02:55:36 PM PST 24 | Feb 21 02:55:40 PM PST 24 | 1152899567 ps | ||
| T905 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.932852687 | Feb 21 02:56:05 PM PST 24 | Feb 21 02:56:06 PM PST 24 | 29739604 ps | ||
| T906 | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1283025928 | Feb 21 02:56:02 PM PST 24 | Feb 21 02:56:04 PM PST 24 | 47010294 ps | ||
| T907 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1879121395 | Feb 21 02:55:58 PM PST 24 | Feb 21 02:56:01 PM PST 24 | 33278987 ps | ||
| T908 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.309322667 | Feb 21 02:56:08 PM PST 24 | Feb 21 02:56:09 PM PST 24 | 16205518 ps | ||
| T909 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3933008087 | Feb 21 02:56:03 PM PST 24 | Feb 21 02:56:06 PM PST 24 | 90742947 ps | ||
| T910 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3660272917 | Feb 21 02:55:27 PM PST 24 | Feb 21 02:55:28 PM PST 24 | 19740573 ps | ||
| T911 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.398900727 | Feb 21 02:55:44 PM PST 24 | Feb 21 02:55:49 PM PST 24 | 276383150 ps | ||
| T912 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4011177132 | Feb 21 02:55:56 PM PST 24 | Feb 21 02:55:57 PM PST 24 | 46779622 ps | ||
| T913 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4160894696 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:42 PM PST 24 | 78154561 ps | ||
| T914 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4259838876 | Feb 21 02:55:53 PM PST 24 | Feb 21 02:55:55 PM PST 24 | 332126060 ps | ||
| T74 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2083980764 | Feb 21 02:55:41 PM PST 24 | Feb 21 02:55:43 PM PST 24 | 23274228 ps | ||
| T915 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1909750786 | Feb 21 02:55:34 PM PST 24 | Feb 21 02:55:37 PM PST 24 | 20701925 ps | ||
| T916 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3223730410 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:44 PM PST 24 | 23757411 ps | ||
| T917 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3411322311 | Feb 21 02:55:28 PM PST 24 | Feb 21 02:55:29 PM PST 24 | 56392734 ps | ||
| T94 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4251419050 | Feb 21 02:56:05 PM PST 24 | Feb 21 02:56:08 PM PST 24 | 779493530 ps | ||
| T75 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4061129466 | Feb 21 02:55:46 PM PST 24 | Feb 21 02:55:57 PM PST 24 | 1562960151 ps | ||
| T918 | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3861671720 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:54 PM PST 24 | 1604256087 ps | ||
| T919 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2224884538 | Feb 21 02:55:57 PM PST 24 | Feb 21 02:55:59 PM PST 24 | 65483190 ps | ||
| T920 | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.347095598 | Feb 21 02:55:58 PM PST 24 | Feb 21 02:56:05 PM PST 24 | 1162427670 ps | ||
| T921 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.402715947 | Feb 21 02:56:09 PM PST 24 | Feb 21 02:56:10 PM PST 24 | 30913227 ps | ||
| T922 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.874331059 | Feb 21 02:55:27 PM PST 24 | Feb 21 02:55:28 PM PST 24 | 36418673 ps | ||
| T923 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1698735998 | Feb 21 02:56:04 PM PST 24 | Feb 21 02:56:09 PM PST 24 | 633808995 ps | ||
| T924 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1513594371 | Feb 21 02:55:27 PM PST 24 | Feb 21 02:55:27 PM PST 24 | 40192996 ps | ||
| T76 | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.874404662 | Feb 21 02:55:48 PM PST 24 | Feb 21 02:55:59 PM PST 24 | 3350086679 ps | ||
| T925 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4173351976 | Feb 21 02:56:02 PM PST 24 | Feb 21 02:56:07 PM PST 24 | 76024947 ps | ||
| T78 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3790015969 | Feb 21 02:55:51 PM PST 24 | Feb 21 02:56:01 PM PST 24 | 433316959 ps | ||
| T926 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3695726567 | Feb 21 02:56:10 PM PST 24 | Feb 21 02:56:11 PM PST 24 | 46230892 ps | ||
| T927 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.279466261 | Feb 21 02:56:12 PM PST 24 | Feb 21 02:56:13 PM PST 24 | 20944030 ps | ||
| T928 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.383103827 | Feb 21 02:55:54 PM PST 24 | Feb 21 02:55:55 PM PST 24 | 28356174 ps | ||
| T929 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2909576202 | Feb 21 02:55:41 PM PST 24 | Feb 21 02:55:47 PM PST 24 | 234772329 ps | ||
| T930 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2869464679 | Feb 21 02:56:03 PM PST 24 | Feb 21 02:56:07 PM PST 24 | 429885684 ps | ||
| T931 | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.148773410 | Feb 21 02:55:46 PM PST 24 | Feb 21 02:55:47 PM PST 24 | 22473108 ps | ||
| T932 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1411464028 | Feb 21 02:55:41 PM PST 24 | Feb 21 02:55:46 PM PST 24 | 167893568 ps | ||
| T933 | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1968037217 | Feb 21 02:55:41 PM PST 24 | Feb 21 02:55:44 PM PST 24 | 25227407 ps | ||
| T934 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3820744099 | Feb 21 02:55:59 PM PST 24 | Feb 21 02:56:04 PM PST 24 | 33766625 ps | ||
| T935 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.271126578 | Feb 21 02:56:01 PM PST 24 | Feb 21 02:56:06 PM PST 24 | 115216465 ps | ||
| T936 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1352594589 | Feb 21 02:56:05 PM PST 24 | Feb 21 02:56:06 PM PST 24 | 45028546 ps | ||
| T937 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.499276832 | Feb 21 02:55:48 PM PST 24 | Feb 21 02:55:51 PM PST 24 | 151653649 ps | ||
| T91 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2873151030 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:43 PM PST 24 | 299529812 ps | ||
| T938 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3450563391 | Feb 21 02:55:23 PM PST 24 | Feb 21 02:55:33 PM PST 24 | 693576387 ps | ||
| T939 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.508541892 | Feb 21 02:55:51 PM PST 24 | Feb 21 02:55:52 PM PST 24 | 123042604 ps | ||
| T92 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.407604114 | Feb 21 02:56:05 PM PST 24 | Feb 21 02:56:08 PM PST 24 | 831894072 ps | ||
| T940 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1709825873 | Feb 21 02:55:25 PM PST 24 | Feb 21 02:55:26 PM PST 24 | 55002476 ps | ||
| T941 | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3396852659 | Feb 21 02:55:54 PM PST 24 | Feb 21 02:55:57 PM PST 24 | 960816149 ps | ||
| T942 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2290745708 | Feb 21 02:56:05 PM PST 24 | Feb 21 02:56:10 PM PST 24 | 133616157 ps | ||
| T943 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4220714676 | Feb 21 02:56:10 PM PST 24 | Feb 21 02:56:21 PM PST 24 | 1523057793 ps | ||
| T944 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3155974108 | Feb 21 02:56:02 PM PST 24 | Feb 21 02:56:04 PM PST 24 | 18323088 ps | ||
| T95 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2120122150 | Feb 21 02:55:53 PM PST 24 | Feb 21 02:55:56 PM PST 24 | 713507388 ps | ||
| T945 | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4082393710 | Feb 21 02:55:54 PM PST 24 | Feb 21 02:55:55 PM PST 24 | 52525872 ps | ||
| T946 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2024961216 | Feb 21 02:55:40 PM PST 24 | Feb 21 02:55:42 PM PST 24 | 17583995 ps | ||
| T947 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2925959850 | Feb 21 02:55:25 PM PST 24 | Feb 21 02:55:30 PM PST 24 | 78077179 ps | ||
| T948 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1593503603 | Feb 21 02:55:34 PM PST 24 | Feb 21 02:55:36 PM PST 24 | 18744569 ps | ||
| T949 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.897637683 | Feb 21 02:55:57 PM PST 24 | Feb 21 02:56:03 PM PST 24 | 463570595 ps | ||
| T950 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2587043507 | Feb 21 02:55:26 PM PST 24 | Feb 21 02:55:27 PM PST 24 | 98850175 ps | ||
| T951 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2252995420 | Feb 21 02:55:55 PM PST 24 | Feb 21 02:55:59 PM PST 24 | 37354670 ps | ||
| T952 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2875025148 | Feb 21 02:55:42 PM PST 24 | Feb 21 02:55:45 PM PST 24 | 14872371 ps | ||
| T953 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3549370967 | Feb 21 02:55:43 PM PST 24 | Feb 21 02:55:47 PM PST 24 | 715912282 ps | ||
| T954 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1861058832 | Feb 21 02:55:57 PM PST 24 | Feb 21 02:56:00 PM PST 24 | 14474891 ps | ||
| T955 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4115732464 | Feb 21 02:55:41 PM PST 24 | Feb 21 02:55:46 PM PST 24 | 36560221 ps |
| Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1172931531 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 17491337587 ps |
| CPU time | 1835.19 seconds |
| Started | Feb 21 01:21:46 PM PST 24 |
| Finished | Feb 21 01:52:22 PM PST 24 |
| Peak memory | 373500 kb |
| Host | smart-852ec314-f7a5-43ed-a93b-3f187cf55376 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172931531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.1172931531 |
| Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.982719443 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 62204811448 ps |
| CPU time | 5522.9 seconds |
| Started | Feb 21 01:20:51 PM PST 24 |
| Finished | Feb 21 02:52:55 PM PST 24 |
| Peak memory | 375584 kb |
| Host | smart-17e55e7a-8351-42ce-b119-78ae03aab6a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982719443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_stress_all.982719443 |
| Directory | /workspace/33.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2022229179 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 349100825 ps |
| CPU time | 2.23 seconds |
| Started | Feb 21 02:56:00 PM PST 24 |
| Finished | Feb 21 02:56:04 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-8f4654bd-9a88-497a-9bfe-67218ff11ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022229179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.2022229179 |
| Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2416690424 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 138341926632 ps |
| CPU time | 1413.07 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 01:44:17 PM PST 24 |
| Peak memory | 370504 kb |
| Host | smart-0bb3871c-007f-4ef6-9ee1-b89ec46aba08 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416690424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2416690424 |
| Directory | /workspace/31.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4155816558 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1765467827 ps |
| CPU time | 4.43 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:46 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-e32ae2e7-f45c-432b-86b2-d4fe314c782d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155816558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.4155816558 |
| Directory | /workspace/4.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.1455449550 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 446683065 ps |
| CPU time | 1.94 seconds |
| Started | Feb 21 01:18:17 PM PST 24 |
| Finished | Feb 21 01:18:19 PM PST 24 |
| Peak memory | 221076 kb |
| Host | smart-8c778f41-91ee-414d-99ee-dced1eedd276 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455449550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1455449550 |
| Directory | /workspace/0.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.3566509122 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 153838363 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 01:22:34 PM PST 24 |
| Finished | Feb 21 01:22:35 PM PST 24 |
| Peak memory | 202920 kb |
| Host | smart-58864363-5957-45b2-8e5f-82a9af79d09b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566509122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3566509122 |
| Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.1262917437 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 81147227072 ps |
| CPU time | 1543.75 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:47:28 PM PST 24 |
| Peak memory | 381988 kb |
| Host | smart-809e26d6-89d3-4829-b75e-f115d7659ddf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262917437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1262917437 |
| Directory | /workspace/42.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.700975038 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 388925384 ps |
| CPU time | 10.34 seconds |
| Started | Feb 21 02:56:06 PM PST 24 |
| Finished | Feb 21 02:56:16 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-45e2aecf-08f9-4cd3-a36f-ed7b8a783aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700975038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.700975038 |
| Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.4159665710 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 108639404941 ps |
| CPU time | 628.94 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:30:51 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-5c6d0a5f-29e2-4172-9347-ea1da8a34811 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159665710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.4159665710 |
| Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.91853769 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 30052459 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 01:19:35 PM PST 24 |
| Finished | Feb 21 01:19:37 PM PST 24 |
| Peak memory | 201624 kb |
| Host | smart-0c2f7368-9e58-4000-abba-a9fee501d710 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91853769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_alert_test.91853769 |
| Directory | /workspace/17.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_executable.1965567151 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2398162966 ps |
| CPU time | 968.29 seconds |
| Started | Feb 21 01:22:31 PM PST 24 |
| Finished | Feb 21 01:38:40 PM PST 24 |
| Peak memory | 373428 kb |
| Host | smart-c252a547-ba54-4cf8-805f-cc5c312acc39 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965567151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.1965567151 |
| Directory | /workspace/49.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4251419050 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 779493530 ps |
| CPU time | 2.44 seconds |
| Started | Feb 21 02:56:05 PM PST 24 |
| Finished | Feb 21 02:56:08 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-12957d34-c957-44b5-8188-508abc1a604c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251419050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.4251419050 |
| Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1256928833 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 165348327 ps |
| CPU time | 2.3 seconds |
| Started | Feb 21 02:55:56 PM PST 24 |
| Finished | Feb 21 02:56:00 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-ab765672-5c0e-4acb-acd2-86385e3dedbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256928833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.1256928833 |
| Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1528981525 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 149478494 ps |
| CPU time | 1.58 seconds |
| Started | Feb 21 02:55:28 PM PST 24 |
| Finished | Feb 21 02:55:30 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-e9a58b90-10b8-45fa-9ee4-dbfb7e7d8a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528981525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1528981525 |
| Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3793153891 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1650285191 ps |
| CPU time | 5.45 seconds |
| Started | Feb 21 02:55:23 PM PST 24 |
| Finished | Feb 21 02:55:29 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-b9c18db1-cf5f-4698-ba35-863148d74a52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793153891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3793153891 |
| Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.561299576 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2617607460 ps |
| CPU time | 204.39 seconds |
| Started | Feb 21 01:19:33 PM PST 24 |
| Finished | Feb 21 01:22:57 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-1f62b0ed-dfca-42fe-8818-346d92221dbd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561299576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .sram_ctrl_stress_pipeline.561299576 |
| Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.3138570699 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 16773130712 ps |
| CPU time | 1705.71 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:48:08 PM PST 24 |
| Peak memory | 382296 kb |
| Host | smart-8e81466b-96bd-4493-aabc-e19d35c7584b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138570699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.3138570699 |
| Directory | /workspace/15.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1709825873 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 55002476 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 02:55:25 PM PST 24 |
| Finished | Feb 21 02:55:26 PM PST 24 |
| Peak memory | 202100 kb |
| Host | smart-6a27d3f2-8fe0-4a24-966b-82f6de940648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709825873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1709825873 |
| Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3411322311 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 56392734 ps |
| CPU time | 1.19 seconds |
| Started | Feb 21 02:55:28 PM PST 24 |
| Finished | Feb 21 02:55:29 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-959ad49e-24d2-4b02-a32e-1848bbab5586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411322311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.3411322311 |
| Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3660272917 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 19740573 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 02:55:27 PM PST 24 |
| Finished | Feb 21 02:55:28 PM PST 24 |
| Peak memory | 202076 kb |
| Host | smart-f117d745-2891-4052-8ac6-032d6d20eaf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660272917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.3660272917 |
| Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.874331059 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 36418673 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 02:55:27 PM PST 24 |
| Finished | Feb 21 02:55:28 PM PST 24 |
| Peak memory | 202096 kb |
| Host | smart-b884f671-8bcc-4b03-9a79-7dd889d8d5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874331059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.sram_ctrl_csr_rw.874331059 |
| Directory | /workspace/0.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2645741871 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 95568368 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 02:55:25 PM PST 24 |
| Finished | Feb 21 02:55:26 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-988becf7-28d0-4d84-8355-dbb65e93276f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645741871 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2645741871 |
| Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.948921486 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29507723 ps |
| CPU time | 2.69 seconds |
| Started | Feb 21 02:55:26 PM PST 24 |
| Finished | Feb 21 02:55:29 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-c9088cc7-e076-402b-9e63-4697ed67d7f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948921486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.948921486 |
| Directory | /workspace/0.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1845751830 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 248277390 ps |
| CPU time | 1.34 seconds |
| Started | Feb 21 02:55:30 PM PST 24 |
| Finished | Feb 21 02:55:32 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-1dcac17c-0f58-4ffa-b7d3-45fc8fdf8e3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845751830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.1845751830 |
| Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2587043507 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 98850175 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 02:55:26 PM PST 24 |
| Finished | Feb 21 02:55:27 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-c1626c91-e927-4c83-85df-1baa6587a880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587043507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2587043507 |
| Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1918784744 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 27268054 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 02:55:38 PM PST 24 |
| Finished | Feb 21 02:55:40 PM PST 24 |
| Peak memory | 202316 kb |
| Host | smart-65bd36c0-a694-4c96-b548-64afdde0c839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918784744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.1918784744 |
| Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1993176629 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 15249311 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 02:55:32 PM PST 24 |
| Finished | Feb 21 02:55:33 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-7f86ef84-cfd1-4d26-8e1f-8daf9aa7b78f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993176629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.1993176629 |
| Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2430882524 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 16632133 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 02:55:27 PM PST 24 |
| Finished | Feb 21 02:55:28 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-6a3c5d7f-54a7-4721-be7c-832098c74ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430882524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2430882524 |
| Directory | /workspace/1.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3450563391 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 693576387 ps |
| CPU time | 9.37 seconds |
| Started | Feb 21 02:55:23 PM PST 24 |
| Finished | Feb 21 02:55:33 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-fd4c9be5-a364-4082-83d4-10bc77241936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450563391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3450563391 |
| Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1593503603 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 18744569 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 02:55:34 PM PST 24 |
| Finished | Feb 21 02:55:36 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-774a5af6-27e1-45b9-9e04-b2159d7ba4aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593503603 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1593503603 |
| Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2925959850 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 78077179 ps |
| CPU time | 4.02 seconds |
| Started | Feb 21 02:55:25 PM PST 24 |
| Finished | Feb 21 02:55:30 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-69d060cb-0b15-4c87-b999-36ba7c4962d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925959850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2925959850 |
| Directory | /workspace/1.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.709864400 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 11369710 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 02:55:54 PM PST 24 |
| Finished | Feb 21 02:55:55 PM PST 24 |
| Peak memory | 202048 kb |
| Host | smart-c6b2fd3c-78b1-4442-9fdc-b9ac3dfe27ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709864400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_csr_rw.709864400 |
| Directory | /workspace/10.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.273933113 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 219214652 ps |
| CPU time | 6.28 seconds |
| Started | Feb 21 02:56:03 PM PST 24 |
| Finished | Feb 21 02:56:11 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-0aadfcb9-cb3a-460f-8f3e-f13009c26d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273933113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.273933113 |
| Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4082393710 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 52525872 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 02:55:54 PM PST 24 |
| Finished | Feb 21 02:55:55 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-9a65cc8c-4ce1-4c46-9e4f-45f0e48338f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082393710 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.4082393710 |
| Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2290745708 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 133616157 ps |
| CPU time | 4.43 seconds |
| Started | Feb 21 02:56:05 PM PST 24 |
| Finished | Feb 21 02:56:10 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-197949ca-6bc0-43bf-9d82-ebe842ec2902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290745708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.2290745708 |
| Directory | /workspace/10.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1476295127 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 619741858 ps |
| CPU time | 2.42 seconds |
| Started | Feb 21 02:55:59 PM PST 24 |
| Finished | Feb 21 02:56:03 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-f9d7f3c9-bbbc-484c-bd64-818046bd6039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476295127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1476295127 |
| Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.451962437 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 119466140 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 02:55:57 PM PST 24 |
| Finished | Feb 21 02:56:00 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-aabdf48d-c144-4d2d-8dbe-96f4bc44c9d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451962437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_csr_rw.451962437 |
| Directory | /workspace/11.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4262303559 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 908813271 ps |
| CPU time | 3.08 seconds |
| Started | Feb 21 02:56:00 PM PST 24 |
| Finished | Feb 21 02:56:05 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-b36c6ae1-9360-471a-bfc4-0182d9285da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262303559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.4262303559 |
| Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2224884538 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 65483190 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 02:55:57 PM PST 24 |
| Finished | Feb 21 02:55:59 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-28635f1b-3b58-480b-8143-1afbc67d2b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224884538 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2224884538 |
| Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3820744099 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 33766625 ps |
| CPU time | 3.5 seconds |
| Started | Feb 21 02:55:59 PM PST 24 |
| Finished | Feb 21 02:56:04 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-74053842-f193-4080-b70b-8f8e7365ca9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820744099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.3820744099 |
| Directory | /workspace/11.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1029246597 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 167355142 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 02:55:58 PM PST 24 |
| Finished | Feb 21 02:56:02 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-69bfebee-7673-47a7-825e-fca5cec0af08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029246597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1029246597 |
| Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.248423889 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 21561243 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 02:56:01 PM PST 24 |
| Finished | Feb 21 02:56:03 PM PST 24 |
| Peak memory | 202144 kb |
| Host | smart-1ccf3479-41ff-4f88-99dd-af21a018d637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248423889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_rw.248423889 |
| Directory | /workspace/12.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3396852659 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 960816149 ps |
| CPU time | 3.55 seconds |
| Started | Feb 21 02:55:54 PM PST 24 |
| Finished | Feb 21 02:55:57 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-e53e8b39-0ceb-46b4-a485-ddb367528555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396852659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.3396852659 |
| Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.402715947 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 30913227 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 02:56:09 PM PST 24 |
| Finished | Feb 21 02:56:10 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-8abb23b8-d01a-460f-a7a5-cf9e5b625493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402715947 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.402715947 |
| Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2544959866 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 106339996 ps |
| CPU time | 2.11 seconds |
| Started | Feb 21 02:55:51 PM PST 24 |
| Finished | Feb 21 02:55:53 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-2854d83b-0dd9-496a-a928-342ca46ccd70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544959866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.2544959866 |
| Directory | /workspace/12.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1317535024 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 16250690 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 02:55:52 PM PST 24 |
| Finished | Feb 21 02:55:53 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-a29d16e7-13d1-4a00-8bb0-e93f467c5692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317535024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.1317535024 |
| Directory | /workspace/13.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.347095598 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 1162427670 ps |
| CPU time | 5.73 seconds |
| Started | Feb 21 02:55:58 PM PST 24 |
| Finished | Feb 21 02:56:05 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-06de450a-de2f-4097-abed-76c8a31da64a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347095598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.347095598 |
| Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.383103827 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 28356174 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 02:55:54 PM PST 24 |
| Finished | Feb 21 02:55:55 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-8c3e51b1-30d5-4f10-9709-b94c501b0644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383103827 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.383103827 |
| Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2252995420 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 37354670 ps |
| CPU time | 3.27 seconds |
| Started | Feb 21 02:55:55 PM PST 24 |
| Finished | Feb 21 02:55:59 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-555f2a41-9e5e-41c4-bcde-4be4daf2fa2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252995420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.2252995420 |
| Directory | /workspace/13.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2016085556 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 188393901 ps |
| CPU time | 1.39 seconds |
| Started | Feb 21 02:55:56 PM PST 24 |
| Finished | Feb 21 02:55:59 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-b6903fbc-5a74-41ba-8cbf-2c110eb02d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016085556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.2016085556 |
| Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1871522856 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 13946924 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 02:56:12 PM PST 24 |
| Finished | Feb 21 02:56:13 PM PST 24 |
| Peak memory | 202052 kb |
| Host | smart-c4abb849-8ca4-4074-9048-35a29d3dd2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871522856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.1871522856 |
| Directory | /workspace/14.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2869464679 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 429885684 ps |
| CPU time | 2.83 seconds |
| Started | Feb 21 02:56:03 PM PST 24 |
| Finished | Feb 21 02:56:07 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-a97bb8a7-6dc3-4671-ad0a-78eb17d72359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869464679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2869464679 |
| Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1532842690 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 135538205 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 02:56:12 PM PST 24 |
| Finished | Feb 21 02:56:13 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-ca4616b1-84cc-4c6e-9fb6-b18bbb3769dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532842690 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1532842690 |
| Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1106500389 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 27035579 ps |
| CPU time | 2.19 seconds |
| Started | Feb 21 02:56:01 PM PST 24 |
| Finished | Feb 21 02:56:04 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-a33c89c7-9601-475a-b062-52654ab57d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106500389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.1106500389 |
| Directory | /workspace/14.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3933008087 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 90742947 ps |
| CPU time | 1.43 seconds |
| Started | Feb 21 02:56:03 PM PST 24 |
| Finished | Feb 21 02:56:06 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-8fdabe2d-3a40-46c1-ae10-b097a4a8aad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933008087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.3933008087 |
| Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3695726567 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 46230892 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 02:56:10 PM PST 24 |
| Finished | Feb 21 02:56:11 PM PST 24 |
| Peak memory | 202152 kb |
| Host | smart-5c9f2aab-601d-405c-8fc2-d00831ebb71d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695726567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3695726567 |
| Directory | /workspace/15.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1352594589 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 45028546 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 02:56:05 PM PST 24 |
| Finished | Feb 21 02:56:06 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-5c889d5c-6d9b-4505-8b64-687a1984bc6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352594589 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1352594589 |
| Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2184039903 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 213977723 ps |
| CPU time | 3.75 seconds |
| Started | Feb 21 02:56:10 PM PST 24 |
| Finished | Feb 21 02:56:14 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-e5199178-6df4-4116-90c3-c0ce1000326d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184039903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.2184039903 |
| Directory | /workspace/15.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.407604114 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 831894072 ps |
| CPU time | 2.39 seconds |
| Started | Feb 21 02:56:05 PM PST 24 |
| Finished | Feb 21 02:56:08 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-fe4df2b8-fdd5-45eb-95bc-db680e2e58f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407604114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sram_ctrl_tl_intg_err.407604114 |
| Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.664128260 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 30760298 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 02:56:05 PM PST 24 |
| Finished | Feb 21 02:56:06 PM PST 24 |
| Peak memory | 202144 kb |
| Host | smart-87ef6eb1-e5a3-4db0-b0de-23831e2b5bc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664128260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_csr_rw.664128260 |
| Directory | /workspace/16.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4220714676 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1523057793 ps |
| CPU time | 10.84 seconds |
| Started | Feb 21 02:56:10 PM PST 24 |
| Finished | Feb 21 02:56:21 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-7cc42525-db61-424c-9999-1aa480654518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220714676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.4220714676 |
| Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.309322667 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 16205518 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 02:56:08 PM PST 24 |
| Finished | Feb 21 02:56:09 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-60e191ca-762f-4121-a847-7bcd48d2a682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309322667 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.309322667 |
| Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.271126578 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 115216465 ps |
| CPU time | 4.19 seconds |
| Started | Feb 21 02:56:01 PM PST 24 |
| Finished | Feb 21 02:56:06 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-981144a1-0b3a-4787-bf07-45673935786f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271126578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.271126578 |
| Directory | /workspace/16.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.908053139 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 112771298 ps |
| CPU time | 1.62 seconds |
| Started | Feb 21 02:56:02 PM PST 24 |
| Finished | Feb 21 02:56:04 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-12f4dc16-401f-4ca5-9f76-76aa062ec3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908053139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.sram_ctrl_tl_intg_err.908053139 |
| Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.279466261 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 20944030 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 02:56:12 PM PST 24 |
| Finished | Feb 21 02:56:13 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-c2681330-c85b-4af1-af51-08bf42f1835e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279466261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.279466261 |
| Directory | /workspace/17.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.897637683 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 463570595 ps |
| CPU time | 4.61 seconds |
| Started | Feb 21 02:55:57 PM PST 24 |
| Finished | Feb 21 02:56:03 PM PST 24 |
| Peak memory | 202536 kb |
| Host | smart-559da5e5-7d09-471c-b865-54df37853fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897637683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.897637683 |
| Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1861058832 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 14474891 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 02:55:57 PM PST 24 |
| Finished | Feb 21 02:56:00 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-c93f7133-3c2e-4ed4-9839-41e6f62d01ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861058832 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1861058832 |
| Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.980778867 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 378192272 ps |
| CPU time | 3.48 seconds |
| Started | Feb 21 02:56:02 PM PST 24 |
| Finished | Feb 21 02:56:07 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-f7def682-2e0c-4fc6-9ab7-1391f49edd55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980778867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.980778867 |
| Directory | /workspace/17.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3155974108 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 18323088 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 02:56:02 PM PST 24 |
| Finished | Feb 21 02:56:04 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-916cd4ef-7315-4544-a8a8-b1e356bec867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155974108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.3155974108 |
| Directory | /workspace/18.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2525753348 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 422738655 ps |
| CPU time | 4.3 seconds |
| Started | Feb 21 02:56:09 PM PST 24 |
| Finished | Feb 21 02:56:13 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-3b669e9e-3ac9-4323-a5ba-24c088499171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525753348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2525753348 |
| Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1707939623 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 23234415 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 02:56:04 PM PST 24 |
| Finished | Feb 21 02:56:05 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-68ae58bb-11ce-47a4-bb92-e81b1db6542c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707939623 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1707939623 |
| Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1698735998 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 633808995 ps |
| CPU time | 4.68 seconds |
| Started | Feb 21 02:56:04 PM PST 24 |
| Finished | Feb 21 02:56:09 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-fcb284ff-faae-4a65-88f8-d44b9a505318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698735998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.1698735998 |
| Directory | /workspace/18.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2120122150 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 713507388 ps |
| CPU time | 2.51 seconds |
| Started | Feb 21 02:55:53 PM PST 24 |
| Finished | Feb 21 02:55:56 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-494a4ed3-1446-4a88-863a-2877bb9d1eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120122150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.2120122150 |
| Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.860109149 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 14135307 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 02:56:02 PM PST 24 |
| Finished | Feb 21 02:56:04 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-5dcf2d58-c8f4-468f-b218-e9fe08251ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860109149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.860109149 |
| Directory | /workspace/19.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.16984005 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 199559716 ps |
| CPU time | 5.56 seconds |
| Started | Feb 21 02:56:05 PM PST 24 |
| Finished | Feb 21 02:56:11 PM PST 24 |
| Peak memory | 210772 kb |
| Host | smart-b2020c0c-2bcc-4a70-a3b6-15ff03a238fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.16984005 |
| Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.932852687 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 29739604 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 02:56:05 PM PST 24 |
| Finished | Feb 21 02:56:06 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-b426b442-57d2-4894-b677-6a667cb51eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932852687 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.932852687 |
| Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4173351976 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 76024947 ps |
| CPU time | 3.6 seconds |
| Started | Feb 21 02:56:02 PM PST 24 |
| Finished | Feb 21 02:56:07 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-d4103645-965d-489a-a8f9-f4717e078aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173351976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.4173351976 |
| Directory | /workspace/19.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2331829016 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 482576413 ps |
| CPU time | 2.06 seconds |
| Started | Feb 21 02:55:56 PM PST 24 |
| Finished | Feb 21 02:55:59 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-d3eb071b-7839-4be7-be9b-081e2be1af3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331829016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.2331829016 |
| Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2667927197 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 18981791 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 02:55:44 PM PST 24 |
| Finished | Feb 21 02:55:47 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-3af1030d-a9f1-43d6-9f04-fe556d2f463f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667927197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.2667927197 |
| Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.499276832 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 151653649 ps |
| CPU time | 1.97 seconds |
| Started | Feb 21 02:55:48 PM PST 24 |
| Finished | Feb 21 02:55:51 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-cb07b2ea-efd9-42c6-8570-c9e959787442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499276832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.499276832 |
| Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1513594371 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 40192996 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 02:55:27 PM PST 24 |
| Finished | Feb 21 02:55:27 PM PST 24 |
| Peak memory | 201140 kb |
| Host | smart-e0bc2428-8d95-41c4-85d5-a779784ea7dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513594371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.1513594371 |
| Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2083980764 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 23274228 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 02:55:41 PM PST 24 |
| Finished | Feb 21 02:55:43 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-2b22e8a7-b3c5-4bdf-8a91-4242a552a2e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083980764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.2083980764 |
| Directory | /workspace/2.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3139359246 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 462884961 ps |
| CPU time | 3.19 seconds |
| Started | Feb 21 02:55:29 PM PST 24 |
| Finished | Feb 21 02:55:33 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-80863d84-fdfc-4a0b-b4df-69512ca1712e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139359246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3139359246 |
| Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.148773410 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 22473108 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 02:55:46 PM PST 24 |
| Finished | Feb 21 02:55:47 PM PST 24 |
| Peak memory | 202152 kb |
| Host | smart-02fec8a3-afd0-4c70-be91-4b3393a0936a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148773410 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.148773410 |
| Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1909750786 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 20701925 ps |
| CPU time | 1.83 seconds |
| Started | Feb 21 02:55:34 PM PST 24 |
| Finished | Feb 21 02:55:37 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-f700aaf2-1d14-495c-8123-456ab8ef2210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909750786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.1909750786 |
| Directory | /workspace/2.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3695810982 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1688269624 ps |
| CPU time | 1.74 seconds |
| Started | Feb 21 02:55:27 PM PST 24 |
| Finished | Feb 21 02:55:29 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-6feabde3-1a83-4f49-b7bf-2b7c1c056357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695810982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.3695810982 |
| Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.488482570 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 20797037 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 02:55:39 PM PST 24 |
| Finished | Feb 21 02:55:40 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-f81f7af4-0956-4efc-b76a-f3d7c74995a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488482570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.488482570 |
| Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1858133679 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 710254117 ps |
| CPU time | 2.37 seconds |
| Started | Feb 21 02:55:43 PM PST 24 |
| Finished | Feb 21 02:55:47 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-fab5b3a8-7294-43cc-9cf5-34d12dc91662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858133679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.1858133679 |
| Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2244285146 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 29678345 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 02:55:41 PM PST 24 |
| Finished | Feb 21 02:55:44 PM PST 24 |
| Peak memory | 202016 kb |
| Host | smart-dc4a6f94-4bcb-4454-8fb4-2bb8191ade32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244285146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.2244285146 |
| Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2435269108 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 10901340 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 02:55:47 PM PST 24 |
| Finished | Feb 21 02:55:48 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-b32ef2c5-f91c-4122-b4fc-8bdc37a4f7da |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435269108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2435269108 |
| Directory | /workspace/3.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1948576631 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1152899567 ps |
| CPU time | 3.26 seconds |
| Started | Feb 21 02:55:36 PM PST 24 |
| Finished | Feb 21 02:55:40 PM PST 24 |
| Peak memory | 202532 kb |
| Host | smart-4543a430-927e-407a-b6f2-ac51dd0d8194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948576631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1948576631 |
| Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.91757639 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 116808766 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 02:55:48 PM PST 24 |
| Finished | Feb 21 02:55:50 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-1819b90f-48f8-4378-bbbc-d86f4b725347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91757639 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.91757639 |
| Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4115732464 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 36560221 ps |
| CPU time | 3.54 seconds |
| Started | Feb 21 02:55:41 PM PST 24 |
| Finished | Feb 21 02:55:46 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-866e82fc-c2da-418f-a77e-ae4b5a941f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115732464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.4115732464 |
| Directory | /workspace/3.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2873151030 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 299529812 ps |
| CPU time | 1.97 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:43 PM PST 24 |
| Peak memory | 202296 kb |
| Host | smart-e4518d9e-9644-48fb-8cb7-fad35f743292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873151030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.2873151030 |
| Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2024961216 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 17583995 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:42 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-7e7d3a8c-fd44-4eeb-96ca-e3432eae0cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024961216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2024961216 |
| Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4259838876 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 332126060 ps |
| CPU time | 1.39 seconds |
| Started | Feb 21 02:55:53 PM PST 24 |
| Finished | Feb 21 02:55:55 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-0f962cc8-b71a-4132-9bf5-4a06ff495c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259838876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.4259838876 |
| Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.99692534 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 15709897 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 02:55:43 PM PST 24 |
| Finished | Feb 21 02:55:45 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-9f50a091-866a-4c89-95b5-7ad9da73ce92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99692534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.99692534 |
| Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1879121395 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 33278987 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 02:55:58 PM PST 24 |
| Finished | Feb 21 02:56:01 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-f10e082f-57b4-4472-ba16-99cf3df84fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879121395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.1879121395 |
| Directory | /workspace/4.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4061129466 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1562960151 ps |
| CPU time | 10.88 seconds |
| Started | Feb 21 02:55:46 PM PST 24 |
| Finished | Feb 21 02:55:57 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-d5f8aec5-dfb5-453d-8c74-bcb423d9a7f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061129466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.4061129466 |
| Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3223730410 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 23757411 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:44 PM PST 24 |
| Peak memory | 202080 kb |
| Host | smart-bfe8039c-1fe7-44bd-a514-19251f5a6440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223730410 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3223730410 |
| Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3549370967 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 715912282 ps |
| CPU time | 2.38 seconds |
| Started | Feb 21 02:55:43 PM PST 24 |
| Finished | Feb 21 02:55:47 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-de9573d6-d63a-4e33-a390-42d88172d894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549370967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3549370967 |
| Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.157947097 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 13478002 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:42 PM PST 24 |
| Peak memory | 202032 kb |
| Host | smart-12f5663e-58cc-4935-a031-58f067109f50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157947097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_csr_rw.157947097 |
| Directory | /workspace/5.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2832285850 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 837678931 ps |
| CPU time | 3.27 seconds |
| Started | Feb 21 02:55:41 PM PST 24 |
| Finished | Feb 21 02:55:46 PM PST 24 |
| Peak memory | 202488 kb |
| Host | smart-f1019aec-44ba-46da-8064-53fd2a1ebd9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832285850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2832285850 |
| Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.456782297 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 47648523 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 02:55:44 PM PST 24 |
| Finished | Feb 21 02:55:46 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-443a1b87-ae2b-4be3-9ead-b38930c7209e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456782297 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.456782297 |
| Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1411464028 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 167893568 ps |
| CPU time | 2.56 seconds |
| Started | Feb 21 02:55:41 PM PST 24 |
| Finished | Feb 21 02:55:46 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-fd85e9ae-ee39-4f2f-bdae-fd4bf667e225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411464028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.1411464028 |
| Directory | /workspace/5.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1212034432 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 385382150 ps |
| CPU time | 2.57 seconds |
| Started | Feb 21 02:55:43 PM PST 24 |
| Finished | Feb 21 02:55:47 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-0a21e22c-ef14-47d5-a61f-76ad0babf168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212034432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.1212034432 |
| Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.804524144 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 15046723 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:42 PM PST 24 |
| Peak memory | 202092 kb |
| Host | smart-e79eb049-0a22-4076-8ff7-9c7bc883411a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804524144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_csr_rw.804524144 |
| Directory | /workspace/6.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2909576202 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 234772329 ps |
| CPU time | 3.07 seconds |
| Started | Feb 21 02:55:41 PM PST 24 |
| Finished | Feb 21 02:55:47 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-b75fbdf4-6ee2-488b-9b4e-8f15188d3835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909576202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2909576202 |
| Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4160894696 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 78154561 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:42 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-24021d17-3a65-4587-a796-8b28df2943bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160894696 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.4160894696 |
| Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.398900727 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 276383150 ps |
| CPU time | 2.98 seconds |
| Started | Feb 21 02:55:44 PM PST 24 |
| Finished | Feb 21 02:55:49 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-b54c3005-3029-4512-b65d-a1ba461d60ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398900727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.398900727 |
| Directory | /workspace/6.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2352454038 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 347090899 ps |
| CPU time | 1.46 seconds |
| Started | Feb 21 02:55:42 PM PST 24 |
| Finished | Feb 21 02:55:46 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-a31d27e8-88c3-4051-96b6-b1a543ba4ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352454038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.2352454038 |
| Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.780220150 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 11778597 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 02:55:43 PM PST 24 |
| Finished | Feb 21 02:55:45 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-83cb4e17-be79-49fa-831f-2a512b99337d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780220150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.780220150 |
| Directory | /workspace/7.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.874404662 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3350086679 ps |
| CPU time | 10.43 seconds |
| Started | Feb 21 02:55:48 PM PST 24 |
| Finished | Feb 21 02:55:59 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-054585c0-4bd0-442e-8b77-0aeff99a7000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874404662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.874404662 |
| Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1968037217 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 25227407 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 02:55:41 PM PST 24 |
| Finished | Feb 21 02:55:44 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-6003891c-c950-494c-a81f-8cf75fd6aaab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968037217 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1968037217 |
| Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1310104424 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 273178760 ps |
| CPU time | 2.87 seconds |
| Started | Feb 21 02:55:44 PM PST 24 |
| Finished | Feb 21 02:55:49 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-630e9134-5e94-4528-b97e-49598fb4f324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310104424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.1310104424 |
| Directory | /workspace/7.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1236359986 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 124261105 ps |
| CPU time | 1.64 seconds |
| Started | Feb 21 02:55:43 PM PST 24 |
| Finished | Feb 21 02:55:46 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-ca7a95c7-cf1f-4b12-b0d1-1bf55a308902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236359986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.1236359986 |
| Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2875025148 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 14872371 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 02:55:42 PM PST 24 |
| Finished | Feb 21 02:55:45 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-270c1ceb-2252-42aa-af59-71a6c7ac971e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875025148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.2875025148 |
| Directory | /workspace/8.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3861671720 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 1604256087 ps |
| CPU time | 11.07 seconds |
| Started | Feb 21 02:55:40 PM PST 24 |
| Finished | Feb 21 02:55:54 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-b1ffd6c9-7bee-417c-9c21-bbfb53a6be80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861671720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3861671720 |
| Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.508541892 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 123042604 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 02:55:51 PM PST 24 |
| Finished | Feb 21 02:55:52 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-1ea3b80d-16f8-409a-9515-febe1ed3b506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508541892 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.508541892 |
| Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.328142246 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 333065587 ps |
| CPU time | 3 seconds |
| Started | Feb 21 02:55:39 PM PST 24 |
| Finished | Feb 21 02:55:43 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-fbcd8a56-e7ce-49ed-8aa9-c254b38ae5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328142246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.328142246 |
| Directory | /workspace/8.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.440894307 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 463250114 ps |
| CPU time | 2.22 seconds |
| Started | Feb 21 02:55:44 PM PST 24 |
| Finished | Feb 21 02:55:47 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-42d9e5b1-2e4e-4988-ba51-78eaff09b6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440894307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.sram_ctrl_tl_intg_err.440894307 |
| Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4011177132 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 46779622 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 02:55:56 PM PST 24 |
| Finished | Feb 21 02:55:57 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-985cbb0a-feb4-4e06-9082-832fab26f8dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011177132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.4011177132 |
| Directory | /workspace/9.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3790015969 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 433316959 ps |
| CPU time | 9.91 seconds |
| Started | Feb 21 02:55:51 PM PST 24 |
| Finished | Feb 21 02:56:01 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-6a13571c-592b-4d1d-b035-b23d3e0abf6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790015969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3790015969 |
| Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1283025928 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 47010294 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 02:56:02 PM PST 24 |
| Finished | Feb 21 02:56:04 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-2a0060d8-dbef-4822-b1ed-8c5539df34c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283025928 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1283025928 |
| Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1509866043 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 128979760 ps |
| CPU time | 4.75 seconds |
| Started | Feb 21 02:56:11 PM PST 24 |
| Finished | Feb 21 02:56:16 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-0960210c-0a70-4289-bbb5-341b26cc9682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509866043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.1509866043 |
| Directory | /workspace/9.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.4148606551 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3686345547 ps |
| CPU time | 1450.25 seconds |
| Started | Feb 21 01:18:18 PM PST 24 |
| Finished | Feb 21 01:42:28 PM PST 24 |
| Peak memory | 374500 kb |
| Host | smart-a56d2f50-e8a7-40aa-b0be-25c61709ab2d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148606551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.4148606551 |
| Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.3396168233 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 60236769 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:18:20 PM PST 24 |
| Finished | Feb 21 01:18:22 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-ce3776e7-c45d-47d2-8dbc-798d7aeb2b74 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396168233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3396168233 |
| Directory | /workspace/0.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_bijection.1825453827 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2267640097 ps |
| CPU time | 35.82 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:18:48 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-a24d1a8b-d179-4956-a6d9-49c26ab7c441 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825453827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 1825453827 |
| Directory | /workspace/0.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_executable.3969838324 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3114551901 ps |
| CPU time | 601.77 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:28:18 PM PST 24 |
| Peak memory | 364348 kb |
| Host | smart-e010484d-d81c-4442-9041-a6ceb36708b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969838324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3969838324 |
| Directory | /workspace/0.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.2534664063 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 466936053 ps |
| CPU time | 6.98 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:18:21 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-de051cec-0d30-463d-ad54-a3533efa3886 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534664063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.2534664063 |
| Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.4017328466 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 43040146 ps |
| CPU time | 2.39 seconds |
| Started | Feb 21 01:18:14 PM PST 24 |
| Finished | Feb 21 01:18:19 PM PST 24 |
| Peak memory | 210864 kb |
| Host | smart-1f227703-dfa5-4819-ac8e-6e551b558f69 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017328466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.4017328466 |
| Directory | /workspace/0.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4148447985 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 82775073 ps |
| CPU time | 2.93 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:18:19 PM PST 24 |
| Peak memory | 210908 kb |
| Host | smart-50c74125-fd05-4e35-b926-9649ec0869bd |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148447985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.4148447985 |
| Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.1499393465 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 575402538 ps |
| CPU time | 10.36 seconds |
| Started | Feb 21 01:18:17 PM PST 24 |
| Finished | Feb 21 01:18:28 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-8b0c67d1-ee45-46da-84cb-3da37a452c64 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499393465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.1499393465 |
| Directory | /workspace/0.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.2630469267 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 24214746680 ps |
| CPU time | 455.1 seconds |
| Started | Feb 21 01:18:11 PM PST 24 |
| Finished | Feb 21 01:25:48 PM PST 24 |
| Peak memory | 374568 kb |
| Host | smart-fb00b431-dcf7-4482-817e-bd1200c36cf1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630469267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.2630469267 |
| Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.117157797 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 548865000 ps |
| CPU time | 8.11 seconds |
| Started | Feb 21 01:18:16 PM PST 24 |
| Finished | Feb 21 01:18:25 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-37dc5a32-1eb1-4d83-8d96-79fa33be3d06 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117157797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr am_ctrl_partial_access.117157797 |
| Directory | /workspace/0.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3093736779 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 50124056876 ps |
| CPU time | 345.53 seconds |
| Started | Feb 21 01:18:20 PM PST 24 |
| Finished | Feb 21 01:24:07 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-a70f70a2-5001-41d5-ba1b-e9847d740f35 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093736779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.3093736779 |
| Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.928270146 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 211134169 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:18:17 PM PST 24 |
| Finished | Feb 21 01:18:18 PM PST 24 |
| Peak memory | 202912 kb |
| Host | smart-cc4f7866-0b81-4b51-bc86-f0ca373ec9e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928270146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.928270146 |
| Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_regwen.1023796275 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 16342209495 ps |
| CPU time | 1103.42 seconds |
| Started | Feb 21 01:18:10 PM PST 24 |
| Finished | Feb 21 01:36:35 PM PST 24 |
| Peak memory | 363312 kb |
| Host | smart-af37ca6c-dd2b-4e8b-9a96-c21b364d3bfe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023796275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1023796275 |
| Directory | /workspace/0.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_smoke.4249852565 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3332666141 ps |
| CPU time | 9.4 seconds |
| Started | Feb 21 01:18:09 PM PST 24 |
| Finished | Feb 21 01:18:20 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-38fe132e-8c61-4b52-8327-e6287cc1f381 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249852565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.4249852565 |
| Directory | /workspace/0.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.3235006494 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 76134962761 ps |
| CPU time | 4288.64 seconds |
| Started | Feb 21 01:18:19 PM PST 24 |
| Finished | Feb 21 02:29:48 PM PST 24 |
| Peak memory | 374484 kb |
| Host | smart-dadc3edc-2f4c-49b2-b2c9-6597bdc423ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235006494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.3235006494 |
| Directory | /workspace/0.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2764042530 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 8416929979 ps |
| CPU time | 414.81 seconds |
| Started | Feb 21 01:18:15 PM PST 24 |
| Finished | Feb 21 01:25:11 PM PST 24 |
| Peak memory | 202972 kb |
| Host | smart-c1200e77-2274-4f89-b389-353bd9459f8a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764042530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.2764042530 |
| Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.788831809 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 205207946 ps |
| CPU time | 5.4 seconds |
| Started | Feb 21 01:18:20 PM PST 24 |
| Finished | Feb 21 01:18:27 PM PST 24 |
| Peak memory | 224036 kb |
| Host | smart-5a1359d5-1cf0-41aa-a904-db02c13b08d7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788831809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.788831809 |
| Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1669389578 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4076927439 ps |
| CPU time | 631.81 seconds |
| Started | Feb 21 01:18:56 PM PST 24 |
| Finished | Feb 21 01:29:28 PM PST 24 |
| Peak memory | 371384 kb |
| Host | smart-9730a7b3-bbac-4f30-be44-35daea770652 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669389578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.1669389578 |
| Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.26307963 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 19752368 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:18:59 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-b9349ad4-d144-4e29-99c2-689acba32a8e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_alert_test.26307963 |
| Directory | /workspace/1.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_bijection.789667248 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1716073498 ps |
| CPU time | 33.71 seconds |
| Started | Feb 21 01:18:31 PM PST 24 |
| Finished | Feb 21 01:19:05 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-9567c09e-5a8d-48ee-b90d-6b4c5a9d00c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789667248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.789667248 |
| Directory | /workspace/1.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_executable.3402924642 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 13367074822 ps |
| CPU time | 189.39 seconds |
| Started | Feb 21 01:18:37 PM PST 24 |
| Finished | Feb 21 01:21:46 PM PST 24 |
| Peak memory | 329800 kb |
| Host | smart-d6e992f8-81a8-4f75-bd03-961fcab1fda3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402924642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.3402924642 |
| Directory | /workspace/1.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.1531984359 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 795906512 ps |
| CPU time | 9.31 seconds |
| Started | Feb 21 01:18:29 PM PST 24 |
| Finished | Feb 21 01:18:38 PM PST 24 |
| Peak memory | 210820 kb |
| Host | smart-866967bc-2902-4953-b7e6-56b8036f1346 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531984359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1531984359 |
| Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1564481065 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 134516716 ps |
| CPU time | 98.17 seconds |
| Started | Feb 21 01:19:04 PM PST 24 |
| Finished | Feb 21 01:20:42 PM PST 24 |
| Peak memory | 354940 kb |
| Host | smart-56e7b9c2-9fbf-4942-8733-dee63578f109 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564481065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1564481065 |
| Directory | /workspace/1.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.552858837 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 156613843 ps |
| CPU time | 5.23 seconds |
| Started | Feb 21 01:18:57 PM PST 24 |
| Finished | Feb 21 01:19:02 PM PST 24 |
| Peak memory | 211772 kb |
| Host | smart-30ed73ac-b77e-4772-81fb-90b3f5a30614 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552858837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_mem_partial_access.552858837 |
| Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.818589107 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 79482996 ps |
| CPU time | 4.14 seconds |
| Started | Feb 21 01:18:53 PM PST 24 |
| Finished | Feb 21 01:18:57 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-5838c56a-c332-4bb8-8a53-e52fe78f292e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818589107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.818589107 |
| Directory | /workspace/1.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.3961816558 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5642217999 ps |
| CPU time | 2083.48 seconds |
| Started | Feb 21 01:18:17 PM PST 24 |
| Finished | Feb 21 01:53:01 PM PST 24 |
| Peak memory | 375572 kb |
| Host | smart-f4d4ee3a-d18a-49b9-a868-d3b232a5b542 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961816558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.3961816558 |
| Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.1396091716 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1218040241 ps |
| CPU time | 16.6 seconds |
| Started | Feb 21 01:18:42 PM PST 24 |
| Finished | Feb 21 01:18:59 PM PST 24 |
| Peak memory | 254516 kb |
| Host | smart-b0eafbd1-b044-4266-8844-8b186827b665 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396091716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1396091716 |
| Directory | /workspace/1.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3416654484 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 76554336317 ps |
| CPU time | 561.75 seconds |
| Started | Feb 21 01:18:37 PM PST 24 |
| Finished | Feb 21 01:27:59 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-abade57e-8ab1-40d4-80cd-6b70e8f230f0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416654484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.3416654484 |
| Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.1165225215 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 30201200 ps |
| CPU time | 0.89 seconds |
| Started | Feb 21 01:18:32 PM PST 24 |
| Finished | Feb 21 01:18:34 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-16f8373e-df55-4093-858c-b07c85639982 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165225215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1165225215 |
| Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_regwen.1332452702 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 5487209140 ps |
| CPU time | 292.53 seconds |
| Started | Feb 21 01:18:31 PM PST 24 |
| Finished | Feb 21 01:23:24 PM PST 24 |
| Peak memory | 342764 kb |
| Host | smart-f84fe7e6-a579-4a60-b223-b78924061bc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332452702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1332452702 |
| Directory | /workspace/1.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.1245319616 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 169963280 ps |
| CPU time | 1.69 seconds |
| Started | Feb 21 01:18:55 PM PST 24 |
| Finished | Feb 21 01:18:57 PM PST 24 |
| Peak memory | 221312 kb |
| Host | smart-ab1bfa0d-2bde-4909-b3fb-f577305bb6a4 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245319616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1245319616 |
| Directory | /workspace/1.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_smoke.3973296312 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 127386402 ps |
| CPU time | 1.55 seconds |
| Started | Feb 21 01:18:18 PM PST 24 |
| Finished | Feb 21 01:18:20 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-2ab7505d-da5e-448a-ac6d-9201932691a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973296312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3973296312 |
| Directory | /workspace/1.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.412034496 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 88944909224 ps |
| CPU time | 2922.63 seconds |
| Started | Feb 21 01:18:25 PM PST 24 |
| Finished | Feb 21 02:07:09 PM PST 24 |
| Peak memory | 374928 kb |
| Host | smart-4d6f08c8-fccf-4b84-a529-d5ef6ca747f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412034496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_stress_all.412034496 |
| Directory | /workspace/1.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1618545724 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3648795971 ps |
| CPU time | 165.46 seconds |
| Started | Feb 21 01:18:35 PM PST 24 |
| Finished | Feb 21 01:21:21 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-39ed0cbd-dc4f-4aea-b8b7-2efafc2460b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618545724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1618545724 |
| Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3805955722 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 102377963 ps |
| CPU time | 34.73 seconds |
| Started | Feb 21 01:18:32 PM PST 24 |
| Finished | Feb 21 01:19:07 PM PST 24 |
| Peak memory | 289064 kb |
| Host | smart-1f21e685-f581-4518-b009-0cfd09c88a0a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805955722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3805955722 |
| Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2016687066 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 6086253750 ps |
| CPU time | 953.69 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:35:15 PM PST 24 |
| Peak memory | 371432 kb |
| Host | smart-d4935eb5-6166-4dbe-ae5e-89e33627ec82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016687066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.2016687066 |
| Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.2633741253 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 18896291 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:19:40 PM PST 24 |
| Finished | Feb 21 01:19:42 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-c38894db-99c3-4a96-8d24-1c5766abcd99 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633741253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2633741253 |
| Directory | /workspace/10.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_bijection.1053078666 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 670617813 ps |
| CPU time | 37.75 seconds |
| Started | Feb 21 01:19:14 PM PST 24 |
| Finished | Feb 21 01:19:52 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-dd919972-ce68-492d-8daa-60936ff7e8dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053078666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .1053078666 |
| Directory | /workspace/10.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_executable.3682076511 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 13032633404 ps |
| CPU time | 1101.66 seconds |
| Started | Feb 21 01:19:14 PM PST 24 |
| Finished | Feb 21 01:37:36 PM PST 24 |
| Peak memory | 367216 kb |
| Host | smart-cc933b19-52df-4d0c-aeaf-fdc5fa906f59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682076511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.3682076511 |
| Directory | /workspace/10.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.1932766864 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 596970454 ps |
| CPU time | 3.62 seconds |
| Started | Feb 21 01:19:20 PM PST 24 |
| Finished | Feb 21 01:19:25 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-d1530c45-f3b4-4b10-ad2a-9ba36ae6618f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932766864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1932766864 |
| Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.4140803265 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 185183269 ps |
| CPU time | 5.3 seconds |
| Started | Feb 21 01:19:20 PM PST 24 |
| Finished | Feb 21 01:19:27 PM PST 24 |
| Peak memory | 226024 kb |
| Host | smart-e2f1655f-00d5-473a-be29-ec7539c8fd2f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140803265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.4140803265 |
| Directory | /workspace/10.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.914893457 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 812564817 ps |
| CPU time | 3.1 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:19:27 PM PST 24 |
| Peak memory | 210776 kb |
| Host | smart-8c29a2ff-4ee9-4fac-ba91-90fe61280ac9 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914893457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_mem_partial_access.914893457 |
| Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.3738713744 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 312127385 ps |
| CPU time | 8.11 seconds |
| Started | Feb 21 01:19:30 PM PST 24 |
| Finished | Feb 21 01:19:39 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-119e6a93-51ad-40e9-b218-04cd52b2fc9c |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738713744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3738713744 |
| Directory | /workspace/10.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.1594691989 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 10126919220 ps |
| CPU time | 426.94 seconds |
| Started | Feb 21 01:19:14 PM PST 24 |
| Finished | Feb 21 01:26:22 PM PST 24 |
| Peak memory | 355144 kb |
| Host | smart-03fbdfd8-8b65-47bd-9f4d-c38e88a5067c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594691989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.1594691989 |
| Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.1497690787 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 827633855 ps |
| CPU time | 32.49 seconds |
| Started | Feb 21 01:19:18 PM PST 24 |
| Finished | Feb 21 01:19:50 PM PST 24 |
| Peak memory | 296892 kb |
| Host | smart-cab7fb44-1d3d-491f-96a6-d55acffb6d33 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497690787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.1497690787 |
| Directory | /workspace/10.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1294170832 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 11028846341 ps |
| CPU time | 279.41 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:23:41 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-b79b9a84-0107-4afc-8887-8b4a525099a6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294170832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.1294170832 |
| Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.3147417803 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 46415386 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 01:19:40 PM PST 24 |
| Finished | Feb 21 01:19:42 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-85a37054-a81d-4bda-8b6f-dba48ad78fd3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147417803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3147417803 |
| Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_regwen.2885403097 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 65443124649 ps |
| CPU time | 2278.17 seconds |
| Started | Feb 21 01:19:29 PM PST 24 |
| Finished | Feb 21 01:57:27 PM PST 24 |
| Peak memory | 370452 kb |
| Host | smart-bb8488ec-e099-4f65-8de3-7c6415c01365 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885403097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2885403097 |
| Directory | /workspace/10.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_smoke.2501691362 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1127217286 ps |
| CPU time | 78.63 seconds |
| Started | Feb 21 01:19:13 PM PST 24 |
| Finished | Feb 21 01:20:32 PM PST 24 |
| Peak memory | 326288 kb |
| Host | smart-245b310d-8715-46d3-aef4-682fabc6567a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501691362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2501691362 |
| Directory | /workspace/10.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.1070418216 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 114987769569 ps |
| CPU time | 2657.39 seconds |
| Started | Feb 21 01:19:25 PM PST 24 |
| Finished | Feb 21 02:03:43 PM PST 24 |
| Peak memory | 375460 kb |
| Host | smart-e425b350-e6d9-4e24-954c-88d6ca4ef5b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070418216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.1070418216 |
| Directory | /workspace/10.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.4102490519 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1657185150 ps |
| CPU time | 160.48 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:22:00 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-9df2ce38-f134-4a0c-b095-8bb00720d132 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102490519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.4102490519 |
| Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2385836340 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 294226173 ps |
| CPU time | 88.12 seconds |
| Started | Feb 21 01:19:21 PM PST 24 |
| Finished | Feb 21 01:20:51 PM PST 24 |
| Peak memory | 357036 kb |
| Host | smart-6cb5aed8-278f-42a6-8dc3-105a06d6c0f9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385836340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2385836340 |
| Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1976826779 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 11349481684 ps |
| CPU time | 1165.08 seconds |
| Started | Feb 21 01:19:36 PM PST 24 |
| Finished | Feb 21 01:39:02 PM PST 24 |
| Peak memory | 373488 kb |
| Host | smart-1665da5e-6039-4a96-a7a1-6dad11093e3b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976826779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.1976826779 |
| Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.3841635520 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 16750295 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:19:50 PM PST 24 |
| Finished | Feb 21 01:19:51 PM PST 24 |
| Peak memory | 201732 kb |
| Host | smart-ef750365-f751-459d-9c3f-cde5cba73222 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841635520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3841635520 |
| Directory | /workspace/11.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_bijection.1193348135 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5032611923 ps |
| CPU time | 22.2 seconds |
| Started | Feb 21 01:19:40 PM PST 24 |
| Finished | Feb 21 01:20:03 PM PST 24 |
| Peak memory | 203028 kb |
| Host | smart-ad8e66f4-e909-4919-9751-86a4752fc427 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193348135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .1193348135 |
| Directory | /workspace/11.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_executable.3638445981 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 26760027626 ps |
| CPU time | 1022.19 seconds |
| Started | Feb 21 01:20:00 PM PST 24 |
| Finished | Feb 21 01:37:05 PM PST 24 |
| Peak memory | 373528 kb |
| Host | smart-64146d32-3126-4e2b-a719-f6cfcfb152fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638445981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.3638445981 |
| Directory | /workspace/11.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.2736786189 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 291234606 ps |
| CPU time | 48.51 seconds |
| Started | Feb 21 01:19:42 PM PST 24 |
| Finished | Feb 21 01:20:31 PM PST 24 |
| Peak memory | 327528 kb |
| Host | smart-f3d6af71-896d-48b4-8ac8-fb56ccd6e782 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736786189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.2736786189 |
| Directory | /workspace/11.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2866939540 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 46843624 ps |
| CPU time | 2.9 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:19:57 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-9742eda8-de4d-4262-846b-8d91a2f0a584 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866939540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.2866939540 |
| Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.4047447666 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 233402279 ps |
| CPU time | 4.98 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:19:59 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-e8880bea-55da-47c1-b50c-2c422da72dec |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047447666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.4047447666 |
| Directory | /workspace/11.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.3956142775 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 159720678614 ps |
| CPU time | 1559.97 seconds |
| Started | Feb 21 01:19:37 PM PST 24 |
| Finished | Feb 21 01:45:38 PM PST 24 |
| Peak memory | 373512 kb |
| Host | smart-93eada1f-838e-4680-abe7-0631d6b2d693 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956142775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3956142775 |
| Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.2402316705 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 216332814 ps |
| CPU time | 11.9 seconds |
| Started | Feb 21 01:19:45 PM PST 24 |
| Finished | Feb 21 01:19:58 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-cc467cf3-d752-47f2-b401-4a236a6428bc |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402316705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.2402316705 |
| Directory | /workspace/11.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2239183384 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 47080593462 ps |
| CPU time | 286.02 seconds |
| Started | Feb 21 01:19:45 PM PST 24 |
| Finished | Feb 21 01:24:32 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-a6c94bce-b044-405e-a4f5-93b6975c98a3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239183384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2239183384 |
| Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.3665146433 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 57569564 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:19:44 PM PST 24 |
| Peak memory | 202868 kb |
| Host | smart-49d5286e-91da-4149-9872-9aa2ae6c7413 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665146433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3665146433 |
| Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_regwen.3506790675 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 16417925894 ps |
| CPU time | 743.41 seconds |
| Started | Feb 21 01:19:28 PM PST 24 |
| Finished | Feb 21 01:31:51 PM PST 24 |
| Peak memory | 365384 kb |
| Host | smart-d311edee-a203-465e-abb9-3efc0957ee3f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506790675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3506790675 |
| Directory | /workspace/11.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_smoke.2825130513 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 782532192 ps |
| CPU time | 48.24 seconds |
| Started | Feb 21 01:19:30 PM PST 24 |
| Finished | Feb 21 01:20:19 PM PST 24 |
| Peak memory | 298372 kb |
| Host | smart-ecfd9e76-c223-489b-ad27-dd677937b1dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825130513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2825130513 |
| Directory | /workspace/11.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.835006076 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 258351968599 ps |
| CPU time | 3825.45 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 02:23:28 PM PST 24 |
| Peak memory | 382724 kb |
| Host | smart-6dec4df6-9ab0-498a-8249-764a5c723aa0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835006076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_stress_all.835006076 |
| Directory | /workspace/11.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2833695237 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 15121282862 ps |
| CPU time | 366.82 seconds |
| Started | Feb 21 01:19:21 PM PST 24 |
| Finished | Feb 21 01:25:30 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-c7398ffa-826c-45dd-beec-fda9867b3bd3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833695237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.2833695237 |
| Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2276815116 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 76238153 ps |
| CPU time | 11.89 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:19:52 PM PST 24 |
| Peak memory | 251692 kb |
| Host | smart-d40f4e91-b07e-4695-a6f2-edc8d23135f9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276815116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2276815116 |
| Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1348459824 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4734768593 ps |
| CPU time | 1291.88 seconds |
| Started | Feb 21 01:19:16 PM PST 24 |
| Finished | Feb 21 01:40:48 PM PST 24 |
| Peak memory | 373540 kb |
| Host | smart-6b8ff2a7-94a2-4251-a9bf-8dfb37b3c838 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348459824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.1348459824 |
| Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.21416091 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 36878352 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:19:22 PM PST 24 |
| Peak memory | 201704 kb |
| Host | smart-9e6bdedc-d7b7-4b20-850d-6116e2c2907c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21416091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_alert_test.21416091 |
| Directory | /workspace/12.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_bijection.3593537906 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 269492039 ps |
| CPU time | 17.97 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:17 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-08111d26-c83e-4169-be02-1ee781b054b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593537906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .3593537906 |
| Directory | /workspace/12.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_executable.895489930 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 139991461950 ps |
| CPU time | 899.47 seconds |
| Started | Feb 21 01:19:17 PM PST 24 |
| Finished | Feb 21 01:34:16 PM PST 24 |
| Peak memory | 373968 kb |
| Host | smart-a9a221ae-8172-470a-b75e-d4d5cc188406 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895489930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executabl e.895489930 |
| Directory | /workspace/12.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.3601174541 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 376764767 ps |
| CPU time | 1.58 seconds |
| Started | Feb 21 01:19:12 PM PST 24 |
| Finished | Feb 21 01:19:14 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-4452534e-056d-4879-a0b7-74783aaf4f64 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601174541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.3601174541 |
| Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.3209937346 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 61632446 ps |
| CPU time | 4.23 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:19:23 PM PST 24 |
| Peak memory | 219068 kb |
| Host | smart-fb6f40fe-7d52-4d4d-905d-27d36e00e535 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209937346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3209937346 |
| Directory | /workspace/12.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.939675829 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 177971696 ps |
| CPU time | 2.93 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 01:19:19 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-bd112bb8-f490-46f8-88cf-7258c7388282 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939675829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_mem_partial_access.939675829 |
| Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.3675784721 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 654691441 ps |
| CPU time | 9.92 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 01:19:26 PM PST 24 |
| Peak memory | 202828 kb |
| Host | smart-a983b3d3-62e8-4190-adf4-11ab0559194d |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675784721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.3675784721 |
| Directory | /workspace/12.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.573648327 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 11091676652 ps |
| CPU time | 774.76 seconds |
| Started | Feb 21 01:20:01 PM PST 24 |
| Finished | Feb 21 01:32:57 PM PST 24 |
| Peak memory | 359248 kb |
| Host | smart-26187e64-9b51-4f9e-b7f8-9a24de44bada |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573648327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multip le_keys.573648327 |
| Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.1594533384 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 648118819 ps |
| CPU time | 7.84 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:20:08 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-108a55de-b4aa-4215-b262-d06d5cc46ec9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594533384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.1594533384 |
| Directory | /workspace/12.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.474757897 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 15771265832 ps |
| CPU time | 352.63 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:25:51 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-7180d1e6-b285-4c59-babc-7970739522db |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474757897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.sram_ctrl_partial_access_b2b.474757897 |
| Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.3679922603 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 85407264 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:00 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-373e5416-677d-470a-90bc-6ddc96d0faf5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679922603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3679922603 |
| Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_regwen.896355806 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 14655867172 ps |
| CPU time | 783.91 seconds |
| Started | Feb 21 01:19:52 PM PST 24 |
| Finished | Feb 21 01:32:56 PM PST 24 |
| Peak memory | 373744 kb |
| Host | smart-3ad2cce7-810c-489d-bc69-fbae316f57ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896355806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.896355806 |
| Directory | /workspace/12.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_smoke.2337947464 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 931797732 ps |
| CPU time | 9.52 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:20:12 PM PST 24 |
| Peak memory | 238204 kb |
| Host | smart-a92747fa-9835-4c6a-a6e9-4228b1fa721c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337947464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2337947464 |
| Directory | /workspace/12.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.2172402438 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 10862942897 ps |
| CPU time | 1770.59 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 01:48:46 PM PST 24 |
| Peak memory | 374304 kb |
| Host | smart-aefb67b2-b4f5-4c95-9bc0-9809ed73d066 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172402438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.2172402438 |
| Directory | /workspace/12.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.733195403 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1975985671 ps |
| CPU time | 183.32 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:23:05 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-b8ad4717-9e6b-4223-86d6-87309b172240 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733195403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_stress_pipeline.733195403 |
| Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3661708837 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 117480780 ps |
| CPU time | 49.69 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:49 PM PST 24 |
| Peak memory | 310304 kb |
| Host | smart-e1bc47a8-77f4-4b8f-89d8-a8c065babe8a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661708837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.3661708837 |
| Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1013311754 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2641629185 ps |
| CPU time | 918.65 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:34:43 PM PST 24 |
| Peak memory | 374464 kb |
| Host | smart-377d3a09-aa56-47c0-a099-9c3866d6daac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013311754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1013311754 |
| Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.924464185 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 15317373 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:19:25 PM PST 24 |
| Peak memory | 201732 kb |
| Host | smart-bdb6edf3-7c74-41a2-9f97-889fafcb886e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924464185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.924464185 |
| Directory | /workspace/13.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_bijection.949836356 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4368821741 ps |
| CPU time | 69.47 seconds |
| Started | Feb 21 01:19:22 PM PST 24 |
| Finished | Feb 21 01:20:33 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-8ec3c28d-138c-4c80-8f72-82bc19f13897 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949836356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection. 949836356 |
| Directory | /workspace/13.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_executable.3960514661 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 43524979066 ps |
| CPU time | 782.65 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:32:45 PM PST 24 |
| Peak memory | 373036 kb |
| Host | smart-51bb25ce-65ea-4882-91f4-6a70004c3855 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960514661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.3960514661 |
| Directory | /workspace/13.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.2894223680 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2287503426 ps |
| CPU time | 9.28 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:19:34 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-4cfd303f-1eea-4153-8da7-9570b74003a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894223680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.2894223680 |
| Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.2507645427 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 562572308 ps |
| CPU time | 158.43 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:22:03 PM PST 24 |
| Peak memory | 365180 kb |
| Host | smart-98bcd39f-15c8-4cbc-9706-ad3ff80e89a2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507645427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.2507645427 |
| Directory | /workspace/13.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2017810701 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 444507687 ps |
| CPU time | 2.79 seconds |
| Started | Feb 21 01:19:36 PM PST 24 |
| Finished | Feb 21 01:19:40 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-2c2b651a-0ab7-49ca-be8d-a222e3e75fd3 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017810701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.2017810701 |
| Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.1076944630 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 140939825 ps |
| CPU time | 8.27 seconds |
| Started | Feb 21 01:19:28 PM PST 24 |
| Finished | Feb 21 01:19:36 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-6dfb607c-bf67-48f6-abf1-e9ed4b34b430 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076944630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.1076944630 |
| Directory | /workspace/13.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.1860073372 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 26717657134 ps |
| CPU time | 1116.57 seconds |
| Started | Feb 21 01:19:24 PM PST 24 |
| Finished | Feb 21 01:38:01 PM PST 24 |
| Peak memory | 370480 kb |
| Host | smart-e38e34bb-b8df-4626-a75e-d00b86dbe43f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860073372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.1860073372 |
| Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.1036775976 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 697856029 ps |
| CPU time | 2.54 seconds |
| Started | Feb 21 01:19:36 PM PST 24 |
| Finished | Feb 21 01:19:40 PM PST 24 |
| Peak memory | 205656 kb |
| Host | smart-f755314a-3e8c-46ab-bfce-6ec96967ec86 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036775976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.1036775976 |
| Directory | /workspace/13.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.104921992 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 6048960953 ps |
| CPU time | 413.41 seconds |
| Started | Feb 21 01:19:17 PM PST 24 |
| Finished | Feb 21 01:26:10 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-b365f79b-2f6d-4c71-bcfe-e9553fb6b4ea |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104921992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.sram_ctrl_partial_access_b2b.104921992 |
| Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.276692963 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 28423034 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 01:19:43 PM PST 24 |
| Finished | Feb 21 01:19:45 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-92932e24-f2d3-4a43-af2a-732b12535340 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276692963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.276692963 |
| Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3642962410 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3317085557 ps |
| CPU time | 110.72 seconds |
| Started | Feb 21 01:19:43 PM PST 24 |
| Finished | Feb 21 01:21:35 PM PST 24 |
| Peak memory | 342796 kb |
| Host | smart-391c09d7-07c3-40f3-beb2-b4bbe80f0c16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642962410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3642962410 |
| Directory | /workspace/13.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_smoke.1711949715 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 656952621 ps |
| CPU time | 10.81 seconds |
| Started | Feb 21 01:19:27 PM PST 24 |
| Finished | Feb 21 01:19:38 PM PST 24 |
| Peak memory | 242560 kb |
| Host | smart-1d94ebb4-858c-48f5-aefa-e65c0e3ea5b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711949715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1711949715 |
| Directory | /workspace/13.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.2069266543 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 158862705266 ps |
| CPU time | 3231.77 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 02:13:16 PM PST 24 |
| Peak memory | 368316 kb |
| Host | smart-0a42c6ae-ec22-4020-838e-4057b54ca306 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069266543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.2069266543 |
| Directory | /workspace/13.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1750060773 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 629191555 ps |
| CPU time | 12.65 seconds |
| Started | Feb 21 01:19:24 PM PST 24 |
| Finished | Feb 21 01:19:37 PM PST 24 |
| Peak memory | 251728 kb |
| Host | smart-612b3be1-61e4-4f95-8714-5b169e6ec5fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750060773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1750060773 |
| Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1232727141 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1422082228 ps |
| CPU time | 529.21 seconds |
| Started | Feb 21 01:19:28 PM PST 24 |
| Finished | Feb 21 01:28:18 PM PST 24 |
| Peak memory | 359992 kb |
| Host | smart-ebabe352-c654-44b6-a1f4-9d58893b5575 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232727141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.1232727141 |
| Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.3047351020 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 38521404 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:19:26 PM PST 24 |
| Finished | Feb 21 01:19:27 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-cba41c38-49a3-45ff-9469-4934d63fcbb8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047351020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3047351020 |
| Directory | /workspace/14.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_bijection.1168570470 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3473102073 ps |
| CPU time | 51.67 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:20:16 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-1e7dd742-6f28-4fe1-a88f-80d2b779e610 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168570470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .1168570470 |
| Directory | /workspace/14.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_executable.2193753649 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 16713582552 ps |
| CPU time | 1112.48 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:37:53 PM PST 24 |
| Peak memory | 373492 kb |
| Host | smart-33f1e630-fdf7-4254-b31c-de28c9207fee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193753649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.2193753649 |
| Directory | /workspace/14.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.1796720595 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 478654044 ps |
| CPU time | 6.41 seconds |
| Started | Feb 21 01:19:30 PM PST 24 |
| Finished | Feb 21 01:19:37 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-c4f9d82c-b22c-4264-8c3d-9276fa7883a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796720595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.1796720595 |
| Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.3561858847 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 135537293 ps |
| CPU time | 85.4 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:20:50 PM PST 24 |
| Peak memory | 361900 kb |
| Host | smart-45f9c00c-95ca-4a61-be46-d13892011754 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561858847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.3561858847 |
| Directory | /workspace/14.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3493995984 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 267031547 ps |
| CPU time | 4.76 seconds |
| Started | Feb 21 01:19:22 PM PST 24 |
| Finished | Feb 21 01:19:28 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-9806fb86-bdd7-4d2b-a15e-4e4aea979a94 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493995984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3493995984 |
| Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.2638506159 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 155473176 ps |
| CPU time | 8.02 seconds |
| Started | Feb 21 01:19:32 PM PST 24 |
| Finished | Feb 21 01:19:40 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-fd11a5ab-8793-4894-9b71-4529012623b1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638506159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.2638506159 |
| Directory | /workspace/14.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.1456445632 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 36926423293 ps |
| CPU time | 1448.87 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:43:51 PM PST 24 |
| Peak memory | 374576 kb |
| Host | smart-04b76f0d-8a4c-476c-9f2f-b70338289baf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456445632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.1456445632 |
| Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.882091436 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 196930647 ps |
| CPU time | 4.85 seconds |
| Started | Feb 21 01:19:26 PM PST 24 |
| Finished | Feb 21 01:19:31 PM PST 24 |
| Peak memory | 218920 kb |
| Host | smart-10b3b8f5-400c-4d6c-9dd3-f2b975d78600 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882091436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s ram_ctrl_partial_access.882091436 |
| Directory | /workspace/14.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1386685446 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 6294885093 ps |
| CPU time | 229.34 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:23:14 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-bdf58208-1b70-4988-81e8-d8f741df5540 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386685446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.1386685446 |
| Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.2443117351 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 89878191 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:19:22 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-d45b9b39-8a25-4d85-946f-1756a3de5561 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443117351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2443117351 |
| Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_regwen.201732321 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 54023745974 ps |
| CPU time | 1905.5 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:51:10 PM PST 24 |
| Peak memory | 369324 kb |
| Host | smart-d4e8729d-50ce-40d4-93cf-339c0b00a358 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201732321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.201732321 |
| Directory | /workspace/14.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_smoke.3735677174 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 212233084 ps |
| CPU time | 11.01 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:19:35 PM PST 24 |
| Peak memory | 246508 kb |
| Host | smart-31d54f83-5b86-46f9-94d3-bdb0000decf4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735677174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3735677174 |
| Directory | /workspace/14.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3268551167 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 9657196382 ps |
| CPU time | 196.66 seconds |
| Started | Feb 21 01:19:28 PM PST 24 |
| Finished | Feb 21 01:22:45 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-70bf11cf-1827-49c9-a16b-0dc515b38b81 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268551167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.3268551167 |
| Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1026067295 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 661576340 ps |
| CPU time | 88.98 seconds |
| Started | Feb 21 01:19:25 PM PST 24 |
| Finished | Feb 21 01:20:54 PM PST 24 |
| Peak memory | 351660 kb |
| Host | smart-2a0e5b0a-46b9-40cb-b975-ea65cf8569c1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026067295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1026067295 |
| Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3687722315 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 7371927866 ps |
| CPU time | 1444.15 seconds |
| Started | Feb 21 01:19:22 PM PST 24 |
| Finished | Feb 21 01:43:28 PM PST 24 |
| Peak memory | 369408 kb |
| Host | smart-09794696-5d7e-47ea-a682-48740ab07b5c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687722315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.3687722315 |
| Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.3745812215 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 78181076 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:19:31 PM PST 24 |
| Finished | Feb 21 01:19:32 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-5cca52a5-0cf0-4fb1-9e60-c46f6da2a863 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745812215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3745812215 |
| Directory | /workspace/15.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_bijection.2774605377 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 6617694454 ps |
| CPU time | 28.82 seconds |
| Started | Feb 21 01:19:26 PM PST 24 |
| Finished | Feb 21 01:19:55 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-d0299613-8f1b-4d5c-aa09-b39205a62a9e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774605377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2774605377 |
| Directory | /workspace/15.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_executable.75057544 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 13519725817 ps |
| CPU time | 1100.99 seconds |
| Started | Feb 21 01:19:22 PM PST 24 |
| Finished | Feb 21 01:37:45 PM PST 24 |
| Peak memory | 374500 kb |
| Host | smart-5356f1da-8b7c-40ec-a40b-e198a6f29a02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75057544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable .75057544 |
| Directory | /workspace/15.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.1200291957 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1900226683 ps |
| CPU time | 7.63 seconds |
| Started | Feb 21 01:19:28 PM PST 24 |
| Finished | Feb 21 01:19:36 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-f28a0529-2bfd-439b-9f27-38f202e80f78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200291957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.1200291957 |
| Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.2524245013 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 127055462 ps |
| CPU time | 76.18 seconds |
| Started | Feb 21 01:19:25 PM PST 24 |
| Finished | Feb 21 01:20:42 PM PST 24 |
| Peak memory | 354276 kb |
| Host | smart-ad4355b2-1f1f-43d2-a92f-f7933312af66 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524245013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.2524245013 |
| Directory | /workspace/15.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1016995967 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 155654848 ps |
| CPU time | 4.98 seconds |
| Started | Feb 21 01:19:30 PM PST 24 |
| Finished | Feb 21 01:19:36 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-d8aeb987-3a48-4d97-b7a8-c8dca8964d7a |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016995967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.1016995967 |
| Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.3970052053 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 516873938 ps |
| CPU time | 8.14 seconds |
| Started | Feb 21 01:19:46 PM PST 24 |
| Finished | Feb 21 01:19:54 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-190770b3-dd02-4fd5-8d21-c79e06dc0de2 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970052053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.3970052053 |
| Directory | /workspace/15.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.688878024 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 31323383509 ps |
| CPU time | 1120.97 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:38:23 PM PST 24 |
| Peak memory | 372352 kb |
| Host | smart-a316a3ee-6623-4c03-a6cf-e00948b89de1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688878024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip le_keys.688878024 |
| Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.521811414 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2735023186 ps |
| CPU time | 13.37 seconds |
| Started | Feb 21 01:19:31 PM PST 24 |
| Finished | Feb 21 01:19:45 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-df8ba07f-2afc-4961-a2b8-30d3e56ca11f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521811414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s ram_ctrl_partial_access.521811414 |
| Directory | /workspace/15.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3399790402 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 6519005164 ps |
| CPU time | 226.98 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:23:08 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-3280782c-61c6-4157-93ce-64cf6f40e688 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399790402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.3399790402 |
| Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.3773690164 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 83488269 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 01:19:29 PM PST 24 |
| Finished | Feb 21 01:19:30 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-d3eea052-a642-4827-a58d-4f8e7635ffe0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773690164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3773690164 |
| Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_regwen.1434311339 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3727413475 ps |
| CPU time | 608.99 seconds |
| Started | Feb 21 01:19:28 PM PST 24 |
| Finished | Feb 21 01:29:37 PM PST 24 |
| Peak memory | 368280 kb |
| Host | smart-ccc7b304-81cb-4bc4-98fc-a645983a1c82 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434311339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1434311339 |
| Directory | /workspace/15.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_smoke.3888384473 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 165229149 ps |
| CPU time | 3.72 seconds |
| Started | Feb 21 01:19:34 PM PST 24 |
| Finished | Feb 21 01:19:39 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-54252086-93fe-418a-b126-67ffac4342ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888384473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3888384473 |
| Directory | /workspace/15.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2312186503 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2263966493 ps |
| CPU time | 225.97 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:23:07 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-0d2e93ef-9a43-4508-bb58-d584b4e7966f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312186503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2312186503 |
| Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1819991722 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 98631638 ps |
| CPU time | 25.1 seconds |
| Started | Feb 21 01:19:27 PM PST 24 |
| Finished | Feb 21 01:19:53 PM PST 24 |
| Peak memory | 284488 kb |
| Host | smart-2cd835d2-9f6e-4cf7-966c-45bedb36a56c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819991722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1819991722 |
| Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1333455754 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4803922202 ps |
| CPU time | 1861.66 seconds |
| Started | Feb 21 01:19:38 PM PST 24 |
| Finished | Feb 21 01:50:42 PM PST 24 |
| Peak memory | 373540 kb |
| Host | smart-723bf419-b820-4822-bc09-075ca5ab353f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333455754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.1333455754 |
| Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.3316408708 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 85877782 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:19:35 PM PST 24 |
| Finished | Feb 21 01:19:37 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-148ca4d5-fa73-401f-8826-8365a676ee68 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316408708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3316408708 |
| Directory | /workspace/16.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_bijection.3412246676 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 905818407 ps |
| CPU time | 56.68 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:55 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-e95f1959-7e07-4ece-a344-ae834190db2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412246676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .3412246676 |
| Directory | /workspace/16.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_executable.3884081854 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 73369156155 ps |
| CPU time | 1349.65 seconds |
| Started | Feb 21 01:19:27 PM PST 24 |
| Finished | Feb 21 01:41:57 PM PST 24 |
| Peak memory | 374592 kb |
| Host | smart-ac1e3e39-063f-4dc7-9a1a-40e54479e71b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884081854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.3884081854 |
| Directory | /workspace/16.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.1658484274 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1899826381 ps |
| CPU time | 8.31 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:08 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-293453d4-31d5-4885-8c5d-466597a1c133 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658484274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.1658484274 |
| Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.588266218 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 473704950 ps |
| CPU time | 101.83 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:21:22 PM PST 24 |
| Peak memory | 354896 kb |
| Host | smart-2e19fa80-2708-430a-89fd-d19db578498c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588266218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_max_throughput.588266218 |
| Directory | /workspace/16.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.740965151 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 295995428 ps |
| CPU time | 5.1 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:19:59 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-5bbc7eab-9f75-4b9f-9997-988a6b2d87f3 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740965151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_mem_partial_access.740965151 |
| Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.3315839250 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 138632579 ps |
| CPU time | 8.31 seconds |
| Started | Feb 21 01:19:43 PM PST 24 |
| Finished | Feb 21 01:19:51 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-d6fa0323-ac4f-47d3-9deb-a0e0358fb062 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315839250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.3315839250 |
| Directory | /workspace/16.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.3860919163 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7371851555 ps |
| CPU time | 737.9 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:32:21 PM PST 24 |
| Peak memory | 374492 kb |
| Host | smart-1a50ec36-f7a8-413f-a3cd-a4db67cbd6c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860919163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3860919163 |
| Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.3004419090 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 185169286 ps |
| CPU time | 53.82 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:20:57 PM PST 24 |
| Peak memory | 339384 kb |
| Host | smart-0b6ad5d1-75a3-4654-8183-cf75c6437a4e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004419090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3004419090 |
| Directory | /workspace/16.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2010438963 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 10033371763 ps |
| CPU time | 178.28 seconds |
| Started | Feb 21 01:19:42 PM PST 24 |
| Finished | Feb 21 01:22:41 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-74d15ea2-90b5-4895-ba75-b955eee43959 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010438963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2010438963 |
| Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.2877854727 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 27179462 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:19:42 PM PST 24 |
| Peak memory | 202932 kb |
| Host | smart-0129e165-8017-4c3c-8a99-ae6565e21f4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877854727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2877854727 |
| Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2924510017 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 41809245231 ps |
| CPU time | 1222.74 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:40:21 PM PST 24 |
| Peak memory | 370596 kb |
| Host | smart-8c044ef7-f16c-4548-84bd-8d3bfcab56c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924510017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2924510017 |
| Directory | /workspace/16.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_smoke.376242496 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 15605206127 ps |
| CPU time | 22.28 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:20:04 PM PST 24 |
| Peak memory | 202836 kb |
| Host | smart-7bc52689-7b7a-42ad-9978-1d877e3441cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376242496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.376242496 |
| Directory | /workspace/16.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.821043011 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4098957371 ps |
| CPU time | 952.49 seconds |
| Started | Feb 21 01:19:54 PM PST 24 |
| Finished | Feb 21 01:35:48 PM PST 24 |
| Peak memory | 369712 kb |
| Host | smart-efcd4f93-bb0d-42de-8a77-c5fd09a66b42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821043011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_stress_all.821043011 |
| Directory | /workspace/16.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.429596634 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7690015744 ps |
| CPU time | 377.73 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:26:12 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-5194566e-80af-42c5-ba26-2f318d88fff0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429596634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_stress_pipeline.429596634 |
| Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1464152263 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 351467048 ps |
| CPU time | 11.55 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:19:54 PM PST 24 |
| Peak memory | 241080 kb |
| Host | smart-1dfc89bb-9aab-4613-947b-cecb1107c62f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464152263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1464152263 |
| Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2022731116 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 9257296265 ps |
| CPU time | 830.19 seconds |
| Started | Feb 21 01:19:37 PM PST 24 |
| Finished | Feb 21 01:33:29 PM PST 24 |
| Peak memory | 373496 kb |
| Host | smart-9adb71a7-4dde-44bc-abbe-e92fefde9019 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022731116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.2022731116 |
| Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_bijection.2164669660 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1340279245 ps |
| CPU time | 25.56 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:25 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-1a57470d-72aa-4117-a856-8998f0b3ff16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164669660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .2164669660 |
| Directory | /workspace/17.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_executable.1035158134 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 83959426267 ps |
| CPU time | 1186.27 seconds |
| Started | Feb 21 01:19:37 PM PST 24 |
| Finished | Feb 21 01:39:25 PM PST 24 |
| Peak memory | 367084 kb |
| Host | smart-ccaa41c2-9a8c-4bf9-bd4d-06a8da8006bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035158134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.1035158134 |
| Directory | /workspace/17.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.268531824 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1732227921 ps |
| CPU time | 6.09 seconds |
| Started | Feb 21 01:19:52 PM PST 24 |
| Finished | Feb 21 01:19:58 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-42860ad2-2343-4117-bf76-6425555de925 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268531824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc alation.268531824 |
| Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.2426543562 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 358116743 ps |
| CPU time | 15.28 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:20:18 PM PST 24 |
| Peak memory | 256100 kb |
| Host | smart-5393fd1b-3382-4fbd-a9b5-5305b1082d46 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426543562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.2426543562 |
| Directory | /workspace/17.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2364024015 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 341538026 ps |
| CPU time | 3.08 seconds |
| Started | Feb 21 01:19:29 PM PST 24 |
| Finished | Feb 21 01:19:32 PM PST 24 |
| Peak memory | 215872 kb |
| Host | smart-1ca3cda4-faff-44c9-81b1-c671979012e6 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364024015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.2364024015 |
| Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.1088787038 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 141947045 ps |
| CPU time | 8.38 seconds |
| Started | Feb 21 01:19:40 PM PST 24 |
| Finished | Feb 21 01:19:49 PM PST 24 |
| Peak memory | 202864 kb |
| Host | smart-c704a34c-19ad-472d-afdc-e24dce43e99e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088787038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.1088787038 |
| Directory | /workspace/17.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.3210748683 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4384421527 ps |
| CPU time | 779.9 seconds |
| Started | Feb 21 01:19:43 PM PST 24 |
| Finished | Feb 21 01:32:44 PM PST 24 |
| Peak memory | 370824 kb |
| Host | smart-8a6c6e61-dbba-46b6-929c-6f32c948bf7e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210748683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.3210748683 |
| Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.2846858279 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 621955803 ps |
| CPU time | 48 seconds |
| Started | Feb 21 01:19:54 PM PST 24 |
| Finished | Feb 21 01:20:44 PM PST 24 |
| Peak memory | 311664 kb |
| Host | smart-e23ac8c1-a3f8-4e12-bb30-2245640b9ea2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846858279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.2846858279 |
| Directory | /workspace/17.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2875265714 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 58423978505 ps |
| CPU time | 366.2 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:25:46 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-f735fa8c-b2b4-404b-9440-cc8d4d35b691 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875265714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.2875265714 |
| Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.436681825 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 29542099 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 01:19:34 PM PST 24 |
| Finished | Feb 21 01:19:35 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-175aeda0-9cfd-4de5-b6e6-8509b40fecdd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436681825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.436681825 |
| Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_regwen.812610487 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 32700744910 ps |
| CPU time | 1133.81 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:38:34 PM PST 24 |
| Peak memory | 374556 kb |
| Host | smart-b9311a55-eb4f-48d7-a542-90c5fde21298 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812610487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.812610487 |
| Directory | /workspace/17.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_smoke.4049265762 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 654559108 ps |
| CPU time | 92.86 seconds |
| Started | Feb 21 01:19:37 PM PST 24 |
| Finished | Feb 21 01:21:11 PM PST 24 |
| Peak memory | 348420 kb |
| Host | smart-110cf6af-216b-4a4f-aa00-c97f29ec3192 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049265762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4049265762 |
| Directory | /workspace/17.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.61323265 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3759172951 ps |
| CPU time | 736.16 seconds |
| Started | Feb 21 01:19:41 PM PST 24 |
| Finished | Feb 21 01:31:58 PM PST 24 |
| Peak memory | 373120 kb |
| Host | smart-03855d5e-4d7b-420b-b166-d6d2ae7d2b96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61323265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.sram_ctrl_stress_all.61323265 |
| Directory | /workspace/17.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3576823058 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 17885647047 ps |
| CPU time | 320.15 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:25:14 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-98d82695-291d-40bf-a6b0-7738c926e076 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576823058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3576823058 |
| Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2407574536 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 330029427 ps |
| CPU time | 3.9 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:19:58 PM PST 24 |
| Peak memory | 219076 kb |
| Host | smart-6d6ebd0f-5dd8-4a2a-9a3c-086d07570901 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407574536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2407574536 |
| Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.616937795 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1842924308 ps |
| CPU time | 192.03 seconds |
| Started | Feb 21 01:19:35 PM PST 24 |
| Finished | Feb 21 01:22:48 PM PST 24 |
| Peak memory | 291216 kb |
| Host | smart-0f87b50c-57bf-4224-9e6e-96bf2a835c77 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616937795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_access_during_key_req.616937795 |
| Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.3779978820 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 17729747 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:20:01 PM PST 24 |
| Finished | Feb 21 01:20:03 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-27733b2a-0a98-4a39-ad1d-e950efa77841 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779978820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3779978820 |
| Directory | /workspace/18.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_bijection.2816427923 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1633719352 ps |
| CPU time | 51.97 seconds |
| Started | Feb 21 01:19:43 PM PST 24 |
| Finished | Feb 21 01:20:36 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-7e199713-d9d4-4f2c-86ee-008663b43822 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816427923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2816427923 |
| Directory | /workspace/18.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_executable.102595682 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 4210716258 ps |
| CPU time | 530 seconds |
| Started | Feb 21 01:19:35 PM PST 24 |
| Finished | Feb 21 01:28:26 PM PST 24 |
| Peak memory | 366320 kb |
| Host | smart-76c39aef-e6db-4d52-828a-d8ed1a0892aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102595682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executabl e.102595682 |
| Directory | /workspace/18.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.3067394763 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5797069859 ps |
| CPU time | 13.13 seconds |
| Started | Feb 21 01:19:44 PM PST 24 |
| Finished | Feb 21 01:19:58 PM PST 24 |
| Peak memory | 211056 kb |
| Host | smart-8d29f781-4d91-4202-8a3c-1ffa56e6a1f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067394763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.3067394763 |
| Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.3265701898 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 98030966 ps |
| CPU time | 41.18 seconds |
| Started | Feb 21 01:19:35 PM PST 24 |
| Finished | Feb 21 01:20:17 PM PST 24 |
| Peak memory | 304748 kb |
| Host | smart-a82a181e-a337-4c17-af16-2bea49228bab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265701898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.3265701898 |
| Directory | /workspace/18.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1176217638 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 119957430 ps |
| CPU time | 4.66 seconds |
| Started | Feb 21 01:19:42 PM PST 24 |
| Finished | Feb 21 01:19:47 PM PST 24 |
| Peak memory | 211752 kb |
| Host | smart-f6884cab-174f-4d26-8f51-857e8beb097b |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176217638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.1176217638 |
| Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.3776069463 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 75413735 ps |
| CPU time | 4.52 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:20:08 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-b90d3714-7880-466d-8ea4-77b2ac71af64 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776069463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3776069463 |
| Directory | /workspace/18.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.3596473852 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 5389897001 ps |
| CPU time | 1345.57 seconds |
| Started | Feb 21 01:19:29 PM PST 24 |
| Finished | Feb 21 01:41:55 PM PST 24 |
| Peak memory | 375496 kb |
| Host | smart-1340eee8-dc3b-4e63-ba98-619516c0c4cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596473852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.3596473852 |
| Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.3965351187 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2248500350 ps |
| CPU time | 10.13 seconds |
| Started | Feb 21 01:19:36 PM PST 24 |
| Finished | Feb 21 01:19:48 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-b07f8de6-debb-487d-ae3a-fafc8b4238cc |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965351187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.3965351187 |
| Directory | /workspace/18.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2023565148 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 10706185969 ps |
| CPU time | 274.41 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:24:15 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-08f7e60b-6a9c-4812-b209-d81e237302a9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023565148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.2023565148 |
| Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.130244029 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 31510709 ps |
| CPU time | 0.9 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:20:04 PM PST 24 |
| Peak memory | 202280 kb |
| Host | smart-c9ae4781-37ce-4203-9b8f-5346ba3e8928 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130244029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.130244029 |
| Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_regwen.3161042658 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 9009885149 ps |
| CPU time | 288.85 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:24:51 PM PST 24 |
| Peak memory | 339140 kb |
| Host | smart-c9166996-949a-4225-8eb0-740898989936 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161042658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3161042658 |
| Directory | /workspace/18.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_smoke.2347785563 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 97702553 ps |
| CPU time | 0.91 seconds |
| Started | Feb 21 01:19:42 PM PST 24 |
| Finished | Feb 21 01:19:44 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-f67a0f43-d3dc-4742-a86d-a016c5e3543a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347785563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2347785563 |
| Directory | /workspace/18.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.2780807937 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 16029788719 ps |
| CPU time | 2568.11 seconds |
| Started | Feb 21 01:19:45 PM PST 24 |
| Finished | Feb 21 02:02:34 PM PST 24 |
| Peak memory | 374488 kb |
| Host | smart-333209df-207c-4e83-b6aa-9020f944bed4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780807937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.2780807937 |
| Directory | /workspace/18.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3850139506 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3455567245 ps |
| CPU time | 170.27 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:22:31 PM PST 24 |
| Peak memory | 202940 kb |
| Host | smart-15f93132-de09-43f9-ac16-e4b26de9921b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850139506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3850139506 |
| Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.833475141 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 99926715 ps |
| CPU time | 24.07 seconds |
| Started | Feb 21 01:19:30 PM PST 24 |
| Finished | Feb 21 01:19:55 PM PST 24 |
| Peak memory | 284444 kb |
| Host | smart-58f5026a-1aef-4ed5-80bb-dab2fe6fa96e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833475141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.833475141 |
| Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1516407528 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 12537414700 ps |
| CPU time | 1075.1 seconds |
| Started | Feb 21 01:20:00 PM PST 24 |
| Finished | Feb 21 01:37:58 PM PST 24 |
| Peak memory | 372480 kb |
| Host | smart-b12646ea-6211-475c-9964-e98db4fdc877 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516407528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.1516407528 |
| Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.3186147265 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 38605325 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:19:52 PM PST 24 |
| Finished | Feb 21 01:19:53 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-829ec5a6-aeb8-47c4-8cc5-7f46f278c81a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186147265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3186147265 |
| Directory | /workspace/19.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_bijection.3332874916 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 7872219252 ps |
| CPU time | 54.25 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:20:35 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-25b0bde9-4c6f-414d-9188-9d1dd414fa7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332874916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .3332874916 |
| Directory | /workspace/19.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_executable.1926168542 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7077731927 ps |
| CPU time | 522.61 seconds |
| Started | Feb 21 01:19:51 PM PST 24 |
| Finished | Feb 21 01:28:34 PM PST 24 |
| Peak memory | 373496 kb |
| Host | smart-cb290923-ced4-42d6-9731-aab74158f1aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926168542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.1926168542 |
| Directory | /workspace/19.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.1308223076 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 630980324 ps |
| CPU time | 9.09 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:20:11 PM PST 24 |
| Peak memory | 211080 kb |
| Host | smart-ef8aef5b-d79c-44c7-b419-a705c688a2de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308223076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1308223076 |
| Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.3124733914 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 934757291 ps |
| CPU time | 78.55 seconds |
| Started | Feb 21 01:19:51 PM PST 24 |
| Finished | Feb 21 01:21:09 PM PST 24 |
| Peak memory | 343784 kb |
| Host | smart-5fc82fcc-efa3-49f7-aa55-fc6eec746b41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124733914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.3124733914 |
| Directory | /workspace/19.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2432705988 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 172080307 ps |
| CPU time | 2.95 seconds |
| Started | Feb 21 01:19:43 PM PST 24 |
| Finished | Feb 21 01:19:46 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-cc54838c-9821-4b18-87c8-51deb2c0bf53 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432705988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.2432705988 |
| Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.3905986526 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1313531356 ps |
| CPU time | 5.54 seconds |
| Started | Feb 21 01:19:43 PM PST 24 |
| Finished | Feb 21 01:19:49 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-985c2665-b940-484b-9bb3-4cd7f27d1a62 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905986526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3905986526 |
| Directory | /workspace/19.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.3458173166 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 20563372650 ps |
| CPU time | 413.36 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:26:34 PM PST 24 |
| Peak memory | 371800 kb |
| Host | smart-fbbed5a1-5cd2-4031-8e64-400b21662b7e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458173166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.3458173166 |
| Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.3676566218 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 150581649 ps |
| CPU time | 5.2 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:20:07 PM PST 24 |
| Peak memory | 220088 kb |
| Host | smart-b3cdf58f-2532-4d21-b026-6378d968eea7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676566218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.3676566218 |
| Directory | /workspace/19.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1591639164 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 81225850663 ps |
| CPU time | 230.96 seconds |
| Started | Feb 21 01:20:02 PM PST 24 |
| Finished | Feb 21 01:23:54 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-baad1bbc-ea65-4452-a840-9a252da3b2a2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591639164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.1591639164 |
| Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.4075592748 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 27892057 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 01:19:42 PM PST 24 |
| Finished | Feb 21 01:19:44 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-136ffb94-fb8c-43a7-8a54-dfc87e15dd70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075592748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.4075592748 |
| Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_regwen.168382716 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1600984389 ps |
| CPU time | 180.89 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:22:41 PM PST 24 |
| Peak memory | 364016 kb |
| Host | smart-752a6128-b807-4237-ae37-a1c379a9e992 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168382716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.168382716 |
| Directory | /workspace/19.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_smoke.2992311476 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 77508976 ps |
| CPU time | 7.87 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:20:11 PM PST 24 |
| Peak memory | 232680 kb |
| Host | smart-bf09ad3a-3d1c-4fd3-8e34-082deeba81a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992311476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2992311476 |
| Directory | /workspace/19.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.1726880613 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 122938760931 ps |
| CPU time | 1948.42 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:52:23 PM PST 24 |
| Peak memory | 382796 kb |
| Host | smart-d7c4b311-0ac6-4bc7-8a86-34bfe7f031da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726880613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.1726880613 |
| Directory | /workspace/19.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1342546482 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1268713164 ps |
| CPU time | 121.25 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:21:55 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-9e8e7075-e232-42fe-bcb6-7ed5adae9f6d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342546482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.1342546482 |
| Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1692751843 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 51165064 ps |
| CPU time | 3.89 seconds |
| Started | Feb 21 01:19:40 PM PST 24 |
| Finished | Feb 21 01:19:45 PM PST 24 |
| Peak memory | 219036 kb |
| Host | smart-7ee1c103-b916-437c-a6e6-8c33fe3ce1bc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692751843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1692751843 |
| Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2303162729 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 20461952644 ps |
| CPU time | 739.65 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:31:19 PM PST 24 |
| Peak memory | 351032 kb |
| Host | smart-39f7cba7-b163-4d35-885e-4d099ee0881c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303162729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.2303162729 |
| Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.1172735527 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14716049 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 01:19:02 PM PST 24 |
| Finished | Feb 21 01:19:04 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-f5825562-fca7-449e-8c9e-9c3b8af7281f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172735527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1172735527 |
| Directory | /workspace/2.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_bijection.1087525487 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4471041965 ps |
| CPU time | 66.61 seconds |
| Started | Feb 21 01:18:42 PM PST 24 |
| Finished | Feb 21 01:19:49 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-ec8aed6c-550b-424a-96a9-fb79283a1599 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087525487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1087525487 |
| Directory | /workspace/2.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_executable.3427803719 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 10949319503 ps |
| CPU time | 773.3 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:31:54 PM PST 24 |
| Peak memory | 374768 kb |
| Host | smart-c8538bba-b25e-47a8-8be7-a54ecff2a7c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427803719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.3427803719 |
| Directory | /workspace/2.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.21672024 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 465127492 ps |
| CPU time | 4.09 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:19:08 PM PST 24 |
| Peak memory | 210928 kb |
| Host | smart-fad8d505-c1f7-4eef-8d33-fa700b209eee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21672024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escal ation.21672024 |
| Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.3490380370 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 367418489 ps |
| CPU time | 6.59 seconds |
| Started | Feb 21 01:18:56 PM PST 24 |
| Finished | Feb 21 01:19:03 PM PST 24 |
| Peak memory | 235348 kb |
| Host | smart-88fdf575-0667-4146-b4d7-6db68240253d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490380370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.3490380370 |
| Directory | /workspace/2.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2171248279 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1004014236 ps |
| CPU time | 3.03 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:19:07 PM PST 24 |
| Peak memory | 210828 kb |
| Host | smart-b57329c7-624c-4271-a0fc-6366af65bbb2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171248279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.2171248279 |
| Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.2672953193 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 274479290 ps |
| CPU time | 8.21 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:09 PM PST 24 |
| Peak memory | 202852 kb |
| Host | smart-fbe318c2-8c13-40cf-99f2-0eb141072aa1 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672953193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.2672953193 |
| Directory | /workspace/2.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.3815652133 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 18984478421 ps |
| CPU time | 1382.69 seconds |
| Started | Feb 21 01:18:45 PM PST 24 |
| Finished | Feb 21 01:41:48 PM PST 24 |
| Peak memory | 372336 kb |
| Host | smart-cea3e57f-07c4-4cb3-9d64-a3a20ccac439 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815652133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.3815652133 |
| Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.1789732060 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 123482848 ps |
| CPU time | 2.23 seconds |
| Started | Feb 21 01:18:55 PM PST 24 |
| Finished | Feb 21 01:18:58 PM PST 24 |
| Peak memory | 203008 kb |
| Host | smart-1b2d099f-9944-4fe4-83d9-21b943be37b9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789732060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.1789732060 |
| Directory | /workspace/2.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1340464225 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 30800713070 ps |
| CPU time | 350.59 seconds |
| Started | Feb 21 01:18:32 PM PST 24 |
| Finished | Feb 21 01:24:23 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-b02273f8-2698-4b3c-ae7c-50e4b1490ab0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340464225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.1340464225 |
| Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.3111482309 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 28948935 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:19:04 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-930ebd3e-eca9-479f-afad-9be582aa3d09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111482309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3111482309 |
| Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_regwen.3449692594 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 13781379086 ps |
| CPU time | 1728.04 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:47:50 PM PST 24 |
| Peak memory | 373568 kb |
| Host | smart-bf4778a6-a7ad-4362-b86d-d7a098917527 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449692594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3449692594 |
| Directory | /workspace/2.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.1449544413 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 456989763 ps |
| CPU time | 2.17 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:02 PM PST 24 |
| Peak memory | 221068 kb |
| Host | smart-7c795b0c-737d-4702-82af-a6b559151569 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449544413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1449544413 |
| Directory | /workspace/2.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_smoke.66413449 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 60466723 ps |
| CPU time | 12.6 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:19:16 PM PST 24 |
| Peak memory | 249092 kb |
| Host | smart-9a1141e6-8c41-4fc6-b35e-8a9c8235a897 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66413449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.66413449 |
| Directory | /workspace/2.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.2187334681 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 65633830077 ps |
| CPU time | 2470.85 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 02:00:13 PM PST 24 |
| Peak memory | 382432 kb |
| Host | smart-31127aa0-7fcf-4a49-b026-bedf8a186b46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187334681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2187334681 |
| Directory | /workspace/2.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.4070635158 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 8497854143 ps |
| CPU time | 250.42 seconds |
| Started | Feb 21 01:18:45 PM PST 24 |
| Finished | Feb 21 01:22:57 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-ecf9019a-db56-49b8-bc58-f9b733ae96c2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070635158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.4070635158 |
| Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.689191962 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 322911771 ps |
| CPU time | 5.45 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:19:07 PM PST 24 |
| Peak memory | 220544 kb |
| Host | smart-1c6c5a3c-6b22-4eaa-9dfb-54476701a378 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689191962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.689191962 |
| Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1272850788 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 11903383406 ps |
| CPU time | 472.86 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:27:47 PM PST 24 |
| Peak memory | 372964 kb |
| Host | smart-f4af9e11-f610-4d50-b402-7dfab4d8786f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272850788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.1272850788 |
| Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.1885834599 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 24396016 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:19:55 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-ff69cd3e-a7cd-4805-9d70-5676f3f85a18 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885834599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1885834599 |
| Directory | /workspace/20.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_bijection.3870560876 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 402130385 ps |
| CPU time | 24.99 seconds |
| Started | Feb 21 01:19:52 PM PST 24 |
| Finished | Feb 21 01:20:17 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-fa9ae2bc-5e7f-4f1a-91cc-0bcf223bd45a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870560876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .3870560876 |
| Directory | /workspace/20.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_executable.2304942119 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1205033858 ps |
| CPU time | 625.23 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:30:27 PM PST 24 |
| Peak memory | 371388 kb |
| Host | smart-b421ddb1-c9c4-4c26-8474-b55f3d31e077 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304942119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.2304942119 |
| Directory | /workspace/20.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.3536872905 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1813184697 ps |
| CPU time | 125.11 seconds |
| Started | Feb 21 01:19:51 PM PST 24 |
| Finished | Feb 21 01:21:57 PM PST 24 |
| Peak memory | 367100 kb |
| Host | smart-a154edda-95c7-48e1-b649-ea246ce82adf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536872905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.3536872905 |
| Directory | /workspace/20.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3246310170 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 345354645 ps |
| CPU time | 5.25 seconds |
| Started | Feb 21 01:19:54 PM PST 24 |
| Finished | Feb 21 01:20:01 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-a8d72fa9-06ba-492b-b368-d514e140c122 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246310170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.3246310170 |
| Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.3010870673 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3570184853 ps |
| CPU time | 6.81 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:05 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-4dc79f40-f4cd-4cfe-935e-09b00d0849ad |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010870673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3010870673 |
| Directory | /workspace/20.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.3121375993 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2997484526 ps |
| CPU time | 177.84 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:22:52 PM PST 24 |
| Peak memory | 315916 kb |
| Host | smart-5b59cb28-1068-462f-8235-6963190bd8b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121375993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.3121375993 |
| Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.3552171832 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 691830679 ps |
| CPU time | 9.33 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:20:10 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-167a9dcc-1222-4533-9ae8-934a92980d5a |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552171832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.3552171832 |
| Directory | /workspace/20.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.282540710 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 66161481677 ps |
| CPU time | 442.51 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:27:24 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-4bb58a99-d2ad-4fa5-b0a9-1cc52136a8d6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282540710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.sram_ctrl_partial_access_b2b.282540710 |
| Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.1874137393 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 25878956 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:19:54 PM PST 24 |
| Finished | Feb 21 01:19:58 PM PST 24 |
| Peak memory | 202884 kb |
| Host | smart-e2c255e4-df7d-4cb5-baae-17b16eaca771 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874137393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1874137393 |
| Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_regwen.3093995258 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 223233597996 ps |
| CPU time | 1176.27 seconds |
| Started | Feb 21 01:19:52 PM PST 24 |
| Finished | Feb 21 01:39:29 PM PST 24 |
| Peak memory | 361260 kb |
| Host | smart-cbb3c49d-7962-4c4d-a3f0-b1f7379a9135 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093995258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3093995258 |
| Directory | /workspace/20.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_smoke.1104425070 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 227151089 ps |
| CPU time | 13.85 seconds |
| Started | Feb 21 01:20:03 PM PST 24 |
| Finished | Feb 21 01:20:17 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-32c48785-870f-49da-9b83-1dfd89dfbb1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104425070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1104425070 |
| Directory | /workspace/20.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.3861786989 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 39446806733 ps |
| CPU time | 416.61 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:26:55 PM PST 24 |
| Peak memory | 380156 kb |
| Host | smart-731068f5-2068-425e-92ff-81cc58ca325e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861786989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.3861786989 |
| Directory | /workspace/20.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1851051028 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4077076976 ps |
| CPU time | 187.28 seconds |
| Started | Feb 21 01:19:51 PM PST 24 |
| Finished | Feb 21 01:22:59 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-b585a046-d632-4e96-a616-0b47bf5f357d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851051028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1851051028 |
| Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.283263668 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1082486193 ps |
| CPU time | 77.97 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:21:20 PM PST 24 |
| Peak memory | 345808 kb |
| Host | smart-7f1e693d-b531-4015-ad34-01a3461599ed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283263668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.283263668 |
| Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2832311329 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 9839954916 ps |
| CPU time | 646.79 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:30:42 PM PST 24 |
| Peak memory | 373512 kb |
| Host | smart-de477b8d-a06e-4e76-a48d-cc53333bc209 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832311329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.2832311329 |
| Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.1644543732 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 39383565 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:19:58 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-d04e6171-9007-466b-8673-889c828220af |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644543732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1644543732 |
| Directory | /workspace/21.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_bijection.3951675987 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1549613628 ps |
| CPU time | 49.93 seconds |
| Started | Feb 21 01:19:51 PM PST 24 |
| Finished | Feb 21 01:20:41 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-7160659a-eed0-4320-b21c-ca7f5e51d2d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951675987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3951675987 |
| Directory | /workspace/21.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_executable.2639857248 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 35773629522 ps |
| CPU time | 1016.84 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:36:59 PM PST 24 |
| Peak memory | 373548 kb |
| Host | smart-90cc3950-84af-4589-ada3-4ad1632c5b8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639857248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.2639857248 |
| Directory | /workspace/21.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.150174659 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1602222285 ps |
| CPU time | 24.9 seconds |
| Started | Feb 21 01:19:53 PM PST 24 |
| Finished | Feb 21 01:20:20 PM PST 24 |
| Peak memory | 210876 kb |
| Host | smart-09d9caa0-7374-496a-aeeb-e7971b8acfa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150174659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc alation.150174659 |
| Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.1029089539 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 133641607 ps |
| CPU time | 108.47 seconds |
| Started | Feb 21 01:19:52 PM PST 24 |
| Finished | Feb 21 01:21:40 PM PST 24 |
| Peak memory | 356008 kb |
| Host | smart-6fb9c678-c450-4d50-b262-7f0c63cf9083 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029089539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.1029089539 |
| Directory | /workspace/21.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.631550092 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 62848214 ps |
| CPU time | 4.94 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:20:07 PM PST 24 |
| Peak memory | 210844 kb |
| Host | smart-e7d04a78-9ddf-4de6-9e25-0d0fe9468c75 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631550092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_mem_partial_access.631550092 |
| Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.1885414859 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 284913130 ps |
| CPU time | 4.41 seconds |
| Started | Feb 21 01:20:01 PM PST 24 |
| Finished | Feb 21 01:20:07 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-c7721f95-62ec-4b9f-98ea-04418cbb58cc |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885414859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.1885414859 |
| Directory | /workspace/21.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.2922071850 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 9321289621 ps |
| CPU time | 438.21 seconds |
| Started | Feb 21 01:20:09 PM PST 24 |
| Finished | Feb 21 01:27:28 PM PST 24 |
| Peak memory | 325704 kb |
| Host | smart-82abc759-1eff-46c3-be0f-fda40000e51d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922071850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2922071850 |
| Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.2816731066 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 170823298 ps |
| CPU time | 4.72 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:20:01 PM PST 24 |
| Peak memory | 217108 kb |
| Host | smart-e20fc58b-b580-483c-b837-546769c5a4e2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816731066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.2816731066 |
| Directory | /workspace/21.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1811053347 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4932500941 ps |
| CPU time | 365.19 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:26:02 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-02252fef-33f3-4b85-8f5e-59de4bb76bd2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811053347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.1811053347 |
| Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.868840691 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 29425653 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:19:59 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-4d1c71c3-d77a-4c35-bd00-fdeaf15871be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868840691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.868840691 |
| Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_regwen.3042910588 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1361786570 ps |
| CPU time | 639.96 seconds |
| Started | Feb 21 01:19:52 PM PST 24 |
| Finished | Feb 21 01:30:32 PM PST 24 |
| Peak memory | 373680 kb |
| Host | smart-f0d510fb-a7a3-40ba-9f2b-69673325db87 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042910588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3042910588 |
| Directory | /workspace/21.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_smoke.624714789 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 467189642 ps |
| CPU time | 48.84 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:20:51 PM PST 24 |
| Peak memory | 310760 kb |
| Host | smart-1094f8e1-1634-4c7c-ba59-5670d3243812 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624714789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.624714789 |
| Directory | /workspace/21.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.2639974867 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 62056083665 ps |
| CPU time | 603.74 seconds |
| Started | Feb 21 01:20:01 PM PST 24 |
| Finished | Feb 21 01:30:06 PM PST 24 |
| Peak memory | 379048 kb |
| Host | smart-52a624e9-d5d3-4524-9704-305e526fbee4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639974867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.2639974867 |
| Directory | /workspace/21.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2283127041 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 6724973788 ps |
| CPU time | 161.7 seconds |
| Started | Feb 21 01:20:00 PM PST 24 |
| Finished | Feb 21 01:22:44 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-ae3cc3dd-857d-405d-8ced-d7a655ffe0d3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283127041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.2283127041 |
| Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3610341871 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 142290114 ps |
| CPU time | 96.72 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:21:35 PM PST 24 |
| Peak memory | 338604 kb |
| Host | smart-76690e08-a585-450a-8fab-20a2e3525616 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610341871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3610341871 |
| Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.4069911225 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 9635933881 ps |
| CPU time | 562.22 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:29:21 PM PST 24 |
| Peak memory | 362584 kb |
| Host | smart-78e38bbc-3607-4443-a44a-47d3382ab2fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069911225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.4069911225 |
| Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.764494708 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 19143011 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:19:59 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-39ddc172-70bb-4277-a19c-d11b38961c27 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764494708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.764494708 |
| Directory | /workspace/22.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_bijection.1420259503 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3838278924 ps |
| CPU time | 60.26 seconds |
| Started | Feb 21 01:19:54 PM PST 24 |
| Finished | Feb 21 01:20:57 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-e9f81122-9179-4c31-abce-598fffb3081b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420259503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .1420259503 |
| Directory | /workspace/22.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_executable.3668482430 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 27589482911 ps |
| CPU time | 699.84 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:31:40 PM PST 24 |
| Peak memory | 365300 kb |
| Host | smart-4bf245b9-265e-4c0c-b952-e5a443dc5574 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668482430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.3668482430 |
| Directory | /workspace/22.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.937906989 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 734400821 ps |
| CPU time | 4.5 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:20:05 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-7d2f521a-7c80-4f88-a1db-3cbc9acc88c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937906989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc alation.937906989 |
| Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.2487062880 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 118220218 ps |
| CPU time | 70.89 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:21:07 PM PST 24 |
| Peak memory | 328140 kb |
| Host | smart-abbbf6d5-3b6f-491c-ac68-399d03392aa7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487062880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2487062880 |
| Directory | /workspace/22.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1033757236 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 99101380 ps |
| CPU time | 2.95 seconds |
| Started | Feb 21 01:20:15 PM PST 24 |
| Finished | Feb 21 01:20:18 PM PST 24 |
| Peak memory | 210836 kb |
| Host | smart-f5ae0795-5cd7-4634-9122-da15f41c5d29 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033757236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.1033757236 |
| Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.1537601168 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 236274853 ps |
| CPU time | 5.27 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:20:07 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-88675cb5-7233-430b-859e-f34941e45f66 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537601168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.1537601168 |
| Directory | /workspace/22.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.764084243 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 10444763750 ps |
| CPU time | 941.93 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:35:39 PM PST 24 |
| Peak memory | 371336 kb |
| Host | smart-00d8e2bf-045e-4659-8ec4-6d05cd51bc23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764084243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip le_keys.764084243 |
| Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.3423895754 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 430918747 ps |
| CPU time | 2.2 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:20:04 PM PST 24 |
| Peak memory | 203316 kb |
| Host | smart-8dbfccf1-1ac9-4c80-9098-db15d3e38306 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423895754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.3423895754 |
| Directory | /workspace/22.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2874149761 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 56642774670 ps |
| CPU time | 374.31 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:26:14 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-c5c4f8f7-aede-42b4-9769-4b7c4a379bba |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874149761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.2874149761 |
| Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.3543752751 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 29986238 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:20:01 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-3034fd1f-2643-4579-a082-334f2ad777cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543752751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3543752751 |
| Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_regwen.1638118837 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3185876183 ps |
| CPU time | 717.67 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:31:58 PM PST 24 |
| Peak memory | 373184 kb |
| Host | smart-e31ef0b8-9077-4ab7-84fe-08083c7c7ef0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638118837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1638118837 |
| Directory | /workspace/22.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_smoke.2221207287 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 120759742 ps |
| CPU time | 98.38 seconds |
| Started | Feb 21 01:19:56 PM PST 24 |
| Finished | Feb 21 01:21:38 PM PST 24 |
| Peak memory | 344536 kb |
| Host | smart-b3921f30-53b4-403d-96a1-145f2db8675b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221207287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2221207287 |
| Directory | /workspace/22.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.704615201 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 280390820475 ps |
| CPU time | 4787.96 seconds |
| Started | Feb 21 01:19:54 PM PST 24 |
| Finished | Feb 21 02:39:44 PM PST 24 |
| Peak memory | 382656 kb |
| Host | smart-62808728-1438-41ca-bfba-5c7f5f67afbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704615201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_stress_all.704615201 |
| Directory | /workspace/22.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3128622017 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4087700098 ps |
| CPU time | 285.23 seconds |
| Started | Feb 21 01:19:50 PM PST 24 |
| Finished | Feb 21 01:24:36 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-bc2672f9-aa11-42bb-b06b-0688363b3ffc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128622017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.3128622017 |
| Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.635149047 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 452529658 ps |
| CPU time | 34.2 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:20:31 PM PST 24 |
| Peak memory | 294764 kb |
| Host | smart-d6cc8dab-4af6-4ad5-abab-1d117e580f8d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635149047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.635149047 |
| Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2482473269 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1675180119 ps |
| CPU time | 433 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:27:14 PM PST 24 |
| Peak memory | 340376 kb |
| Host | smart-3795058d-babf-4e94-b988-85e4d6d23b0e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482473269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.2482473269 |
| Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.4229577395 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 38550610 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:20:04 PM PST 24 |
| Finished | Feb 21 01:20:05 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-85e5a8a7-0fd8-438d-90dd-5199d7ece80f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229577395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.4229577395 |
| Directory | /workspace/23.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_bijection.739257881 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2199328497 ps |
| CPU time | 48.44 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:20:48 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-d7b423fe-d3d9-495f-b891-7cb35bfb7934 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739257881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection. 739257881 |
| Directory | /workspace/23.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_executable.1600265038 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1708376434 ps |
| CPU time | 458.07 seconds |
| Started | Feb 21 01:19:57 PM PST 24 |
| Finished | Feb 21 01:27:39 PM PST 24 |
| Peak memory | 364548 kb |
| Host | smart-82b87e9c-c910-4c71-817b-dd01f463b539 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600265038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1600265038 |
| Directory | /workspace/23.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.2966876530 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 366119976 ps |
| CPU time | 50.59 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:20:52 PM PST 24 |
| Peak memory | 304496 kb |
| Host | smart-3705c636-4617-4b4c-a3e9-2dce4e179d52 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966876530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2966876530 |
| Directory | /workspace/23.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3174487819 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 44715384 ps |
| CPU time | 2.95 seconds |
| Started | Feb 21 01:20:00 PM PST 24 |
| Finished | Feb 21 01:20:05 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-5b585436-27b3-4159-bc0c-d14ea0932050 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174487819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.3174487819 |
| Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.3367484183 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 162207297 ps |
| CPU time | 8 seconds |
| Started | Feb 21 01:20:08 PM PST 24 |
| Finished | Feb 21 01:20:17 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-77ad029f-f6ad-49fe-a8c8-ec4fa6f6c2b0 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367484183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.3367484183 |
| Directory | /workspace/23.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.3660770244 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 9229784993 ps |
| CPU time | 1109.46 seconds |
| Started | Feb 21 01:19:59 PM PST 24 |
| Finished | Feb 21 01:38:31 PM PST 24 |
| Peak memory | 363256 kb |
| Host | smart-467c19e5-4509-4fae-b5c5-9f27a4f77902 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660770244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.3660770244 |
| Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.798244850 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 105519220 ps |
| CPU time | 1.94 seconds |
| Started | Feb 21 01:19:55 PM PST 24 |
| Finished | Feb 21 01:19:59 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-edd47fd2-9250-4a24-8c03-a625fcaf0346 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798244850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s ram_ctrl_partial_access.798244850 |
| Directory | /workspace/23.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1265402207 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5559353240 ps |
| CPU time | 192.33 seconds |
| Started | Feb 21 01:20:10 PM PST 24 |
| Finished | Feb 21 01:23:23 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-4ad9b95c-694b-43cd-a115-7535c9f9d7c5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265402207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.1265402207 |
| Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.198701190 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 84551507 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:20:09 PM PST 24 |
| Finished | Feb 21 01:20:11 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-faa89053-1cb5-4572-a343-5ba006a1b5e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198701190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.198701190 |
| Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_regwen.2518211482 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 60740591739 ps |
| CPU time | 1077.6 seconds |
| Started | Feb 21 01:20:09 PM PST 24 |
| Finished | Feb 21 01:38:07 PM PST 24 |
| Peak memory | 374672 kb |
| Host | smart-ca406ca5-9fc9-4aff-82f1-17fa82d852c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518211482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2518211482 |
| Directory | /workspace/23.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_smoke.3809337508 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 508265470 ps |
| CPU time | 75.77 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:21:18 PM PST 24 |
| Peak memory | 330656 kb |
| Host | smart-74a73f90-b86b-49db-8bc4-609881720028 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809337508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3809337508 |
| Directory | /workspace/23.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.1304108680 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 41195324013 ps |
| CPU time | 1085.18 seconds |
| Started | Feb 21 01:20:14 PM PST 24 |
| Finished | Feb 21 01:38:19 PM PST 24 |
| Peak memory | 367328 kb |
| Host | smart-61e20c73-465d-4f36-8411-ae9dc5813957 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304108680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.1304108680 |
| Directory | /workspace/23.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2081754259 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 3282721121 ps |
| CPU time | 160.48 seconds |
| Started | Feb 21 01:19:58 PM PST 24 |
| Finished | Feb 21 01:22:42 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-49d9a1e0-751a-4728-bdcf-bb844e192f7f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081754259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.2081754259 |
| Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2003485827 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 781944639 ps |
| CPU time | 43.4 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:21:02 PM PST 24 |
| Peak memory | 326384 kb |
| Host | smart-d72cf0c0-b6b8-43d4-b961-17aa6f9c02a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003485827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2003485827 |
| Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.227610228 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2260043392 ps |
| CPU time | 289.15 seconds |
| Started | Feb 21 01:20:17 PM PST 24 |
| Finished | Feb 21 01:25:06 PM PST 24 |
| Peak memory | 364012 kb |
| Host | smart-c9a431a3-5543-4cbb-b48f-c0b9099eda3d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227610228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 24.sram_ctrl_access_during_key_req.227610228 |
| Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.1901646190 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 47448006 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:20:23 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-5dc5cfc9-a4cc-4d3d-9f22-edbed4489ca8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901646190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.1901646190 |
| Directory | /workspace/24.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_bijection.3417812179 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 5235770061 ps |
| CPU time | 53.9 seconds |
| Started | Feb 21 01:20:09 PM PST 24 |
| Finished | Feb 21 01:21:04 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-46970234-0c29-4503-a7bc-d15b37d619f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417812179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .3417812179 |
| Directory | /workspace/24.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_executable.3085160033 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 9439580716 ps |
| CPU time | 1192.96 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:40:17 PM PST 24 |
| Peak memory | 373524 kb |
| Host | smart-cf36d79d-005b-4ee0-a99f-1015cd31c8ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085160033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3085160033 |
| Directory | /workspace/24.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.851933289 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 388944500 ps |
| CPU time | 8.94 seconds |
| Started | Feb 21 01:20:10 PM PST 24 |
| Finished | Feb 21 01:20:20 PM PST 24 |
| Peak memory | 210936 kb |
| Host | smart-db450eeb-6c1f-4e90-bc41-9739939f136a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851933289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc alation.851933289 |
| Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.2297281595 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 52180041 ps |
| CPU time | 3.08 seconds |
| Started | Feb 21 01:20:16 PM PST 24 |
| Finished | Feb 21 01:20:19 PM PST 24 |
| Peak memory | 214768 kb |
| Host | smart-9ccf5b9f-e8a1-4795-afff-764de11cd836 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297281595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.2297281595 |
| Directory | /workspace/24.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1335171865 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 195312857 ps |
| CPU time | 5.36 seconds |
| Started | Feb 21 01:20:13 PM PST 24 |
| Finished | Feb 21 01:20:19 PM PST 24 |
| Peak memory | 215916 kb |
| Host | smart-f8bbfcb4-3082-4ea0-a0da-930fceb4dc6a |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335171865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1335171865 |
| Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.216595309 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 153199934 ps |
| CPU time | 4.52 seconds |
| Started | Feb 21 01:20:11 PM PST 24 |
| Finished | Feb 21 01:20:16 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-9fed5e7f-41ec-49df-a8e4-70638afb4624 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216595309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _mem_walk.216595309 |
| Directory | /workspace/24.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.1962810398 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 8791336156 ps |
| CPU time | 1171.82 seconds |
| Started | Feb 21 01:20:12 PM PST 24 |
| Finished | Feb 21 01:39:44 PM PST 24 |
| Peak memory | 371532 kb |
| Host | smart-7966911c-2f5f-424b-8c83-d618096777db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962810398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.1962810398 |
| Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.1480971811 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 323480516 ps |
| CPU time | 25.36 seconds |
| Started | Feb 21 01:20:07 PM PST 24 |
| Finished | Feb 21 01:20:33 PM PST 24 |
| Peak memory | 281076 kb |
| Host | smart-ad92df52-7663-495b-8b48-0d9ba593007c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480971811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.1480971811 |
| Directory | /workspace/24.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3646152009 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 70426492976 ps |
| CPU time | 371.23 seconds |
| Started | Feb 21 01:20:13 PM PST 24 |
| Finished | Feb 21 01:26:25 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-4a8f1649-1f36-44e5-be7d-beaf4262d8d0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646152009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3646152009 |
| Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.678203212 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 28366827 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 01:20:10 PM PST 24 |
| Finished | Feb 21 01:20:11 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-24d3890d-ffcf-4470-875f-a6ac7f5e56df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678203212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.678203212 |
| Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_regwen.1386917173 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1699505268 ps |
| CPU time | 834.47 seconds |
| Started | Feb 21 01:20:12 PM PST 24 |
| Finished | Feb 21 01:34:06 PM PST 24 |
| Peak memory | 371540 kb |
| Host | smart-1ad59231-2950-460d-9f52-e0dcc16b1ea6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386917173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1386917173 |
| Directory | /workspace/24.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_smoke.3165332933 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 135974632 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 01:20:09 PM PST 24 |
| Finished | Feb 21 01:20:11 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-8fb412c4-660e-4f99-bbc6-0f87b2904ab8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165332933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3165332933 |
| Directory | /workspace/24.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.1305081869 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 109035117997 ps |
| CPU time | 3449.69 seconds |
| Started | Feb 21 01:20:11 PM PST 24 |
| Finished | Feb 21 02:17:42 PM PST 24 |
| Peak memory | 397364 kb |
| Host | smart-92c78d64-5c81-4226-b806-1c279beffa33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305081869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.1305081869 |
| Directory | /workspace/24.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2462199514 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 17093720310 ps |
| CPU time | 225.36 seconds |
| Started | Feb 21 01:20:10 PM PST 24 |
| Finished | Feb 21 01:23:56 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-db23d309-10be-4d20-b158-a90ee65f3e36 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462199514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.2462199514 |
| Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1872722035 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 89884087 ps |
| CPU time | 3.31 seconds |
| Started | Feb 21 01:20:13 PM PST 24 |
| Finished | Feb 21 01:20:17 PM PST 24 |
| Peak memory | 218068 kb |
| Host | smart-e932a9a5-6c6a-4350-b11e-5ffbd48ca113 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872722035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1872722035 |
| Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2620303567 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 9352113271 ps |
| CPU time | 992.01 seconds |
| Started | Feb 21 01:20:20 PM PST 24 |
| Finished | Feb 21 01:36:53 PM PST 24 |
| Peak memory | 373512 kb |
| Host | smart-971e0022-3dc9-4f55-8e80-13e7e0f11032 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620303567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2620303567 |
| Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.2158739996 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 67993437 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:20:20 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-a9e80ef1-601d-4255-a6bf-004e3c826a32 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158739996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2158739996 |
| Directory | /workspace/25.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_bijection.3995982140 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 7058349222 ps |
| CPU time | 76.06 seconds |
| Started | Feb 21 01:20:18 PM PST 24 |
| Finished | Feb 21 01:21:34 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-25d3d8cc-b62e-4bb8-9760-fefaefd6487f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995982140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .3995982140 |
| Directory | /workspace/25.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_executable.3414398135 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 22837536832 ps |
| CPU time | 1127.42 seconds |
| Started | Feb 21 01:20:20 PM PST 24 |
| Finished | Feb 21 01:39:08 PM PST 24 |
| Peak memory | 367380 kb |
| Host | smart-66b12055-0ecc-41dd-8c63-45a8140342a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414398135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.3414398135 |
| Directory | /workspace/25.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.378937379 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 532724584 ps |
| CPU time | 3.38 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:20:24 PM PST 24 |
| Peak memory | 210868 kb |
| Host | smart-55fb8d6a-07cb-4102-9275-0bff47311571 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378937379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc alation.378937379 |
| Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.71376674 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 582619779 ps |
| CPU time | 153.23 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:22:53 PM PST 24 |
| Peak memory | 364632 kb |
| Host | smart-ac44e921-6a08-48a3-a79a-0b4984b55bda |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71376674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 25.sram_ctrl_max_throughput.71376674 |
| Directory | /workspace/25.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2118755175 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 118435548 ps |
| CPU time | 4.92 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:20:28 PM PST 24 |
| Peak memory | 215912 kb |
| Host | smart-52a3ffc3-fbbe-41be-96be-0d4ee7fbc0a5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118755175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.2118755175 |
| Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.3577456448 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 669516876 ps |
| CPU time | 9.56 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:20:33 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-b83177cd-ddd3-4cae-b625-242c8df254cd |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577456448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.3577456448 |
| Directory | /workspace/25.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.2413806253 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1641835136 ps |
| CPU time | 26.34 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:20:50 PM PST 24 |
| Peak memory | 267000 kb |
| Host | smart-8bcafcc2-0777-49c5-9312-f82e903ed001 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413806253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.2413806253 |
| Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.88486943 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2324470280 ps |
| CPU time | 15.18 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:20:38 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-14ee9ff5-a1e6-4bc3-8875-8427102a9bd6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88486943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sr am_ctrl_partial_access.88486943 |
| Directory | /workspace/25.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1240631499 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2723290680 ps |
| CPU time | 193.51 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:23:36 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-d26faf9b-43c1-4842-9d11-3c25ba3a102f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240631499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.1240631499 |
| Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.54443313 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 88672317 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 01:20:26 PM PST 24 |
| Finished | Feb 21 01:20:27 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-59b3d6ba-f674-4339-b303-6a28360c16b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54443313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.54443313 |
| Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_regwen.2272040159 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 950171907 ps |
| CPU time | 33.84 seconds |
| Started | Feb 21 01:20:20 PM PST 24 |
| Finished | Feb 21 01:20:54 PM PST 24 |
| Peak memory | 259720 kb |
| Host | smart-c34c6eb4-dfb1-4f1a-8c7b-493bd7197324 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272040159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2272040159 |
| Directory | /workspace/25.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_smoke.667384682 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 413196678 ps |
| CPU time | 8.84 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:20:30 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-b2e288ac-84b7-42ba-a88d-c15b90521c07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667384682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.667384682 |
| Directory | /workspace/25.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.511620872 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 3667018024 ps |
| CPU time | 353.53 seconds |
| Started | Feb 21 01:20:10 PM PST 24 |
| Finished | Feb 21 01:26:04 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-5f40d9b2-4f3e-4bc3-b55d-fc74722160e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511620872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_stress_pipeline.511620872 |
| Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.960729982 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 127154990 ps |
| CPU time | 9.26 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:20:29 PM PST 24 |
| Peak memory | 242832 kb |
| Host | smart-8d123161-088d-4a5b-be23-00bccb3a461d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960729982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.960729982 |
| Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3158890846 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4092260432 ps |
| CPU time | 589.85 seconds |
| Started | Feb 21 01:20:18 PM PST 24 |
| Finished | Feb 21 01:30:08 PM PST 24 |
| Peak memory | 369388 kb |
| Host | smart-3921e0f1-227d-4838-b744-e42548123d12 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158890846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.3158890846 |
| Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.2070311974 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 39136320 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 01:20:24 PM PST 24 |
| Finished | Feb 21 01:20:25 PM PST 24 |
| Peak memory | 201728 kb |
| Host | smart-17ee7b3a-977e-45d9-9f59-335daf80a591 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070311974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2070311974 |
| Directory | /workspace/26.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_bijection.596599833 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1196404505 ps |
| CPU time | 56.5 seconds |
| Started | Feb 21 01:20:18 PM PST 24 |
| Finished | Feb 21 01:21:15 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-43f63c71-168b-4d41-a02e-f019940c71b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596599833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 596599833 |
| Directory | /workspace/26.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_executable.976760974 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 52389316888 ps |
| CPU time | 855.84 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:34:38 PM PST 24 |
| Peak memory | 371608 kb |
| Host | smart-d24d36d2-c2ed-404a-8dd0-b882160dd86e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976760974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.976760974 |
| Directory | /workspace/26.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.2738554497 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1862806576 ps |
| CPU time | 11.81 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:20:34 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-37617d5c-9c1e-478e-98d2-2e2b35cf8aea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738554497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.2738554497 |
| Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.3045736104 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 148766167 ps |
| CPU time | 1.91 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:20:21 PM PST 24 |
| Peak memory | 210896 kb |
| Host | smart-f6e7b676-016b-4b19-ad6d-38ac868daf80 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045736104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.3045736104 |
| Directory | /workspace/26.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2706490656 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 320467143 ps |
| CPU time | 3.06 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:20:23 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-5b42c783-1d2a-473b-b972-9026d5985a1e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706490656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.2706490656 |
| Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.1136445837 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 240747631 ps |
| CPU time | 5.05 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:20:28 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-b6428ddc-a82a-43f1-b916-8b4943d6aa33 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136445837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.1136445837 |
| Directory | /workspace/26.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.436426112 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2044237051 ps |
| CPU time | 489.46 seconds |
| Started | Feb 21 01:20:20 PM PST 24 |
| Finished | Feb 21 01:28:30 PM PST 24 |
| Peak memory | 352992 kb |
| Host | smart-419a835b-a285-4f89-963f-14651deebefc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436426112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip le_keys.436426112 |
| Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.1943248857 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 824967004 ps |
| CPU time | 12.66 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:20:34 PM PST 24 |
| Peak memory | 248652 kb |
| Host | smart-e3893d6e-738a-4bcb-899d-7bc136d30cd8 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943248857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.1943248857 |
| Directory | /workspace/26.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.1433914117 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 30019063 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:20:20 PM PST 24 |
| Finished | Feb 21 01:20:21 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-78551d53-7c99-457d-a2cf-39df61f5b2e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433914117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1433914117 |
| Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_regwen.3929757235 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 13269363575 ps |
| CPU time | 195.87 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:23:35 PM PST 24 |
| Peak memory | 332912 kb |
| Host | smart-d090ab74-8f3a-40d9-9e05-b78b7f2d5038 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929757235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3929757235 |
| Directory | /workspace/26.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_smoke.45880168 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 584384492 ps |
| CPU time | 122.02 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:22:25 PM PST 24 |
| Peak memory | 373288 kb |
| Host | smart-8b2e3152-b438-4034-8d8a-10cc8fd1b3e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45880168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.45880168 |
| Directory | /workspace/26.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.2362655105 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 95063079070 ps |
| CPU time | 3030.94 seconds |
| Started | Feb 21 01:20:18 PM PST 24 |
| Finished | Feb 21 02:10:49 PM PST 24 |
| Peak memory | 374692 kb |
| Host | smart-08b53328-c6e9-412d-badb-f624b5d9d3f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362655105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.2362655105 |
| Directory | /workspace/26.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1928728763 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 4910020885 ps |
| CPU time | 358.77 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:26:21 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-3d5a8802-3853-483a-b48a-7f9ef4cf0402 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928728763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.1928728763 |
| Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3308168103 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 157576159 ps |
| CPU time | 1.75 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:20:23 PM PST 24 |
| Peak memory | 210924 kb |
| Host | smart-8c16f67d-f990-49e5-b1f5-422e2f4bb42d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308168103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3308168103 |
| Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1423636902 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 12031223737 ps |
| CPU time | 894.42 seconds |
| Started | Feb 21 01:20:18 PM PST 24 |
| Finished | Feb 21 01:35:13 PM PST 24 |
| Peak memory | 372224 kb |
| Host | smart-dcfb2f5a-e726-4ba2-9180-ec943c51998c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423636902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1423636902 |
| Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.116304812 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 12751498 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:20:44 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-5c670013-a70b-4031-b257-7a49378930cb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116304812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.116304812 |
| Directory | /workspace/27.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_bijection.865258850 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2467830158 ps |
| CPU time | 37.3 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:20:57 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-e3e99155-f9b1-45e6-ae87-f2b94061cb45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865258850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection. 865258850 |
| Directory | /workspace/27.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_executable.3128193394 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 8644119189 ps |
| CPU time | 426.71 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:27:28 PM PST 24 |
| Peak memory | 361112 kb |
| Host | smart-99e0ff4e-e2ab-47b2-8b47-3ec6a714284c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128193394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.3128193394 |
| Directory | /workspace/27.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.132548215 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 654125519 ps |
| CPU time | 18.83 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:20:43 PM PST 24 |
| Peak memory | 210896 kb |
| Host | smart-8db335c9-501b-4387-8eb9-be6669f62efc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132548215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esc alation.132548215 |
| Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.2996055049 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 911048191 ps |
| CPU time | 32.56 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:20:52 PM PST 24 |
| Peak memory | 284400 kb |
| Host | smart-868560ec-b195-4c65-bd03-b5b4b4fd182b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996055049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.2996055049 |
| Directory | /workspace/27.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.533312744 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 345734010 ps |
| CPU time | 3.13 seconds |
| Started | Feb 21 01:20:32 PM PST 24 |
| Finished | Feb 21 01:20:35 PM PST 24 |
| Peak memory | 210808 kb |
| Host | smart-926a3795-7f39-4c2b-81eb-ba6db76fb6b6 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533312744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_mem_partial_access.533312744 |
| Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.620433254 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1376165690 ps |
| CPU time | 5.04 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:20:48 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-a840af5e-53ea-4979-87de-85f7f72c62cf |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620433254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl _mem_walk.620433254 |
| Directory | /workspace/27.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.2642535661 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 15001303007 ps |
| CPU time | 971 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:36:33 PM PST 24 |
| Peak memory | 373508 kb |
| Host | smart-60e0a04c-84a8-4eba-a008-dee868704cbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642535661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.2642535661 |
| Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.906698036 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 628860289 ps |
| CPU time | 43.09 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:21:03 PM PST 24 |
| Peak memory | 298432 kb |
| Host | smart-1b40b796-1c43-47a7-8937-36e5e171f110 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906698036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s ram_ctrl_partial_access.906698036 |
| Directory | /workspace/27.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2432129549 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4605497176 ps |
| CPU time | 305.12 seconds |
| Started | Feb 21 01:20:19 PM PST 24 |
| Finished | Feb 21 01:25:24 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-eb9d4ae8-982c-435f-8359-18470871e753 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432129549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.2432129549 |
| Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.420300432 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 87110819 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:20:45 PM PST 24 |
| Peak memory | 202824 kb |
| Host | smart-33f2c93e-835d-41e2-b2b2-b78e439d0db1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420300432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.420300432 |
| Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_regwen.3397065123 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 18093483752 ps |
| CPU time | 848.05 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 01:34:52 PM PST 24 |
| Peak memory | 374584 kb |
| Host | smart-42c8885c-8de3-4b7a-9a16-c59e5c625cfd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397065123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3397065123 |
| Directory | /workspace/27.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_smoke.1793427843 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 46384660 ps |
| CPU time | 2.63 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:20:26 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-d7f5d9ba-a1e1-48e0-b9e0-3accb7c9d815 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793427843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1793427843 |
| Directory | /workspace/27.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.1016148872 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 89944465770 ps |
| CPU time | 3364.22 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 02:16:48 PM PST 24 |
| Peak memory | 382656 kb |
| Host | smart-a4eb834e-294d-4da8-9f12-b2b8790400b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016148872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.1016148872 |
| Directory | /workspace/27.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2313687817 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1211320371 ps |
| CPU time | 115.13 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:22:17 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-e551e899-0e5d-4304-a289-04baba4e3dca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313687817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.2313687817 |
| Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3047796226 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 140914661 ps |
| CPU time | 60.53 seconds |
| Started | Feb 21 01:20:22 PM PST 24 |
| Finished | Feb 21 01:21:23 PM PST 24 |
| Peak memory | 327368 kb |
| Host | smart-0fe7e89e-ea05-4e62-8705-a75a572a7f0f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047796226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3047796226 |
| Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3617819247 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3457480139 ps |
| CPU time | 755.07 seconds |
| Started | Feb 21 01:20:35 PM PST 24 |
| Finished | Feb 21 01:33:11 PM PST 24 |
| Peak memory | 370596 kb |
| Host | smart-521c44db-34ba-4b63-8e30-5933450cf659 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617819247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.3617819247 |
| Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.2220344126 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13770215 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:20:29 PM PST 24 |
| Finished | Feb 21 01:20:31 PM PST 24 |
| Peak memory | 201752 kb |
| Host | smart-92b2751b-0dd5-4d00-a3dd-c828ff8418ec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220344126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2220344126 |
| Directory | /workspace/28.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_bijection.558811005 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 8460667748 ps |
| CPU time | 44.37 seconds |
| Started | Feb 21 01:20:32 PM PST 24 |
| Finished | Feb 21 01:21:16 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-a0d6609a-905b-432e-aeb2-4dacba210ff0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558811005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection. 558811005 |
| Directory | /workspace/28.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_executable.2413971473 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 11524387926 ps |
| CPU time | 767.4 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:33:31 PM PST 24 |
| Peak memory | 370980 kb |
| Host | smart-d25a3870-6dab-4876-848e-1325fb1e338f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413971473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.2413971473 |
| Directory | /workspace/28.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.2602344394 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 190268096 ps |
| CPU time | 2.94 seconds |
| Started | Feb 21 01:20:30 PM PST 24 |
| Finished | Feb 21 01:20:33 PM PST 24 |
| Peak memory | 213084 kb |
| Host | smart-d333a5c0-2ac1-4a25-a08b-8427a0ce0b03 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602344394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.2602344394 |
| Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.1127463105 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 518707522 ps |
| CPU time | 141.91 seconds |
| Started | Feb 21 01:20:31 PM PST 24 |
| Finished | Feb 21 01:22:54 PM PST 24 |
| Peak memory | 364724 kb |
| Host | smart-633fb8a6-dd83-4b72-98e6-05ad3980ab0b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127463105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.1127463105 |
| Directory | /workspace/28.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4197140899 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 304478172 ps |
| CPU time | 2.97 seconds |
| Started | Feb 21 01:20:28 PM PST 24 |
| Finished | Feb 21 01:20:31 PM PST 24 |
| Peak memory | 215576 kb |
| Host | smart-5b4b7957-af36-40c8-bc93-04d08daff88f |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197140899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.4197140899 |
| Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.1701224226 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 140637041 ps |
| CPU time | 8.35 seconds |
| Started | Feb 21 01:20:36 PM PST 24 |
| Finished | Feb 21 01:20:44 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-e9b19aab-3482-4485-bbfe-2e3864480ef6 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701224226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.1701224226 |
| Directory | /workspace/28.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.2355854168 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5048779181 ps |
| CPU time | 438.73 seconds |
| Started | Feb 21 01:20:30 PM PST 24 |
| Finished | Feb 21 01:27:49 PM PST 24 |
| Peak memory | 369436 kb |
| Host | smart-9aff28dc-13e0-4949-a1e5-41afd53667e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355854168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.2355854168 |
| Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.2850569631 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 486434723 ps |
| CPU time | 5.64 seconds |
| Started | Feb 21 01:20:27 PM PST 24 |
| Finished | Feb 21 01:20:34 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-9c5f8df7-4d70-4320-9349-709e271247f0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850569631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.2850569631 |
| Directory | /workspace/28.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3143852854 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 10538262034 ps |
| CPU time | 346.32 seconds |
| Started | Feb 21 01:20:21 PM PST 24 |
| Finished | Feb 21 01:26:08 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-23cd7006-d2b2-4252-aca1-36ad94253209 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143852854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.3143852854 |
| Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.232247686 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 42015327 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 01:20:29 PM PST 24 |
| Finished | Feb 21 01:20:30 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-cdd7af4b-11e8-42d6-8696-e9f0080966fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232247686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.232247686 |
| Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3304062566 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 9493713323 ps |
| CPU time | 514.23 seconds |
| Started | Feb 21 01:20:28 PM PST 24 |
| Finished | Feb 21 01:29:03 PM PST 24 |
| Peak memory | 318232 kb |
| Host | smart-dc5aba21-b089-4dfb-8fdd-e2c9a3975d3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304062566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3304062566 |
| Directory | /workspace/28.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_smoke.3895410719 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 198060643 ps |
| CPU time | 12.57 seconds |
| Started | Feb 21 01:20:36 PM PST 24 |
| Finished | Feb 21 01:20:49 PM PST 24 |
| Peak memory | 202904 kb |
| Host | smart-5bb29848-3f9a-4ecb-afe5-a50b353f7e1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895410719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3895410719 |
| Directory | /workspace/28.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.4162128239 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2449384002 ps |
| CPU time | 223.66 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:24:08 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-14abb800-5258-446d-849f-a52b93bbc278 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162128239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.4162128239 |
| Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.414743974 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 116492105 ps |
| CPU time | 1.5 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:20:45 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-67c7dbba-08da-4add-b5d4-610af8b234b5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414743974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.414743974 |
| Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1666586796 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 652657480 ps |
| CPU time | 64.29 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 01:21:48 PM PST 24 |
| Peak memory | 268944 kb |
| Host | smart-5b2e2ae7-49d5-482d-82fb-e2ae88be4b54 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666586796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.1666586796 |
| Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.3750588252 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 67245192 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:20:35 PM PST 24 |
| Finished | Feb 21 01:20:36 PM PST 24 |
| Peak memory | 201764 kb |
| Host | smart-f0c20387-13f3-4678-bd92-c93d86c78903 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750588252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.3750588252 |
| Directory | /workspace/29.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_bijection.670321857 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 972207265 ps |
| CPU time | 16.09 seconds |
| Started | Feb 21 01:20:26 PM PST 24 |
| Finished | Feb 21 01:20:43 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-80847131-ad7a-4965-bff3-b32b62257c7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670321857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection. 670321857 |
| Directory | /workspace/29.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_executable.1959213910 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7499657747 ps |
| CPU time | 933.44 seconds |
| Started | Feb 21 01:20:33 PM PST 24 |
| Finished | Feb 21 01:36:06 PM PST 24 |
| Peak memory | 372436 kb |
| Host | smart-10fe1c75-94c9-49eb-949a-c0f3722bfaa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959213910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.1959213910 |
| Directory | /workspace/29.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.579150439 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1656718792 ps |
| CPU time | 4.89 seconds |
| Started | Feb 21 01:20:28 PM PST 24 |
| Finished | Feb 21 01:20:33 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-912143a3-b7fb-4c96-abb2-454b121dfe27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579150439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc alation.579150439 |
| Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.1107169296 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 267711542 ps |
| CPU time | 17.61 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:21:00 PM PST 24 |
| Peak memory | 254272 kb |
| Host | smart-42d07c8e-bcc7-422c-9635-5b28e1e3fdcf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107169296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.1107169296 |
| Directory | /workspace/29.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.516694677 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 129464907 ps |
| CPU time | 4.75 seconds |
| Started | Feb 21 01:20:31 PM PST 24 |
| Finished | Feb 21 01:20:36 PM PST 24 |
| Peak memory | 210844 kb |
| Host | smart-a52af2f5-8cf6-45c0-9188-d5a64036a733 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516694677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29 .sram_ctrl_mem_partial_access.516694677 |
| Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.1486396163 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 140672083 ps |
| CPU time | 7.84 seconds |
| Started | Feb 21 01:20:29 PM PST 24 |
| Finished | Feb 21 01:20:37 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-72bcb5f5-52bc-41dd-9319-7a2fbca66477 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486396163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1486396163 |
| Directory | /workspace/29.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.1460491618 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 25589615037 ps |
| CPU time | 803.87 seconds |
| Started | Feb 21 01:20:29 PM PST 24 |
| Finished | Feb 21 01:33:54 PM PST 24 |
| Peak memory | 371516 kb |
| Host | smart-844f7f1c-c73a-466c-955d-2a74fb139fd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460491618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.1460491618 |
| Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.3390144286 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3575261167 ps |
| CPU time | 14.58 seconds |
| Started | Feb 21 01:20:28 PM PST 24 |
| Finished | Feb 21 01:20:43 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-12a0b38c-7697-4578-920e-88559315c7db |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390144286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.3390144286 |
| Directory | /workspace/29.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1782055314 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 48741157351 ps |
| CPU time | 405.21 seconds |
| Started | Feb 21 01:20:23 PM PST 24 |
| Finished | Feb 21 01:27:09 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-2bdb3128-e80c-4767-8fad-28ece41bb37c |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782055314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1782055314 |
| Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.2354800665 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 83767188 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:20:29 PM PST 24 |
| Finished | Feb 21 01:20:31 PM PST 24 |
| Peak memory | 202892 kb |
| Host | smart-275ca269-c8a8-49b9-adcc-0a746d523a8e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354800665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2354800665 |
| Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_regwen.3081488934 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 68153771177 ps |
| CPU time | 1274.75 seconds |
| Started | Feb 21 01:20:29 PM PST 24 |
| Finished | Feb 21 01:41:45 PM PST 24 |
| Peak memory | 374424 kb |
| Host | smart-e57275d6-8be3-4426-a65e-a5f818493189 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081488934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3081488934 |
| Directory | /workspace/29.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_smoke.1962830111 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3322914383 ps |
| CPU time | 14.56 seconds |
| Started | Feb 21 01:20:30 PM PST 24 |
| Finished | Feb 21 01:20:45 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-d56833cb-39ab-49c3-8f83-595eeae7c1b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962830111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1962830111 |
| Directory | /workspace/29.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.156668038 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 88274084447 ps |
| CPU time | 6798.22 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 03:14:02 PM PST 24 |
| Peak memory | 375560 kb |
| Host | smart-392947e6-9037-4990-8865-cbcc9d64eba6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156668038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_stress_all.156668038 |
| Directory | /workspace/29.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3595223549 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 6753013483 ps |
| CPU time | 317.13 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 01:26:01 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-5db7a7a2-79bb-4a84-af16-04cb7e176394 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595223549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3595223549 |
| Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1658688684 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 145962494 ps |
| CPU time | 9.6 seconds |
| Started | Feb 21 01:20:31 PM PST 24 |
| Finished | Feb 21 01:20:41 PM PST 24 |
| Peak memory | 240552 kb |
| Host | smart-d78bc13c-a892-4d3a-aa4e-cac1737b3b93 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658688684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1658688684 |
| Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1335448085 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1841935350 ps |
| CPU time | 116.48 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:21:01 PM PST 24 |
| Peak memory | 318012 kb |
| Host | smart-d185faa0-f312-4676-9b35-cc7b415da3c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335448085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1335448085 |
| Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.3177554181 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 12445074 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 01:18:44 PM PST 24 |
| Finished | Feb 21 01:18:45 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-82ab842d-4088-4b1e-8d4b-800c340aa546 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177554181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3177554181 |
| Directory | /workspace/3.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_bijection.1728300033 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 15151815260 ps |
| CPU time | 52.35 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:19:54 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-9b3b0961-95c8-40d1-b9ef-4115f278a1dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728300033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 1728300033 |
| Directory | /workspace/3.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_executable.453737397 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 19584000656 ps |
| CPU time | 32.65 seconds |
| Started | Feb 21 01:19:02 PM PST 24 |
| Finished | Feb 21 01:19:36 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-466db33b-60b7-413f-9467-a4dde387a403 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453737397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable .453737397 |
| Directory | /workspace/3.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.3508238404 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 489084963 ps |
| CPU time | 2.16 seconds |
| Started | Feb 21 01:19:04 PM PST 24 |
| Finished | Feb 21 01:19:06 PM PST 24 |
| Peak memory | 212080 kb |
| Host | smart-7ba0f079-4b39-47e7-8bb5-99694d3831e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508238404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.3508238404 |
| Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.3412309591 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 779313295 ps |
| CPU time | 36.16 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:19:34 PM PST 24 |
| Peak memory | 291156 kb |
| Host | smart-081a94aa-ed31-48e5-9ffd-191419c99eec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412309591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3412309591 |
| Directory | /workspace/3.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.870012666 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 776413690 ps |
| CPU time | 5.11 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:19:09 PM PST 24 |
| Peak memory | 210756 kb |
| Host | smart-4383e0d1-0464-4a8e-bbaf-5c00390c3a1d |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870012666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_mem_partial_access.870012666 |
| Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.3581482094 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 6238815085 ps |
| CPU time | 10.76 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:19:13 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-29187a50-376e-48ab-8641-578a6589c28b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581482094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.3581482094 |
| Directory | /workspace/3.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.2359159016 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 28407163320 ps |
| CPU time | 2527.27 seconds |
| Started | Feb 21 01:19:02 PM PST 24 |
| Finished | Feb 21 02:01:11 PM PST 24 |
| Peak memory | 375584 kb |
| Host | smart-16c681a9-1a99-4bd1-9f58-ef9cf0ed146a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359159016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2359159016 |
| Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.140506919 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 625603291 ps |
| CPU time | 17.02 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:19:16 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-aef23670-82a6-4a52-a77b-a683cacfc2ab |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140506919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.140506919 |
| Directory | /workspace/3.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2581539032 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 20947177575 ps |
| CPU time | 333.19 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:24:35 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-b2d90ad8-77ce-400a-848f-9871a0d994dc |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581539032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2581539032 |
| Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.2891353855 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 29701013 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:19:05 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-352331d5-f367-4605-9154-3a6ac347ee51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891353855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2891353855 |
| Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_regwen.1189009354 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3009793982 ps |
| CPU time | 1051.67 seconds |
| Started | Feb 21 01:19:12 PM PST 24 |
| Finished | Feb 21 01:36:44 PM PST 24 |
| Peak memory | 369348 kb |
| Host | smart-2a75fbce-43db-43d9-8905-49b90f24a6b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189009354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1189009354 |
| Directory | /workspace/3.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.1608289612 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 871617075 ps |
| CPU time | 3.25 seconds |
| Started | Feb 21 01:18:45 PM PST 24 |
| Finished | Feb 21 01:18:49 PM PST 24 |
| Peak memory | 221216 kb |
| Host | smart-e0cf64d6-9a25-401d-9368-c44616bf49f8 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608289612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.1608289612 |
| Directory | /workspace/3.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_smoke.3302860538 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 955306740 ps |
| CPU time | 15.2 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:19:19 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-151ec445-2970-4b78-813f-5cc495d2ebca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302860538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3302860538 |
| Directory | /workspace/3.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2064173379 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3451031630 ps |
| CPU time | 322.46 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:24:22 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-96ec417e-5b7b-48cd-994a-4f26a1f197a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064173379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.2064173379 |
| Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.317551372 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 126471556 ps |
| CPU time | 76.41 seconds |
| Started | Feb 21 01:19:10 PM PST 24 |
| Finished | Feb 21 01:20:26 PM PST 24 |
| Peak memory | 331344 kb |
| Host | smart-75b87e2c-08a6-4ead-92b3-85022094a9fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317551372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.317551372 |
| Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.351398756 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 7796631435 ps |
| CPU time | 618.26 seconds |
| Started | Feb 21 01:20:37 PM PST 24 |
| Finished | Feb 21 01:30:56 PM PST 24 |
| Peak memory | 369452 kb |
| Host | smart-3a78f078-060a-4805-991b-5a248a667e78 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351398756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.sram_ctrl_access_during_key_req.351398756 |
| Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.3156523987 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 22094036 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:20:34 PM PST 24 |
| Finished | Feb 21 01:20:35 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-5ede63aa-48eb-4a48-94e4-57f6f8dc2374 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156523987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3156523987 |
| Directory | /workspace/30.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_bijection.2922944638 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 918045895 ps |
| CPU time | 18.79 seconds |
| Started | Feb 21 01:20:34 PM PST 24 |
| Finished | Feb 21 01:20:53 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-edb65d7b-0ff1-48aa-ab13-7f8b2d441ae0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922944638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .2922944638 |
| Directory | /workspace/30.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_executable.2824282521 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 19322448983 ps |
| CPU time | 864.59 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:35:08 PM PST 24 |
| Peak memory | 373564 kb |
| Host | smart-f02fb53a-1435-4f9c-98fd-c9607fc03c99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824282521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.2824282521 |
| Directory | /workspace/30.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.4290998453 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2046284929 ps |
| CPU time | 6.07 seconds |
| Started | Feb 21 01:20:39 PM PST 24 |
| Finished | Feb 21 01:20:45 PM PST 24 |
| Peak memory | 210860 kb |
| Host | smart-a070ab35-ac1a-4aac-8d46-d4224b89b16f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290998453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.4290998453 |
| Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.26630562 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 286337552 ps |
| CPU time | 4.61 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 01:20:48 PM PST 24 |
| Peak memory | 220668 kb |
| Host | smart-55488cb1-0b76-4db1-950a-72d769ae3694 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 30.sram_ctrl_max_throughput.26630562 |
| Directory | /workspace/30.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2364776914 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 325084187 ps |
| CPU time | 5.06 seconds |
| Started | Feb 21 01:20:34 PM PST 24 |
| Finished | Feb 21 01:20:40 PM PST 24 |
| Peak memory | 210776 kb |
| Host | smart-c1945fd2-4235-4852-a189-7729bd09bdba |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364776914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.2364776914 |
| Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.421142722 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1240628391 ps |
| CPU time | 5.05 seconds |
| Started | Feb 21 01:20:32 PM PST 24 |
| Finished | Feb 21 01:20:38 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-33acbcd2-9f62-425c-b2a3-4af948601f83 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421142722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl _mem_walk.421142722 |
| Directory | /workspace/30.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1389780271 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 13543203432 ps |
| CPU time | 876.56 seconds |
| Started | Feb 21 01:20:36 PM PST 24 |
| Finished | Feb 21 01:35:13 PM PST 24 |
| Peak memory | 361620 kb |
| Host | smart-88aa4e85-c8fb-473e-b019-43dfb732348d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389780271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1389780271 |
| Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.815217916 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 117023440 ps |
| CPU time | 1.9 seconds |
| Started | Feb 21 01:20:44 PM PST 24 |
| Finished | Feb 21 01:20:46 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-2d985409-d812-4273-8004-04ea68e21abf |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815217916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.s ram_ctrl_partial_access.815217916 |
| Directory | /workspace/30.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2801094017 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 7765600287 ps |
| CPU time | 435.86 seconds |
| Started | Feb 21 01:20:33 PM PST 24 |
| Finished | Feb 21 01:27:50 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-f03104f3-4ccf-46f7-b06a-e5f340ebe0b6 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801094017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.2801094017 |
| Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.2473095146 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 45629529 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 01:20:38 PM PST 24 |
| Finished | Feb 21 01:20:39 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-16f552fc-0dd1-4cb4-bd07-712c0afc3b6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473095146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2473095146 |
| Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_regwen.2698936388 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 62155799048 ps |
| CPU time | 1596.88 seconds |
| Started | Feb 21 01:20:36 PM PST 24 |
| Finished | Feb 21 01:47:14 PM PST 24 |
| Peak memory | 374160 kb |
| Host | smart-9f7b5e96-1beb-4bf9-b0f3-660ade0deaa9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698936388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2698936388 |
| Directory | /workspace/30.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_smoke.3238478565 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 279049240 ps |
| CPU time | 23.22 seconds |
| Started | Feb 21 01:20:35 PM PST 24 |
| Finished | Feb 21 01:20:59 PM PST 24 |
| Peak memory | 272512 kb |
| Host | smart-87247049-ed2c-4dde-bc73-4db709bba565 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238478565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3238478565 |
| Directory | /workspace/30.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.2496358225 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 122450553202 ps |
| CPU time | 5428.27 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 02:51:13 PM PST 24 |
| Peak memory | 375464 kb |
| Host | smart-eba99303-2a47-4fcf-bef3-1ff15932ed6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496358225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.2496358225 |
| Directory | /workspace/30.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.275688120 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 6737911553 ps |
| CPU time | 161.12 seconds |
| Started | Feb 21 01:20:33 PM PST 24 |
| Finished | Feb 21 01:23:15 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-c0f88942-7d26-480f-a72a-12421f2fb689 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275688120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_stress_pipeline.275688120 |
| Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.4198141444 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 360211574 ps |
| CPU time | 25.16 seconds |
| Started | Feb 21 01:20:33 PM PST 24 |
| Finished | Feb 21 01:20:59 PM PST 24 |
| Peak memory | 274780 kb |
| Host | smart-5e258655-72b1-42f8-acc8-cf7b1e747699 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198141444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.4198141444 |
| Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.4068115789 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 1011321975 ps |
| CPU time | 520.68 seconds |
| Started | Feb 21 01:20:44 PM PST 24 |
| Finished | Feb 21 01:29:25 PM PST 24 |
| Peak memory | 369320 kb |
| Host | smart-c1ebd371-3b79-45d2-95f5-f7926b35697b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068115789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.4068115789 |
| Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.1043786275 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 31589863 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 01:20:54 PM PST 24 |
| Finished | Feb 21 01:20:55 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-6ab54644-d85a-4e54-bce0-d2069c8bcabc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043786275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.1043786275 |
| Directory | /workspace/31.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_bijection.714089624 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 500619230 ps |
| CPU time | 29.95 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 01:21:14 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-8a045f51-5335-4c18-b2d1-b6c721537c07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714089624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection. 714089624 |
| Directory | /workspace/31.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_executable.4290227991 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 12675012281 ps |
| CPU time | 1189.13 seconds |
| Started | Feb 21 01:20:43 PM PST 24 |
| Finished | Feb 21 01:40:33 PM PST 24 |
| Peak memory | 374476 kb |
| Host | smart-3e92b570-bc5e-423b-902b-a6774af32f3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290227991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.4290227991 |
| Directory | /workspace/31.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.2489463268 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 577813816 ps |
| CPU time | 14.99 seconds |
| Started | Feb 21 01:20:44 PM PST 24 |
| Finished | Feb 21 01:21:00 PM PST 24 |
| Peak memory | 210960 kb |
| Host | smart-d47117a2-fdae-42ec-9e45-c97bbc1475a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489463268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.2489463268 |
| Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.841605403 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 233248847 ps |
| CPU time | 89.9 seconds |
| Started | Feb 21 01:20:44 PM PST 24 |
| Finished | Feb 21 01:22:14 PM PST 24 |
| Peak memory | 339600 kb |
| Host | smart-ce16ba04-9698-4e91-9ca2-4e09e6f03ea8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841605403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.sram_ctrl_max_throughput.841605403 |
| Directory | /workspace/31.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.251721122 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 45487313 ps |
| CPU time | 3.11 seconds |
| Started | Feb 21 01:20:38 PM PST 24 |
| Finished | Feb 21 01:20:41 PM PST 24 |
| Peak memory | 212236 kb |
| Host | smart-daf0d21a-9dc6-4d37-a6fc-c5c58193b220 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251721122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_mem_partial_access.251721122 |
| Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.2400086678 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 146086964 ps |
| CPU time | 4.65 seconds |
| Started | Feb 21 01:20:38 PM PST 24 |
| Finished | Feb 21 01:20:44 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-d0ef75cc-3b44-4b5f-8de3-20ebbeaf4ddd |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400086678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.2400086678 |
| Directory | /workspace/31.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.601772247 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3749678241 ps |
| CPU time | 878.88 seconds |
| Started | Feb 21 01:20:38 PM PST 24 |
| Finished | Feb 21 01:35:17 PM PST 24 |
| Peak memory | 374528 kb |
| Host | smart-eeaf5916-5c2d-47b8-ae6f-e91b541d32a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601772247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip le_keys.601772247 |
| Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.2663129836 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 383104387 ps |
| CPU time | 41.08 seconds |
| Started | Feb 21 01:20:44 PM PST 24 |
| Finished | Feb 21 01:21:26 PM PST 24 |
| Peak memory | 292084 kb |
| Host | smart-283a2ec1-c94d-458f-abf0-52ceac5cd58d |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663129836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.2663129836 |
| Directory | /workspace/31.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2501317502 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 12603525151 ps |
| CPU time | 228.26 seconds |
| Started | Feb 21 01:20:34 PM PST 24 |
| Finished | Feb 21 01:24:23 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-e5dcf388-3254-429e-bae4-59c358992d82 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501317502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2501317502 |
| Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.1924151355 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 60745523 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:20:39 PM PST 24 |
| Finished | Feb 21 01:20:40 PM PST 24 |
| Peak memory | 202916 kb |
| Host | smart-84a1f15a-8879-4fe1-a859-3c82e09343b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924151355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1924151355 |
| Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1746596822 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 327407573 ps |
| CPU time | 14.91 seconds |
| Started | Feb 21 01:20:34 PM PST 24 |
| Finished | Feb 21 01:20:49 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-a8ee1796-36b2-4d9f-b76d-1dcaf7e3983b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746596822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1746596822 |
| Directory | /workspace/31.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.721388684 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 236656494480 ps |
| CPU time | 3527.61 seconds |
| Started | Feb 21 01:20:53 PM PST 24 |
| Finished | Feb 21 02:19:41 PM PST 24 |
| Peak memory | 382708 kb |
| Host | smart-7bd5585d-b5d9-4083-9e26-b65cba8dcf81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721388684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_stress_all.721388684 |
| Directory | /workspace/31.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.4017183418 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 9278860944 ps |
| CPU time | 222.96 seconds |
| Started | Feb 21 01:20:42 PM PST 24 |
| Finished | Feb 21 01:24:26 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-825dc28a-cd61-4d29-b16c-83df0b9eb5cc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017183418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.4017183418 |
| Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.369429811 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 110995251 ps |
| CPU time | 42.5 seconds |
| Started | Feb 21 01:20:37 PM PST 24 |
| Finished | Feb 21 01:21:20 PM PST 24 |
| Peak memory | 298584 kb |
| Host | smart-2c6c4bd3-4b2d-4789-9974-7fa17f0cf614 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369429811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.369429811 |
| Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2298684629 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 15911793962 ps |
| CPU time | 991.04 seconds |
| Started | Feb 21 01:20:53 PM PST 24 |
| Finished | Feb 21 01:37:25 PM PST 24 |
| Peak memory | 365320 kb |
| Host | smart-46bf034d-9a04-4fff-a128-80310a6e5b5a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298684629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.2298684629 |
| Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.326593802 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 17054796 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 01:20:52 PM PST 24 |
| Finished | Feb 21 01:20:54 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-8e0da316-9e1f-494b-8dd7-071cb7802b7f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326593802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.326593802 |
| Directory | /workspace/32.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_bijection.450529831 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6570728061 ps |
| CPU time | 50.52 seconds |
| Started | Feb 21 01:20:51 PM PST 24 |
| Finished | Feb 21 01:21:42 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-79e381cd-19e6-478f-8b88-093d0c1f3cf6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450529831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection. 450529831 |
| Directory | /workspace/32.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_executable.2230228965 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 7716233300 ps |
| CPU time | 1937.43 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:53:07 PM PST 24 |
| Peak memory | 374504 kb |
| Host | smart-5051897f-12d8-4e2e-9834-19398933eacc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230228965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.2230228965 |
| Directory | /workspace/32.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.4112752310 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 267600913 ps |
| CPU time | 138.94 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:23:08 PM PST 24 |
| Peak memory | 365680 kb |
| Host | smart-bab06c64-0fd1-4c85-9ecf-2f2b1c5b9552 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112752310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.4112752310 |
| Directory | /workspace/32.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1503625963 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 86302638 ps |
| CPU time | 2.91 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:20:53 PM PST 24 |
| Peak memory | 210832 kb |
| Host | smart-6869d57f-5712-4693-97d9-183c68465695 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503625963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.1503625963 |
| Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.1476878437 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 136649447 ps |
| CPU time | 8.31 seconds |
| Started | Feb 21 01:20:51 PM PST 24 |
| Finished | Feb 21 01:20:59 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-a12c1f75-15c2-4995-894a-0f0111edb844 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476878437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.1476878437 |
| Directory | /workspace/32.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.630123130 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 9646342411 ps |
| CPU time | 1294.83 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:42:24 PM PST 24 |
| Peak memory | 373568 kb |
| Host | smart-be51988b-a368-49bc-b881-d4f0c2ddc9c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630123130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip le_keys.630123130 |
| Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1451617868 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 349338858 ps |
| CPU time | 16.89 seconds |
| Started | Feb 21 01:20:54 PM PST 24 |
| Finished | Feb 21 01:21:12 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-fc22c11e-0d70-4279-8124-7002ccfa54c0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451617868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1451617868 |
| Directory | /workspace/32.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1315022700 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 49225293753 ps |
| CPU time | 325.2 seconds |
| Started | Feb 21 01:20:52 PM PST 24 |
| Finished | Feb 21 01:26:18 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-2efe4ab1-cc4c-4acc-a861-b19126f69f08 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315022700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.1315022700 |
| Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.1366491999 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 74295110 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 01:20:50 PM PST 24 |
| Finished | Feb 21 01:20:52 PM PST 24 |
| Peak memory | 202888 kb |
| Host | smart-a9345eef-f9d2-4b32-9cac-75375b4ae845 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366491999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1366491999 |
| Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_regwen.2266618917 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 22041489980 ps |
| CPU time | 634.29 seconds |
| Started | Feb 21 01:20:51 PM PST 24 |
| Finished | Feb 21 01:31:25 PM PST 24 |
| Peak memory | 358928 kb |
| Host | smart-90f6b8f7-4cc2-4b3a-a3a0-0d2e10aa9cec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266618917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2266618917 |
| Directory | /workspace/32.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_smoke.3289239222 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1643137175 ps |
| CPU time | 8.68 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:20:59 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-62901d45-3e10-499f-9cb4-9883b2efa169 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289239222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3289239222 |
| Directory | /workspace/32.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.186891807 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 64800354702 ps |
| CPU time | 766.53 seconds |
| Started | Feb 21 01:20:52 PM PST 24 |
| Finished | Feb 21 01:33:40 PM PST 24 |
| Peak memory | 357700 kb |
| Host | smart-4273fb1e-5375-4d8b-86d3-8d435d4ea7c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186891807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_stress_all.186891807 |
| Directory | /workspace/32.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.841297882 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 10333791303 ps |
| CPU time | 208.78 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:24:18 PM PST 24 |
| Peak memory | 202812 kb |
| Host | smart-23865d2c-72b6-469e-8828-b7a16a26e88e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841297882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_stress_pipeline.841297882 |
| Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3443742806 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 256682913 ps |
| CPU time | 76.18 seconds |
| Started | Feb 21 01:20:53 PM PST 24 |
| Finished | Feb 21 01:22:10 PM PST 24 |
| Peak memory | 337452 kb |
| Host | smart-60809807-3799-4430-8c29-928e00230789 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443742806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3443742806 |
| Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.432743737 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3890109992 ps |
| CPU time | 357.6 seconds |
| Started | Feb 21 01:20:47 PM PST 24 |
| Finished | Feb 21 01:26:46 PM PST 24 |
| Peak memory | 354528 kb |
| Host | smart-47d6a8e3-9153-4924-a882-0563dce65bad |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432743737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 33.sram_ctrl_access_during_key_req.432743737 |
| Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.3563399633 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 19791268 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:20:52 PM PST 24 |
| Finished | Feb 21 01:20:53 PM PST 24 |
| Peak memory | 201692 kb |
| Host | smart-6089bdc0-2ef2-4d4c-b5ee-36bb698ff2c5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563399633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3563399633 |
| Directory | /workspace/33.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_bijection.3840400269 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 15790939006 ps |
| CPU time | 69.1 seconds |
| Started | Feb 21 01:20:50 PM PST 24 |
| Finished | Feb 21 01:22:00 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-f561eebe-cc6d-4dfa-bf19-14d358fdb5d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840400269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .3840400269 |
| Directory | /workspace/33.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_executable.3444020954 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 991581420 ps |
| CPU time | 78.32 seconds |
| Started | Feb 21 01:20:52 PM PST 24 |
| Finished | Feb 21 01:22:11 PM PST 24 |
| Peak memory | 296716 kb |
| Host | smart-a9b3574a-a1f0-41e2-9ad0-c430c3baa390 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444020954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3444020954 |
| Directory | /workspace/33.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.2594646639 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 116406685 ps |
| CPU time | 1.87 seconds |
| Started | Feb 21 01:20:55 PM PST 24 |
| Finished | Feb 21 01:20:58 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-c830977d-8f99-49d3-b119-3210ef4df073 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594646639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.2594646639 |
| Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.2975017716 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 192257815 ps |
| CPU time | 5.36 seconds |
| Started | Feb 21 01:20:47 PM PST 24 |
| Finished | Feb 21 01:20:53 PM PST 24 |
| Peak memory | 235408 kb |
| Host | smart-ff9b9bf3-0a17-4802-b0f5-ca7c66c5ab26 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975017716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2975017716 |
| Directory | /workspace/33.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2227743063 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 44264833 ps |
| CPU time | 2.73 seconds |
| Started | Feb 21 01:20:51 PM PST 24 |
| Finished | Feb 21 01:20:55 PM PST 24 |
| Peak memory | 215524 kb |
| Host | smart-63dd0ac4-930c-4113-8cae-d7849edff0c2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227743063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2227743063 |
| Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.2787823636 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 141159162 ps |
| CPU time | 7.74 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:20:57 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-582152f9-6429-44a2-af7c-569e48e9bf2e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787823636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.2787823636 |
| Directory | /workspace/33.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.1120725969 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 13229991637 ps |
| CPU time | 1677.35 seconds |
| Started | Feb 21 01:20:50 PM PST 24 |
| Finished | Feb 21 01:48:48 PM PST 24 |
| Peak memory | 373556 kb |
| Host | smart-3093aad6-a05b-4d49-9b70-b267083b8b14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120725969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.1120725969 |
| Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.207980593 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 9892543095 ps |
| CPU time | 17.21 seconds |
| Started | Feb 21 01:20:57 PM PST 24 |
| Finished | Feb 21 01:21:14 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-91fce2f6-396a-4bf9-a91b-3f08adff80a3 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207980593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.207980593 |
| Directory | /workspace/33.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.521768245 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4484366288 ps |
| CPU time | 328.94 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:26:19 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-3431cfe5-715f-4228-9cc5-3a854fb99be5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521768245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.sram_ctrl_partial_access_b2b.521768245 |
| Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.1187590953 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 166526063 ps |
| CPU time | 0.88 seconds |
| Started | Feb 21 01:20:55 PM PST 24 |
| Finished | Feb 21 01:20:57 PM PST 24 |
| Peak memory | 202900 kb |
| Host | smart-78b369b7-b783-4b0c-afb5-7c270a808f02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187590953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1187590953 |
| Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_regwen.4112581961 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 15730855625 ps |
| CPU time | 1173.95 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:40:24 PM PST 24 |
| Peak memory | 366464 kb |
| Host | smart-37472683-68ba-4138-87c5-821eea5acdc4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112581961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.4112581961 |
| Directory | /workspace/33.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_smoke.695270401 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 724246260 ps |
| CPU time | 11.97 seconds |
| Started | Feb 21 01:20:51 PM PST 24 |
| Finished | Feb 21 01:21:03 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-26735049-f3d2-4de2-8e30-c56d039a29cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695270401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.695270401 |
| Directory | /workspace/33.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.800929272 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4542764328 ps |
| CPU time | 108.96 seconds |
| Started | Feb 21 01:20:52 PM PST 24 |
| Finished | Feb 21 01:22:41 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-be36abfc-a2cd-4180-8a0b-448cbc01090f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800929272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_stress_pipeline.800929272 |
| Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1832766416 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 163979455 ps |
| CPU time | 19.89 seconds |
| Started | Feb 21 01:20:50 PM PST 24 |
| Finished | Feb 21 01:21:10 PM PST 24 |
| Peak memory | 267800 kb |
| Host | smart-94992901-90fc-49ed-88f0-b5de002d1a10 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832766416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1832766416 |
| Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1837338868 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 22121296248 ps |
| CPU time | 918.8 seconds |
| Started | Feb 21 01:21:10 PM PST 24 |
| Finished | Feb 21 01:36:30 PM PST 24 |
| Peak memory | 368088 kb |
| Host | smart-2c5b2f0d-f07e-403e-a8df-610657048ddc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837338868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.1837338868 |
| Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.616689074 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 40671892 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:21:07 PM PST 24 |
| Finished | Feb 21 01:21:08 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-fdc246e3-0681-4d49-8b1c-b713cd0fe34d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616689074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.616689074 |
| Directory | /workspace/34.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_bijection.3147499609 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2419565035 ps |
| CPU time | 49.72 seconds |
| Started | Feb 21 01:21:09 PM PST 24 |
| Finished | Feb 21 01:21:59 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-5debc84c-6518-49f6-a62a-e3aeca52c0b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147499609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .3147499609 |
| Directory | /workspace/34.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_executable.4006046851 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 13168394687 ps |
| CPU time | 1487.2 seconds |
| Started | Feb 21 01:21:05 PM PST 24 |
| Finished | Feb 21 01:45:53 PM PST 24 |
| Peak memory | 371508 kb |
| Host | smart-5b58d72c-30ca-4604-972b-317c26153cdd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006046851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.4006046851 |
| Directory | /workspace/34.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.3883667656 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 586043728 ps |
| CPU time | 7.33 seconds |
| Started | Feb 21 01:21:08 PM PST 24 |
| Finished | Feb 21 01:21:16 PM PST 24 |
| Peak memory | 213212 kb |
| Host | smart-6e5a32bb-4dea-4ccc-9ff4-506db84b7348 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883667656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.3883667656 |
| Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.2340203935 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 142137125 ps |
| CPU time | 89.94 seconds |
| Started | Feb 21 01:21:05 PM PST 24 |
| Finished | Feb 21 01:22:36 PM PST 24 |
| Peak memory | 373220 kb |
| Host | smart-397599b8-e8bb-4fa2-90ad-245f1ebeacca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340203935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2340203935 |
| Directory | /workspace/34.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2481815194 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 118650452 ps |
| CPU time | 4.71 seconds |
| Started | Feb 21 01:21:17 PM PST 24 |
| Finished | Feb 21 01:21:22 PM PST 24 |
| Peak memory | 215724 kb |
| Host | smart-d00f5d50-1aef-4aad-a64a-19ae0def7603 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481815194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2481815194 |
| Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.2839457774 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 637011490 ps |
| CPU time | 9.07 seconds |
| Started | Feb 21 01:21:22 PM PST 24 |
| Finished | Feb 21 01:21:31 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-ab31b385-aa05-43b6-b7d5-b1ed183e7482 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839457774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2839457774 |
| Directory | /workspace/34.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1960321625 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 10222466987 ps |
| CPU time | 169.84 seconds |
| Started | Feb 21 01:21:05 PM PST 24 |
| Finished | Feb 21 01:23:55 PM PST 24 |
| Peak memory | 352384 kb |
| Host | smart-be240701-983d-4749-94d9-8193f4a91f2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960321625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1960321625 |
| Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.1228750556 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 161659120 ps |
| CPU time | 48.48 seconds |
| Started | Feb 21 01:21:11 PM PST 24 |
| Finished | Feb 21 01:22:00 PM PST 24 |
| Peak memory | 313716 kb |
| Host | smart-384e0a24-2302-4898-94dd-6bc75ad48cd9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228750556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.1228750556 |
| Directory | /workspace/34.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.487165797 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 20318373131 ps |
| CPU time | 517.36 seconds |
| Started | Feb 21 01:21:19 PM PST 24 |
| Finished | Feb 21 01:29:57 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-db307b79-7afd-4020-8b6e-3cb1ddc6ccbd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487165797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.sram_ctrl_partial_access_b2b.487165797 |
| Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.276759499 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 35106521 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 01:21:17 PM PST 24 |
| Finished | Feb 21 01:21:18 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-1457cdd3-081d-4403-a0a6-03dc5e29ffc7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276759499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.276759499 |
| Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_regwen.3815096100 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 24035582305 ps |
| CPU time | 274.36 seconds |
| Started | Feb 21 01:21:05 PM PST 24 |
| Finished | Feb 21 01:25:40 PM PST 24 |
| Peak memory | 373624 kb |
| Host | smart-50377f57-3401-45cd-bb60-cf22f3fbf0a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815096100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3815096100 |
| Directory | /workspace/34.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_smoke.3655487937 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 120520995 ps |
| CPU time | 3.05 seconds |
| Started | Feb 21 01:20:49 PM PST 24 |
| Finished | Feb 21 01:20:52 PM PST 24 |
| Peak memory | 202620 kb |
| Host | smart-38661340-e100-4629-aa36-06dedd536e32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655487937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3655487937 |
| Directory | /workspace/34.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.2104703481 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 42374407391 ps |
| CPU time | 3308.54 seconds |
| Started | Feb 21 01:21:07 PM PST 24 |
| Finished | Feb 21 02:16:16 PM PST 24 |
| Peak memory | 375548 kb |
| Host | smart-c2558f13-5194-429e-8817-c43cdf3c9808 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104703481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.2104703481 |
| Directory | /workspace/34.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.636034814 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 12770644652 ps |
| CPU time | 310.91 seconds |
| Started | Feb 21 01:21:15 PM PST 24 |
| Finished | Feb 21 01:26:27 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-4716913b-71b3-4f8c-b387-61f85c0e59dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636034814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .sram_ctrl_stress_pipeline.636034814 |
| Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2608108672 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 239214377 ps |
| CPU time | 11.13 seconds |
| Started | Feb 21 01:21:05 PM PST 24 |
| Finished | Feb 21 01:21:17 PM PST 24 |
| Peak memory | 251764 kb |
| Host | smart-38aadf55-a07a-4eb3-9ee4-490da667dd12 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608108672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2608108672 |
| Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2077856975 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 42182972666 ps |
| CPU time | 1209.56 seconds |
| Started | Feb 21 01:21:18 PM PST 24 |
| Finished | Feb 21 01:41:28 PM PST 24 |
| Peak memory | 369424 kb |
| Host | smart-46d353f3-aafe-434e-90bd-e5a5cc2462fa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077856975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.2077856975 |
| Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2215318609 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 43693151 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 01:21:07 PM PST 24 |
| Finished | Feb 21 01:21:08 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-cf80fcad-2683-4029-9be3-512330e85432 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215318609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2215318609 |
| Directory | /workspace/35.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_bijection.3776786247 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4397525007 ps |
| CPU time | 18.88 seconds |
| Started | Feb 21 01:21:12 PM PST 24 |
| Finished | Feb 21 01:21:31 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-5f15678e-c465-42e1-b986-5c38e9b6dbdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776786247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .3776786247 |
| Directory | /workspace/35.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_executable.3313073727 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 12147765856 ps |
| CPU time | 920.38 seconds |
| Started | Feb 21 01:21:09 PM PST 24 |
| Finished | Feb 21 01:36:30 PM PST 24 |
| Peak memory | 366332 kb |
| Host | smart-f634a2fe-82dd-4988-a02d-98acd278b381 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313073727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.3313073727 |
| Directory | /workspace/35.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.2931900945 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 1078570282 ps |
| CPU time | 10.16 seconds |
| Started | Feb 21 01:21:12 PM PST 24 |
| Finished | Feb 21 01:21:23 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-89343720-6f9e-4f4a-8f81-e3154930425e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931900945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.2931900945 |
| Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.2913007615 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 403952441 ps |
| CPU time | 64.42 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:22:28 PM PST 24 |
| Peak memory | 311500 kb |
| Host | smart-13d6ec0e-fada-42a2-a21e-fa171e2e13e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913007615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.2913007615 |
| Directory | /workspace/35.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3273931786 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 265193472 ps |
| CPU time | 3.34 seconds |
| Started | Feb 21 01:21:08 PM PST 24 |
| Finished | Feb 21 01:21:12 PM PST 24 |
| Peak memory | 210824 kb |
| Host | smart-257a352e-442d-45f4-ba24-36bc78126d45 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273931786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3273931786 |
| Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.243039885 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 74486912 ps |
| CPU time | 4.31 seconds |
| Started | Feb 21 01:21:10 PM PST 24 |
| Finished | Feb 21 01:21:15 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-8fd17f6b-b8c8-4d53-9176-d736d68e4dad |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243039885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _mem_walk.243039885 |
| Directory | /workspace/35.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.2601607101 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 8089260757 ps |
| CPU time | 1525.26 seconds |
| Started | Feb 21 01:21:09 PM PST 24 |
| Finished | Feb 21 01:46:35 PM PST 24 |
| Peak memory | 374552 kb |
| Host | smart-8eb66dac-4bb4-4c36-9b16-74d5634cf1fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601607101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.2601607101 |
| Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.125756751 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 6353541054 ps |
| CPU time | 6.15 seconds |
| Started | Feb 21 01:21:09 PM PST 24 |
| Finished | Feb 21 01:21:16 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-d415d2cd-4f6b-43b1-83ca-91d0db772bf9 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125756751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s ram_ctrl_partial_access.125756751 |
| Directory | /workspace/35.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2029281593 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 21892135394 ps |
| CPU time | 228.52 seconds |
| Started | Feb 21 01:21:07 PM PST 24 |
| Finished | Feb 21 01:24:56 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-040d78f3-6a0b-4592-a46c-66919fcad9fe |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029281593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.2029281593 |
| Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.1808136151 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 45234547 ps |
| CPU time | 0.87 seconds |
| Started | Feb 21 01:21:18 PM PST 24 |
| Finished | Feb 21 01:21:19 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-9272c639-d9d4-46e7-8b1f-783deea708ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808136151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1808136151 |
| Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_smoke.3142247169 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 117711394 ps |
| CPU time | 2.39 seconds |
| Started | Feb 21 01:21:08 PM PST 24 |
| Finished | Feb 21 01:21:10 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-b896d6aa-b961-43e9-991b-79ca076409da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142247169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3142247169 |
| Directory | /workspace/35.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.241900752 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 53645078568 ps |
| CPU time | 2489.23 seconds |
| Started | Feb 21 01:21:15 PM PST 24 |
| Finished | Feb 21 02:02:46 PM PST 24 |
| Peak memory | 382688 kb |
| Host | smart-edc60d86-aaf4-47c6-9c25-1e3ebc32bcbb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241900752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_stress_all.241900752 |
| Directory | /workspace/35.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1662112181 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 7260301912 ps |
| CPU time | 176.06 seconds |
| Started | Feb 21 01:21:08 PM PST 24 |
| Finished | Feb 21 01:24:04 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-235d563f-8d82-4dd3-ae06-bedbd7edbc69 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662112181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1662112181 |
| Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3090714923 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 151353441 ps |
| CPU time | 123.96 seconds |
| Started | Feb 21 01:21:15 PM PST 24 |
| Finished | Feb 21 01:23:20 PM PST 24 |
| Peak memory | 353980 kb |
| Host | smart-b0e141f2-0869-402a-a111-028c68b00dbb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090714923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3090714923 |
| Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2548097545 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 731159103 ps |
| CPU time | 57.63 seconds |
| Started | Feb 21 01:21:18 PM PST 24 |
| Finished | Feb 21 01:22:16 PM PST 24 |
| Peak memory | 307448 kb |
| Host | smart-b057abd4-813d-40ea-b837-057190721eee |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548097545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2548097545 |
| Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.1806552199 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 22161254 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 01:21:19 PM PST 24 |
| Finished | Feb 21 01:21:20 PM PST 24 |
| Peak memory | 201784 kb |
| Host | smart-118c7a64-5bf1-4d4f-b8d1-85aea8cb90ec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806552199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1806552199 |
| Directory | /workspace/36.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_bijection.2948856423 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 12236155843 ps |
| CPU time | 72.83 seconds |
| Started | Feb 21 01:21:08 PM PST 24 |
| Finished | Feb 21 01:22:21 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-d205d3d3-d694-4272-b6e4-050f2130ad41 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948856423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .2948856423 |
| Directory | /workspace/36.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_executable.2079876190 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 130310890579 ps |
| CPU time | 1900.5 seconds |
| Started | Feb 21 01:21:23 PM PST 24 |
| Finished | Feb 21 01:53:04 PM PST 24 |
| Peak memory | 365252 kb |
| Host | smart-d2821c89-2da6-4344-bdd3-4a66a32a6e73 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079876190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.2079876190 |
| Directory | /workspace/36.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.1325186660 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 40133318 ps |
| CPU time | 2.84 seconds |
| Started | Feb 21 01:21:21 PM PST 24 |
| Finished | Feb 21 01:21:25 PM PST 24 |
| Peak memory | 215316 kb |
| Host | smart-93e1dc5e-b23f-4901-ba37-8a4f7bda7b19 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325186660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.1325186660 |
| Directory | /workspace/36.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3051265326 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 124188511 ps |
| CPU time | 4.95 seconds |
| Started | Feb 21 01:21:22 PM PST 24 |
| Finished | Feb 21 01:21:28 PM PST 24 |
| Peak memory | 215684 kb |
| Host | smart-b3515e45-9446-4506-92d5-ff650782f148 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051265326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.3051265326 |
| Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.3071423225 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 447934336 ps |
| CPU time | 8.87 seconds |
| Started | Feb 21 01:21:36 PM PST 24 |
| Finished | Feb 21 01:21:45 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-1c1c647d-25f9-4282-9994-bd8dd59f75c7 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071423225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3071423225 |
| Directory | /workspace/36.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.2672556606 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 25634486387 ps |
| CPU time | 562.97 seconds |
| Started | Feb 21 01:21:08 PM PST 24 |
| Finished | Feb 21 01:30:31 PM PST 24 |
| Peak memory | 367392 kb |
| Host | smart-70686e85-492d-446a-b39c-4d455354c2f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672556606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.2672556606 |
| Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.4042216678 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 19089577170 ps |
| CPU time | 23 seconds |
| Started | Feb 21 01:21:09 PM PST 24 |
| Finished | Feb 21 01:21:33 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-c1a26f89-0e9b-4078-a9a8-3e74c6468e37 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042216678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.4042216678 |
| Directory | /workspace/36.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3427333338 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 25908588220 ps |
| CPU time | 321.94 seconds |
| Started | Feb 21 01:21:05 PM PST 24 |
| Finished | Feb 21 01:26:28 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-3ac340e2-cd9c-46ef-9bbb-3fa0e91dfd33 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427333338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.3427333338 |
| Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.418224402 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 87622626 ps |
| CPU time | 1.15 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:21:28 PM PST 24 |
| Peak memory | 202896 kb |
| Host | smart-a590a05b-fd4a-4d70-ad6d-08283b593d9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418224402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.418224402 |
| Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_regwen.2524372112 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 35551915925 ps |
| CPU time | 869.78 seconds |
| Started | Feb 21 01:21:23 PM PST 24 |
| Finished | Feb 21 01:35:53 PM PST 24 |
| Peak memory | 372224 kb |
| Host | smart-ad3b9b8e-612a-4c85-949d-12ebf17abf93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524372112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2524372112 |
| Directory | /workspace/36.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_smoke.3716338913 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 747578497 ps |
| CPU time | 16.33 seconds |
| Started | Feb 21 01:21:10 PM PST 24 |
| Finished | Feb 21 01:21:27 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-ee21c76f-25f0-4310-8592-8f7bb9af55d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716338913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3716338913 |
| Directory | /workspace/36.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.2496843218 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 9375366561 ps |
| CPU time | 2126.29 seconds |
| Started | Feb 21 01:21:17 PM PST 24 |
| Finished | Feb 21 01:56:44 PM PST 24 |
| Peak memory | 375532 kb |
| Host | smart-0375cc41-1827-439c-8462-7a8e68aecbc5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496843218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.2496843218 |
| Directory | /workspace/36.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.831418023 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 23234028731 ps |
| CPU time | 345.81 seconds |
| Started | Feb 21 01:21:06 PM PST 24 |
| Finished | Feb 21 01:26:52 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-0579cf81-7b5c-42b3-abf3-01c58144594f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831418023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_stress_pipeline.831418023 |
| Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1612757651 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2385422695 ps |
| CPU time | 84.28 seconds |
| Started | Feb 21 01:21:22 PM PST 24 |
| Finished | Feb 21 01:22:47 PM PST 24 |
| Peak memory | 332464 kb |
| Host | smart-fe92b5df-e506-4e5f-ab69-ff9d82a44e8e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612757651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.1612757651 |
| Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1077489629 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 9165487947 ps |
| CPU time | 783.99 seconds |
| Started | Feb 21 01:21:19 PM PST 24 |
| Finished | Feb 21 01:34:23 PM PST 24 |
| Peak memory | 369396 kb |
| Host | smart-3dceff66-80e5-4f08-ae75-73ffa8c1df8c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077489629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.1077489629 |
| Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.1442796088 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 23121785 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:21:17 PM PST 24 |
| Finished | Feb 21 01:21:18 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-8da7ce73-d178-4a05-8b1e-a3278eda4f78 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442796088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1442796088 |
| Directory | /workspace/37.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_bijection.405755577 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1151931610 ps |
| CPU time | 14.34 seconds |
| Started | Feb 21 01:21:18 PM PST 24 |
| Finished | Feb 21 01:21:33 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-5ea90d8e-50a9-4b27-bc40-5453563487a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405755577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection. 405755577 |
| Directory | /workspace/37.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_executable.2056993342 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 31415911566 ps |
| CPU time | 875.12 seconds |
| Started | Feb 21 01:21:21 PM PST 24 |
| Finished | Feb 21 01:35:57 PM PST 24 |
| Peak memory | 360108 kb |
| Host | smart-5c89ad8c-121a-4efd-b980-ed365a151d0d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056993342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.2056993342 |
| Directory | /workspace/37.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.769969873 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 604341535 ps |
| CPU time | 40.17 seconds |
| Started | Feb 21 01:21:21 PM PST 24 |
| Finished | Feb 21 01:22:02 PM PST 24 |
| Peak memory | 301824 kb |
| Host | smart-56a34d8f-0fdc-4f08-83e5-ccec371206de |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769969873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.sram_ctrl_max_throughput.769969873 |
| Directory | /workspace/37.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.4092651594 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 331327950 ps |
| CPU time | 2.86 seconds |
| Started | Feb 21 01:21:20 PM PST 24 |
| Finished | Feb 21 01:21:24 PM PST 24 |
| Peak memory | 210800 kb |
| Host | smart-5f3396fe-94cf-43e2-ac4d-84560132133e |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092651594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.4092651594 |
| Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.743582560 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 488093627 ps |
| CPU time | 5.57 seconds |
| Started | Feb 21 01:21:20 PM PST 24 |
| Finished | Feb 21 01:21:26 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-45310d2c-6587-412d-9aa2-07c8a8a561d2 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743582560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _mem_walk.743582560 |
| Directory | /workspace/37.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.2012298137 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 50589574942 ps |
| CPU time | 658.62 seconds |
| Started | Feb 21 01:21:23 PM PST 24 |
| Finished | Feb 21 01:32:22 PM PST 24 |
| Peak memory | 358252 kb |
| Host | smart-79b37812-d078-4d6d-8f88-5a47a70dd527 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012298137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.2012298137 |
| Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.857070962 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 326443370 ps |
| CPU time | 16.11 seconds |
| Started | Feb 21 01:21:22 PM PST 24 |
| Finished | Feb 21 01:21:38 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-995c5e80-f6f0-4b68-a97f-567491077836 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857070962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s ram_ctrl_partial_access.857070962 |
| Directory | /workspace/37.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3116103581 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2959817389 ps |
| CPU time | 211.85 seconds |
| Started | Feb 21 01:21:17 PM PST 24 |
| Finished | Feb 21 01:24:49 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-b7fd863b-e538-4522-b46e-3e78573e8718 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116103581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3116103581 |
| Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.1691369297 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 31076892 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 01:21:18 PM PST 24 |
| Finished | Feb 21 01:21:19 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-481c9cbf-7fa9-405e-bfef-d68c91b782cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691369297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1691369297 |
| Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3216173855 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 7438580053 ps |
| CPU time | 765.77 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:34:19 PM PST 24 |
| Peak memory | 348028 kb |
| Host | smart-8d4be766-6d98-4d12-a866-2f9bcade61e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216173855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3216173855 |
| Directory | /workspace/37.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_smoke.341896908 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 373168657 ps |
| CPU time | 13.89 seconds |
| Started | Feb 21 01:21:25 PM PST 24 |
| Finished | Feb 21 01:21:39 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-abe39e23-29e8-4c3b-9884-19c188fef6fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341896908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.341896908 |
| Directory | /workspace/37.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.2423863737 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 153925837938 ps |
| CPU time | 5455.42 seconds |
| Started | Feb 21 01:21:22 PM PST 24 |
| Finished | Feb 21 02:52:18 PM PST 24 |
| Peak memory | 381900 kb |
| Host | smart-c05ccf94-8784-4484-9273-05179bcebfe0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423863737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.2423863737 |
| Directory | /workspace/37.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.824890141 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 16166307213 ps |
| CPU time | 203.73 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:24:48 PM PST 24 |
| Peak memory | 202808 kb |
| Host | smart-a41dc9ea-f3d3-4433-b62f-bdd5bf6a87a2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824890141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_stress_pipeline.824890141 |
| Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2285021276 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 47229611 ps |
| CPU time | 2.59 seconds |
| Started | Feb 21 01:21:18 PM PST 24 |
| Finished | Feb 21 01:21:21 PM PST 24 |
| Peak memory | 210896 kb |
| Host | smart-8c79af6f-c308-4725-976c-fa801e3eac81 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285021276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2285021276 |
| Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3161117470 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 11911846198 ps |
| CPU time | 747.72 seconds |
| Started | Feb 21 01:21:23 PM PST 24 |
| Finished | Feb 21 01:33:51 PM PST 24 |
| Peak memory | 373076 kb |
| Host | smart-53758c49-24e5-4d56-bc93-95f77846eb1c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161117470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.3161117470 |
| Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.98368948 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 16565674 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:21:29 PM PST 24 |
| Finished | Feb 21 01:21:30 PM PST 24 |
| Peak memory | 202480 kb |
| Host | smart-0c1065ba-17ca-41d9-922b-90e207ea33a2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98368948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_alert_test.98368948 |
| Directory | /workspace/38.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_bijection.3985807354 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 19759636983 ps |
| CPU time | 79.61 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:22:44 PM PST 24 |
| Peak memory | 202852 kb |
| Host | smart-8af9d91d-16c5-4e72-be3c-9af03c575a59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985807354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .3985807354 |
| Directory | /workspace/38.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_executable.1416161248 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 49760030042 ps |
| CPU time | 1124.06 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:40:09 PM PST 24 |
| Peak memory | 373512 kb |
| Host | smart-55fe7976-aa8c-4df0-b91c-f0280f91d3e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416161248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1416161248 |
| Directory | /workspace/38.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.3060132920 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 578404442 ps |
| CPU time | 3.52 seconds |
| Started | Feb 21 01:21:30 PM PST 24 |
| Finished | Feb 21 01:21:34 PM PST 24 |
| Peak memory | 210824 kb |
| Host | smart-9a758711-6037-47d1-9e76-ae17720d9ead |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060132920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.3060132920 |
| Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.1650360385 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 275393073 ps |
| CPU time | 41.07 seconds |
| Started | Feb 21 01:21:26 PM PST 24 |
| Finished | Feb 21 01:22:08 PM PST 24 |
| Peak memory | 295356 kb |
| Host | smart-fc9e0bc6-22e7-4fe6-88d2-171f2805189d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650360385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.1650360385 |
| Directory | /workspace/38.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2151725052 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 62858054 ps |
| CPU time | 4.73 seconds |
| Started | Feb 21 01:21:30 PM PST 24 |
| Finished | Feb 21 01:21:35 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-655c361a-cfe6-4780-ad68-0c281ba168e5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151725052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.2151725052 |
| Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.1647825929 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 688493151 ps |
| CPU time | 9.68 seconds |
| Started | Feb 21 01:21:19 PM PST 24 |
| Finished | Feb 21 01:21:29 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-ad1b3606-26a2-4c60-8c39-0f1a64eac6bf |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647825929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1647825929 |
| Directory | /workspace/38.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.3259234295 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 5674771415 ps |
| CPU time | 871.32 seconds |
| Started | Feb 21 01:21:16 PM PST 24 |
| Finished | Feb 21 01:35:48 PM PST 24 |
| Peak memory | 375604 kb |
| Host | smart-3d81edde-8d87-4aa1-a5a7-4997338c7656 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259234295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.3259234295 |
| Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.1279514830 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2370170782 ps |
| CPU time | 136.6 seconds |
| Started | Feb 21 01:21:21 PM PST 24 |
| Finished | Feb 21 01:23:38 PM PST 24 |
| Peak memory | 362800 kb |
| Host | smart-53135c1c-8a34-4a81-9ab8-e43887f19ec7 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279514830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.1279514830 |
| Directory | /workspace/38.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4206270975 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 14687472682 ps |
| CPU time | 263.38 seconds |
| Started | Feb 21 01:21:18 PM PST 24 |
| Finished | Feb 21 01:25:42 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-f433f530-d843-4c17-b166-092f6a42d4fa |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206270975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.4206270975 |
| Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.1665969905 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 73327168 ps |
| CPU time | 0.87 seconds |
| Started | Feb 21 01:21:23 PM PST 24 |
| Finished | Feb 21 01:21:24 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-e67cf99c-fe01-4ac0-9fe3-9a907061d66b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665969905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1665969905 |
| Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_regwen.3364242764 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 18004158600 ps |
| CPU time | 1669.68 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:49:14 PM PST 24 |
| Peak memory | 372456 kb |
| Host | smart-da74323b-26b5-430e-bf0c-f63abcc14fd5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364242764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3364242764 |
| Directory | /workspace/38.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_smoke.646483298 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 292517656 ps |
| CPU time | 20.79 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:21:45 PM PST 24 |
| Peak memory | 264876 kb |
| Host | smart-ac55ee31-32c4-4ae2-a0c4-c513009ab705 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646483298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.646483298 |
| Directory | /workspace/38.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.2687163095 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 81089394237 ps |
| CPU time | 2018.98 seconds |
| Started | Feb 21 01:21:30 PM PST 24 |
| Finished | Feb 21 01:55:10 PM PST 24 |
| Peak memory | 370768 kb |
| Host | smart-c5c041e0-062c-424a-b00d-45ec1b0acdc6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687163095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.2687163095 |
| Directory | /workspace/38.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3482839030 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 7315776599 ps |
| CPU time | 177.37 seconds |
| Started | Feb 21 01:21:26 PM PST 24 |
| Finished | Feb 21 01:24:24 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-089e386c-4dc6-4d0f-8d5c-3692cea7ac66 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482839030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.3482839030 |
| Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1648915431 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 131299614 ps |
| CPU time | 1.56 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:21:29 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-b90c4a81-42d9-42e9-bd81-4ecc68136e47 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648915431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1648915431 |
| Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2934159706 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2069290122 ps |
| CPU time | 615.48 seconds |
| Started | Feb 21 01:21:30 PM PST 24 |
| Finished | Feb 21 01:31:46 PM PST 24 |
| Peak memory | 368280 kb |
| Host | smart-e22f67a3-1123-4745-a1a5-9699f0581f45 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934159706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.2934159706 |
| Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.1998090100 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 19814345 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:21:34 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-75f2d00d-db25-482c-9e6e-c6d32ec198ef |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998090100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1998090100 |
| Directory | /workspace/39.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_bijection.1489379843 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2700492900 ps |
| CPU time | 45.81 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:22:10 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-08237d25-f85a-4d15-bb5c-3ea7351010fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489379843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1489379843 |
| Directory | /workspace/39.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_executable.2748408674 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 10180207855 ps |
| CPU time | 592.47 seconds |
| Started | Feb 21 01:21:26 PM PST 24 |
| Finished | Feb 21 01:31:19 PM PST 24 |
| Peak memory | 371752 kb |
| Host | smart-e5d0d017-679b-4151-88c7-d4cbc9db6091 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748408674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2748408674 |
| Directory | /workspace/39.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.3763283875 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 1143951298 ps |
| CPU time | 4.6 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:21:32 PM PST 24 |
| Peak memory | 210844 kb |
| Host | smart-b1f8cfdf-40c8-4a17-8ce7-4aabf6c64c1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763283875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.3763283875 |
| Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.2153621293 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 171542786 ps |
| CPU time | 23.9 seconds |
| Started | Feb 21 01:21:30 PM PST 24 |
| Finished | Feb 21 01:21:55 PM PST 24 |
| Peak memory | 284476 kb |
| Host | smart-4ebf270c-353d-4e60-8ba4-d66a2f0bde4b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153621293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.2153621293 |
| Directory | /workspace/39.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2460271623 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 83873544 ps |
| CPU time | 3.02 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:21:28 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-1c30a897-dde0-4726-a85f-0c1e6b6c5693 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460271623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2460271623 |
| Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.1853233355 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 76751695 ps |
| CPU time | 4.45 seconds |
| Started | Feb 21 01:21:31 PM PST 24 |
| Finished | Feb 21 01:21:36 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-64fc7bba-4d2b-42d6-b010-d84438a92b88 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853233355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.1853233355 |
| Directory | /workspace/39.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.3904803649 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2306512098 ps |
| CPU time | 689.09 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:32:57 PM PST 24 |
| Peak memory | 369068 kb |
| Host | smart-80476835-b3c8-4983-9919-0cdba6d10a18 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904803649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.3904803649 |
| Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.1322208118 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2285761249 ps |
| CPU time | 14.51 seconds |
| Started | Feb 21 01:21:30 PM PST 24 |
| Finished | Feb 21 01:21:45 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-7a910710-7db3-4627-9086-1849613d82ca |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322208118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.1322208118 |
| Directory | /workspace/39.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.690467955 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3487099046 ps |
| CPU time | 243.73 seconds |
| Started | Feb 21 01:21:24 PM PST 24 |
| Finished | Feb 21 01:25:28 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-e12e734b-97af-418b-af1e-227b3df087de |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690467955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.690467955 |
| Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.2577842712 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 27910455 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 01:21:35 PM PST 24 |
| Finished | Feb 21 01:21:36 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-b33df728-07c9-45bf-b446-870edf72704e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577842712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2577842712 |
| Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_regwen.138034145 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 5580681894 ps |
| CPU time | 1214.41 seconds |
| Started | Feb 21 01:21:31 PM PST 24 |
| Finished | Feb 21 01:41:46 PM PST 24 |
| Peak memory | 372296 kb |
| Host | smart-2343bf91-4c7f-4998-919e-48918785c814 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138034145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.138034145 |
| Directory | /workspace/39.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_smoke.1168265768 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 495882215 ps |
| CPU time | 8.33 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:21:36 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-171e6b38-cc92-492d-9d77-0205b044c882 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168265768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1168265768 |
| Directory | /workspace/39.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.3549954500 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 28330886750 ps |
| CPU time | 982.79 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:37:50 PM PST 24 |
| Peak memory | 374544 kb |
| Host | smart-1f24a57a-052c-4b92-8127-de5fdaa5f728 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549954500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.3549954500 |
| Directory | /workspace/39.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1970776466 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1576752366 ps |
| CPU time | 153.31 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:24:01 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-2dbeeaff-4c0b-4f04-9de3-2dd55f15006a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970776466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1970776466 |
| Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1355192415 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 600158836 ps |
| CPU time | 46.49 seconds |
| Started | Feb 21 01:21:23 PM PST 24 |
| Finished | Feb 21 01:22:10 PM PST 24 |
| Peak memory | 328800 kb |
| Host | smart-46bba14d-404b-4bc0-ad2e-4f51053ff874 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355192415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1355192415 |
| Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.4209222910 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 19536890612 ps |
| CPU time | 492.53 seconds |
| Started | Feb 21 01:18:55 PM PST 24 |
| Finished | Feb 21 01:27:08 PM PST 24 |
| Peak memory | 372380 kb |
| Host | smart-71075100-eceb-4347-8d8c-1c3346669ca0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209222910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.4209222910 |
| Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.964066736 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 21566547 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:18:57 PM PST 24 |
| Finished | Feb 21 01:18:58 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-27bfff13-6e17-4878-8183-1c3a9b6561cf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964066736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.964066736 |
| Directory | /workspace/4.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_bijection.1312167212 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3212009881 ps |
| CPU time | 49.82 seconds |
| Started | Feb 21 01:18:44 PM PST 24 |
| Finished | Feb 21 01:19:34 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-110f13fc-2982-46e6-a190-03e4a7639946 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312167212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 1312167212 |
| Directory | /workspace/4.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_executable.1983266676 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2031569144 ps |
| CPU time | 304.62 seconds |
| Started | Feb 21 01:18:52 PM PST 24 |
| Finished | Feb 21 01:23:58 PM PST 24 |
| Peak memory | 332580 kb |
| Host | smart-fbb47938-5c8e-4bf2-925a-f271cce68b7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983266676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.1983266676 |
| Directory | /workspace/4.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.2790742780 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 740981999 ps |
| CPU time | 5.35 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:19:04 PM PST 24 |
| Peak memory | 210864 kb |
| Host | smart-c5b07daa-38e9-4d5a-9e82-695218ac25c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790742780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.2790742780 |
| Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.1626920614 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 196476928 ps |
| CPU time | 48.57 seconds |
| Started | Feb 21 01:18:45 PM PST 24 |
| Finished | Feb 21 01:19:33 PM PST 24 |
| Peak memory | 300784 kb |
| Host | smart-bf04c8ea-22b9-453c-86f8-6b9c3022cf7e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626920614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.1626920614 |
| Directory | /workspace/4.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1306393657 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1806048429 ps |
| CPU time | 6 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:19:04 PM PST 24 |
| Peak memory | 210816 kb |
| Host | smart-da888027-55bb-4532-b4f4-123a7a5ea177 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306393657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.1306393657 |
| Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.4141040403 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 257995656 ps |
| CPU time | 4.61 seconds |
| Started | Feb 21 01:18:42 PM PST 24 |
| Finished | Feb 21 01:18:47 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-0b9a17e1-06da-4fdd-9e93-ff1ebabe0b0e |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141040403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.4141040403 |
| Directory | /workspace/4.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.3034838832 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 57527801506 ps |
| CPU time | 1180.7 seconds |
| Started | Feb 21 01:18:44 PM PST 24 |
| Finished | Feb 21 01:38:25 PM PST 24 |
| Peak memory | 372552 kb |
| Host | smart-e4fadff4-8b45-4f14-9416-d6fe56db789b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034838832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.3034838832 |
| Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.4214301159 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 950803166 ps |
| CPU time | 17.31 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:19:16 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-cfe5ed06-a04d-4a63-92e3-619d456e802f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214301159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.4214301159 |
| Directory | /workspace/4.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4109474118 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 9064191749 ps |
| CPU time | 212.28 seconds |
| Started | Feb 21 01:18:46 PM PST 24 |
| Finished | Feb 21 01:22:19 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-ec6bb9c5-6c54-47cc-8082-345e284d9f7f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109474118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.4109474118 |
| Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.99284011 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 76336280 ps |
| CPU time | 1.14 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:18:59 PM PST 24 |
| Peak memory | 202912 kb |
| Host | smart-cc9a62fb-d3b0-4219-90fb-b15583151f43 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99284011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.99284011 |
| Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_regwen.1482206392 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 13433771338 ps |
| CPU time | 761.81 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:31:40 PM PST 24 |
| Peak memory | 368468 kb |
| Host | smart-236d81ab-8b42-4818-98ca-e2e968c1b74b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482206392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1482206392 |
| Directory | /workspace/4.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.2316085168 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 747758734 ps |
| CPU time | 2.65 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:19:01 PM PST 24 |
| Peak memory | 221168 kb |
| Host | smart-352f49c5-81c1-4cb3-9bc7-4ccdcd2b7dd0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316085168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2316085168 |
| Directory | /workspace/4.sram_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_smoke.1257786910 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 655921090 ps |
| CPU time | 1.7 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:19:05 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-c4b9cf09-a036-4eb2-98c9-e9c855619c51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257786910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1257786910 |
| Directory | /workspace/4.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.3705070971 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 15598077887 ps |
| CPU time | 534.45 seconds |
| Started | Feb 21 01:18:44 PM PST 24 |
| Finished | Feb 21 01:27:39 PM PST 24 |
| Peak memory | 367812 kb |
| Host | smart-82202976-7f92-4545-883c-78cfc68f65ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705070971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.3705070971 |
| Directory | /workspace/4.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2867817626 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 10255695397 ps |
| CPU time | 274.97 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:23:38 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-b3e39c35-48ed-4bd2-bb1a-fa4df451b280 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867817626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2867817626 |
| Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1030013371 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 378103700 ps |
| CPU time | 1.85 seconds |
| Started | Feb 21 01:18:45 PM PST 24 |
| Finished | Feb 21 01:18:48 PM PST 24 |
| Peak memory | 213432 kb |
| Host | smart-14375446-1c50-46f1-ba35-225f10b264f9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030013371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1030013371 |
| Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1949361548 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 20257959303 ps |
| CPU time | 1163.25 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:40:58 PM PST 24 |
| Peak memory | 372516 kb |
| Host | smart-d63e618c-fcdb-485a-878b-2434953cae2d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949361548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.1949361548 |
| Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.839861014 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 36391825 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:21:38 PM PST 24 |
| Finished | Feb 21 01:21:39 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-63840ebd-4f4d-441c-a421-1d112b90a524 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839861014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.839861014 |
| Directory | /workspace/40.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_bijection.1159522126 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 12979338929 ps |
| CPU time | 34.46 seconds |
| Started | Feb 21 01:21:28 PM PST 24 |
| Finished | Feb 21 01:22:02 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-9e99421b-6717-4788-bb84-e50b4bcd0cc1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159522126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .1159522126 |
| Directory | /workspace/40.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_executable.3840749890 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 9051289845 ps |
| CPU time | 971.98 seconds |
| Started | Feb 21 01:21:34 PM PST 24 |
| Finished | Feb 21 01:37:47 PM PST 24 |
| Peak memory | 368404 kb |
| Host | smart-b84bd673-72e4-4e49-9e73-b2c350f0dcf2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840749890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.3840749890 |
| Directory | /workspace/40.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.3706983360 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 613202625 ps |
| CPU time | 8.22 seconds |
| Started | Feb 21 01:21:27 PM PST 24 |
| Finished | Feb 21 01:21:35 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-74d9c68b-7099-4b02-ab9a-c693b90753a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706983360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.3706983360 |
| Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.3139747238 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 90861108 ps |
| CPU time | 39.24 seconds |
| Started | Feb 21 01:21:26 PM PST 24 |
| Finished | Feb 21 01:22:06 PM PST 24 |
| Peak memory | 289212 kb |
| Host | smart-bf47edae-c7b8-42e6-81ff-8a45ac271848 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139747238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.3139747238 |
| Directory | /workspace/40.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1185063239 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 501080160 ps |
| CPU time | 3.06 seconds |
| Started | Feb 21 01:21:31 PM PST 24 |
| Finished | Feb 21 01:21:35 PM PST 24 |
| Peak memory | 211028 kb |
| Host | smart-db7426c2-5b0a-47d3-9600-6888c8bc808c |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185063239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.1185063239 |
| Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.1077313904 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 572751023 ps |
| CPU time | 9.95 seconds |
| Started | Feb 21 01:21:36 PM PST 24 |
| Finished | Feb 21 01:21:46 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-13ae159f-ee19-412c-876e-0a9c5aa7db0b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077313904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.1077313904 |
| Directory | /workspace/40.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.3447119004 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4159465216 ps |
| CPU time | 468.88 seconds |
| Started | Feb 21 01:21:30 PM PST 24 |
| Finished | Feb 21 01:29:19 PM PST 24 |
| Peak memory | 370368 kb |
| Host | smart-8c1d8f07-e8dd-452e-a030-565c507b7631 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447119004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.3447119004 |
| Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.1386446965 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2327218231 ps |
| CPU time | 53.74 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:22:27 PM PST 24 |
| Peak memory | 328112 kb |
| Host | smart-d080fad1-cfdc-4d37-b8e1-4ab33f85ec7b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386446965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.1386446965 |
| Directory | /workspace/40.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3862725650 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3229473462 ps |
| CPU time | 232.65 seconds |
| Started | Feb 21 01:21:26 PM PST 24 |
| Finished | Feb 21 01:25:20 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-c8490abd-3966-4513-9c98-3702d4e839a4 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862725650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.3862725650 |
| Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2636128152 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 143794977 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 01:21:31 PM PST 24 |
| Finished | Feb 21 01:21:32 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-935f1234-ce69-45ea-bce6-62214748299b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636128152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2636128152 |
| Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_regwen.3535001346 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 38935936909 ps |
| CPU time | 1751.46 seconds |
| Started | Feb 21 01:21:33 PM PST 24 |
| Finished | Feb 21 01:50:46 PM PST 24 |
| Peak memory | 374140 kb |
| Host | smart-020df072-09c4-4713-bd75-48c1f4ef382e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535001346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3535001346 |
| Directory | /workspace/40.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_smoke.1949129919 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 87698563 ps |
| CPU time | 1.93 seconds |
| Started | Feb 21 01:21:33 PM PST 24 |
| Finished | Feb 21 01:21:36 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-c1f3470d-2f0c-4e82-8412-a2c188f27e72 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949129919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1949129919 |
| Directory | /workspace/40.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3571356785 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2388350731 ps |
| CPU time | 215.98 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:25:09 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-8d96caab-4d8a-4ae6-afd3-3acd847105d3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571356785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.3571356785 |
| Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3469596932 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 896114189 ps |
| CPU time | 98.84 seconds |
| Started | Feb 21 01:21:21 PM PST 24 |
| Finished | Feb 21 01:23:01 PM PST 24 |
| Peak memory | 340640 kb |
| Host | smart-4fac2318-e598-4e73-9d56-013a5cfc2adb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469596932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3469596932 |
| Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3291001131 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1807136385 ps |
| CPU time | 29.84 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:22:16 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-830503d0-da23-4f84-9f16-e09a2a0b1e3c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291001131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.3291001131 |
| Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.3483228917 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 25050416 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:21:33 PM PST 24 |
| Finished | Feb 21 01:21:36 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-f2b788ad-1b26-46de-96f6-0d472674e8ef |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483228917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3483228917 |
| Directory | /workspace/41.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_bijection.3823916791 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 2865606562 ps |
| CPU time | 58.54 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:22:32 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-2bd34643-5e35-4ee0-b72d-e2b706a17e45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823916791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .3823916791 |
| Directory | /workspace/41.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_executable.2705830572 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 47787543240 ps |
| CPU time | 996.01 seconds |
| Started | Feb 21 01:21:46 PM PST 24 |
| Finished | Feb 21 01:38:22 PM PST 24 |
| Peak memory | 373408 kb |
| Host | smart-06b27c67-d829-4df8-b4f7-8da986ba992c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705830572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.2705830572 |
| Directory | /workspace/41.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.2595260033 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 354890648 ps |
| CPU time | 3 seconds |
| Started | Feb 21 01:21:33 PM PST 24 |
| Finished | Feb 21 01:21:38 PM PST 24 |
| Peak memory | 210904 kb |
| Host | smart-62c80e40-8601-4a7d-9899-4a21ad2320be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595260033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.2595260033 |
| Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.555370227 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 361554171 ps |
| CPU time | 6.23 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:21:40 PM PST 24 |
| Peak memory | 235444 kb |
| Host | smart-6e09dd0e-fb54-4298-ac7f-4cf8d798d9ff |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555370227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.sram_ctrl_max_throughput.555370227 |
| Directory | /workspace/41.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2267408135 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 67408733 ps |
| CPU time | 5.07 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:21:51 PM PST 24 |
| Peak memory | 216048 kb |
| Host | smart-0bea80c4-f031-4ed7-969d-5b90271bec00 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267408135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.2267408135 |
| Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.1354031782 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 73316979 ps |
| CPU time | 4.59 seconds |
| Started | Feb 21 01:21:42 PM PST 24 |
| Finished | Feb 21 01:21:48 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-6593d657-fcdd-4592-a62d-830f6accae8f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354031782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.1354031782 |
| Directory | /workspace/41.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.2920670890 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 9328594738 ps |
| CPU time | 539.88 seconds |
| Started | Feb 21 01:21:42 PM PST 24 |
| Finished | Feb 21 01:30:43 PM PST 24 |
| Peak memory | 371428 kb |
| Host | smart-aa9ae87b-bf1b-4bc8-98a7-c261e2732197 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920670890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.2920670890 |
| Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.752358607 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 73783988 ps |
| CPU time | 1.78 seconds |
| Started | Feb 21 01:21:37 PM PST 24 |
| Finished | Feb 21 01:21:40 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-3f2e017a-942c-4eb7-a4f8-8e9badd48acb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752358607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.752358607 |
| Directory | /workspace/41.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1644221243 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 19568642566 ps |
| CPU time | 262.75 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:26:09 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-9b69de29-647b-4be8-9d6a-7115f370a893 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644221243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.1644221243 |
| Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.3875489301 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 45812448 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 01:21:46 PM PST 24 |
| Finished | Feb 21 01:21:47 PM PST 24 |
| Peak memory | 202876 kb |
| Host | smart-bff4fca2-0651-4248-a122-a7a7959cd709 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875489301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3875489301 |
| Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_regwen.858347699 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 75004369216 ps |
| CPU time | 1620 seconds |
| Started | Feb 21 01:21:43 PM PST 24 |
| Finished | Feb 21 01:48:44 PM PST 24 |
| Peak memory | 375516 kb |
| Host | smart-8c341a63-8041-46ec-945d-f06893873cc0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858347699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.858347699 |
| Directory | /workspace/41.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_smoke.3223190972 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 13246763112 ps |
| CPU time | 19.48 seconds |
| Started | Feb 21 01:21:42 PM PST 24 |
| Finished | Feb 21 01:22:02 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-165ec7ca-7a0d-4804-a8e3-0e80af6d2741 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223190972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3223190972 |
| Directory | /workspace/41.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2465801130 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 6126366134 ps |
| CPU time | 245.26 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:25:39 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-61de73c2-1ecb-47a0-8d8f-a062e246c01a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465801130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.2465801130 |
| Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.585586648 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 139253763 ps |
| CPU time | 71.41 seconds |
| Started | Feb 21 01:21:34 PM PST 24 |
| Finished | Feb 21 01:22:47 PM PST 24 |
| Peak memory | 330704 kb |
| Host | smart-a76a7194-fe84-4f65-9493-228bf162bbe3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585586648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.585586648 |
| Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2660913889 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3186421726 ps |
| CPU time | 832.5 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:35:37 PM PST 24 |
| Peak memory | 374484 kb |
| Host | smart-8d2a7311-0281-44f2-8f19-993d86078a08 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660913889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.2660913889 |
| Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.3870975108 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 16439667 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:21:45 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-7605fb25-ea0c-4d61-834c-0fe2d4f4baad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870975108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3870975108 |
| Directory | /workspace/42.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_bijection.2512626471 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 297396532 ps |
| CPU time | 18.19 seconds |
| Started | Feb 21 01:21:42 PM PST 24 |
| Finished | Feb 21 01:22:01 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-3a1f7b8c-cdc7-4141-9a4e-86d068a7590f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512626471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .2512626471 |
| Directory | /workspace/42.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_executable.2019911907 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 117570906084 ps |
| CPU time | 641.12 seconds |
| Started | Feb 21 01:22:03 PM PST 24 |
| Finished | Feb 21 01:32:45 PM PST 24 |
| Peak memory | 368472 kb |
| Host | smart-f19c0e64-e15f-4f64-9afa-10e6f5643ec3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019911907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2019911907 |
| Directory | /workspace/42.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.3575677772 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 225457001 ps |
| CPU time | 110.37 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:23:36 PM PST 24 |
| Peak memory | 355904 kb |
| Host | smart-0986c068-d7f6-4ec0-81ca-8a0549b33bbb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575677772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.3575677772 |
| Directory | /workspace/42.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2333613474 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 596667617 ps |
| CPU time | 5.54 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:21:50 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-04b41b1a-474d-4a5a-85e2-90cb1d777464 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333613474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.2333613474 |
| Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.4183814796 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 446685159 ps |
| CPU time | 8.9 seconds |
| Started | Feb 21 01:21:54 PM PST 24 |
| Finished | Feb 21 01:22:03 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-d741055e-96f9-43c9-9c9a-89fe74ce4d10 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183814796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.4183814796 |
| Directory | /workspace/42.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.3407437960 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 6763418196 ps |
| CPU time | 611.71 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:31:57 PM PST 24 |
| Peak memory | 370040 kb |
| Host | smart-fa0917e5-513b-44eb-8ddc-02664438a553 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407437960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.3407437960 |
| Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.2625671918 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 209712097 ps |
| CPU time | 15.03 seconds |
| Started | Feb 21 01:21:38 PM PST 24 |
| Finished | Feb 21 01:21:53 PM PST 24 |
| Peak memory | 256432 kb |
| Host | smart-3a000433-8c61-4941-a736-6f95257b69bb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625671918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.2625671918 |
| Directory | /workspace/42.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.213491896 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6745171496 ps |
| CPU time | 473.74 seconds |
| Started | Feb 21 01:21:34 PM PST 24 |
| Finished | Feb 21 01:29:29 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-f1d46969-2ca1-4a75-85ae-bbb98ec9bedd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213491896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.sram_ctrl_partial_access_b2b.213491896 |
| Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.1414480974 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 28399763 ps |
| CPU time | 0.92 seconds |
| Started | Feb 21 01:21:47 PM PST 24 |
| Finished | Feb 21 01:21:49 PM PST 24 |
| Peak memory | 202864 kb |
| Host | smart-93520fa2-a84e-4896-a7a9-0d124ff3f075 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414480974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1414480974 |
| Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_regwen.3959414319 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2659691063 ps |
| CPU time | 183.85 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:24:49 PM PST 24 |
| Peak memory | 347696 kb |
| Host | smart-17f00101-7b98-46fc-a0df-92416ec3c2ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959414319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3959414319 |
| Directory | /workspace/42.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_smoke.535248937 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 125263663 ps |
| CPU time | 3.11 seconds |
| Started | Feb 21 01:21:32 PM PST 24 |
| Finished | Feb 21 01:21:36 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-5a925587-7f08-49ec-9368-834fbb62a9b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535248937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.535248937 |
| Directory | /workspace/42.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3697743588 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2193821160 ps |
| CPU time | 210.44 seconds |
| Started | Feb 21 01:21:37 PM PST 24 |
| Finished | Feb 21 01:25:08 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-5814f8ec-b43b-4a89-bd84-af30a6c7a1f8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697743588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.3697743588 |
| Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.15569823 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 127560086 ps |
| CPU time | 59.8 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:22:46 PM PST 24 |
| Peak memory | 309332 kb |
| Host | smart-b99724ae-a0fe-491e-b7b2-bbed8b427a29 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.sram_ctrl_throughput_w_partial_write.15569823 |
| Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.3765905820 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 143044178 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 01:22:03 PM PST 24 |
| Finished | Feb 21 01:22:05 PM PST 24 |
| Peak memory | 201592 kb |
| Host | smart-737e04e5-2d15-4ef4-9de2-671a3c4842d3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765905820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3765905820 |
| Directory | /workspace/43.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_bijection.306677829 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 10375043391 ps |
| CPU time | 58.14 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:22:44 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-9dcad3f6-4122-4357-8753-0797f9ebd4fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306677829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection. 306677829 |
| Directory | /workspace/43.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_executable.3825326191 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 47268955319 ps |
| CPU time | 1005.22 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:38:32 PM PST 24 |
| Peak memory | 373328 kb |
| Host | smart-0ac49a84-edcf-4780-b674-7a60c6347ed6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825326191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.3825326191 |
| Directory | /workspace/43.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.1707904436 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 371992610 ps |
| CPU time | 8.74 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:21:54 PM PST 24 |
| Peak memory | 210900 kb |
| Host | smart-222aade0-786e-4ecb-9a80-ace9216e2cd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707904436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.1707904436 |
| Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.825506795 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 70847364 ps |
| CPU time | 12.56 seconds |
| Started | Feb 21 01:21:43 PM PST 24 |
| Finished | Feb 21 01:21:56 PM PST 24 |
| Peak memory | 251756 kb |
| Host | smart-887d2b91-83a1-4e54-93fc-77568e329780 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825506795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.sram_ctrl_max_throughput.825506795 |
| Directory | /workspace/43.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2296958517 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 236627650 ps |
| CPU time | 4.66 seconds |
| Started | Feb 21 01:21:46 PM PST 24 |
| Finished | Feb 21 01:21:51 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-6d414478-506e-49f7-bdfe-790f3c7c2bd5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296958517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.2296958517 |
| Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.445334464 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 864749364 ps |
| CPU time | 7.83 seconds |
| Started | Feb 21 01:22:02 PM PST 24 |
| Finished | Feb 21 01:22:11 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-80a29949-f0a2-40e3-aa9b-d8069a41255f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445334464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _mem_walk.445334464 |
| Directory | /workspace/43.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2012234469 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 148077436390 ps |
| CPU time | 1148.62 seconds |
| Started | Feb 21 01:21:47 PM PST 24 |
| Finished | Feb 21 01:40:56 PM PST 24 |
| Peak memory | 373332 kb |
| Host | smart-403d7fb6-e9a5-414c-a76b-0f85d3cf8de5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012234469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2012234469 |
| Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.2205952896 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1331584690 ps |
| CPU time | 6.51 seconds |
| Started | Feb 21 01:22:03 PM PST 24 |
| Finished | Feb 21 01:22:10 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-19d7a2b3-9faf-478a-b4cb-bb01c16fdddd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205952896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.2205952896 |
| Directory | /workspace/43.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2581130635 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 26577841975 ps |
| CPU time | 339.23 seconds |
| Started | Feb 21 01:21:43 PM PST 24 |
| Finished | Feb 21 01:27:23 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-d2085199-0538-4dd2-999f-cab55bcf21b5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581130635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.2581130635 |
| Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.1758142571 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 78037704 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 01:21:50 PM PST 24 |
| Finished | Feb 21 01:21:51 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-da15d219-6154-4b99-8ff8-b8b9724a825a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758142571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1758142571 |
| Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_regwen.2837724371 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 432790430 ps |
| CPU time | 164.13 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:24:30 PM PST 24 |
| Peak memory | 369996 kb |
| Host | smart-8199ea85-7da2-4b96-8568-16cb74119e00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837724371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2837724371 |
| Directory | /workspace/43.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_smoke.650047414 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 154399617 ps |
| CPU time | 5.87 seconds |
| Started | Feb 21 01:21:47 PM PST 24 |
| Finished | Feb 21 01:21:53 PM PST 24 |
| Peak memory | 225152 kb |
| Host | smart-e15f6138-4448-4497-b5f5-fa88d57bd958 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650047414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.650047414 |
| Directory | /workspace/43.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3194610906 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5385698966 ps |
| CPU time | 243.46 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:25:49 PM PST 24 |
| Peak memory | 202752 kb |
| Host | smart-66e1db70-ed98-4847-b5c4-3b279a314fb6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194610906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.3194610906 |
| Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1450521484 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1064193853 ps |
| CPU time | 49.8 seconds |
| Started | Feb 21 01:21:44 PM PST 24 |
| Finished | Feb 21 01:22:35 PM PST 24 |
| Peak memory | 308820 kb |
| Host | smart-6d1355a8-87de-48bd-932c-7b7713e8624e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450521484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1450521484 |
| Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3611588450 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 6558779677 ps |
| CPU time | 1120.48 seconds |
| Started | Feb 21 01:21:54 PM PST 24 |
| Finished | Feb 21 01:40:35 PM PST 24 |
| Peak memory | 371448 kb |
| Host | smart-1e2b8e58-0a4a-47ae-9eab-2ceef042de59 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611588450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3611588450 |
| Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.2664014754 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 43489989 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 01:22:25 PM PST 24 |
| Peak memory | 201736 kb |
| Host | smart-ffe59b70-1121-4f84-9ecf-7ff5a0c849a2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664014754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2664014754 |
| Directory | /workspace/44.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_bijection.421210770 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 536895332 ps |
| CPU time | 33.04 seconds |
| Started | Feb 21 01:21:46 PM PST 24 |
| Finished | Feb 21 01:22:19 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-2fbdc455-648c-443b-90aa-db72e4f76014 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421210770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection. 421210770 |
| Directory | /workspace/44.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_executable.3683577822 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 12329721766 ps |
| CPU time | 989.1 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:38:56 PM PST 24 |
| Peak memory | 374416 kb |
| Host | smart-df56ede1-ca77-448c-837d-c0e07ca03740 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683577822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.3683577822 |
| Directory | /workspace/44.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.4075366239 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1456132405 ps |
| CPU time | 10.01 seconds |
| Started | Feb 21 01:21:47 PM PST 24 |
| Finished | Feb 21 01:21:57 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-39025771-1ee7-46c3-b82b-17f024171029 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075366239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.4075366239 |
| Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.4188199802 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 214402428 ps |
| CPU time | 38.27 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:22:24 PM PST 24 |
| Peak memory | 312672 kb |
| Host | smart-dae614e7-07e6-421a-b63d-bb082c17305d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188199802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.4188199802 |
| Directory | /workspace/44.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.4171240628 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 612010654 ps |
| CPU time | 5.23 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:22:34 PM PST 24 |
| Peak memory | 215984 kb |
| Host | smart-9cf066d3-db38-4348-ac7b-44aa1741ed49 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171240628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.4171240628 |
| Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.4010988582 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2387078229 ps |
| CPU time | 9.99 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 01:22:36 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-83b378d0-a081-4cca-a77d-87babac5882d |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010988582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.4010988582 |
| Directory | /workspace/44.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.4050443921 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13395520031 ps |
| CPU time | 984.11 seconds |
| Started | Feb 21 01:21:47 PM PST 24 |
| Finished | Feb 21 01:38:11 PM PST 24 |
| Peak memory | 367428 kb |
| Host | smart-9e5db64b-9aa0-488a-bd3d-cb8a06d002db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050443921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.4050443921 |
| Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.3853527557 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 168439951 ps |
| CPU time | 57.25 seconds |
| Started | Feb 21 01:21:47 PM PST 24 |
| Finished | Feb 21 01:22:45 PM PST 24 |
| Peak memory | 306100 kb |
| Host | smart-e5e63c04-b93f-446a-8490-9d45e8607efc |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853527557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.3853527557 |
| Directory | /workspace/44.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3226886477 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 7977283680 ps |
| CPU time | 169.58 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:24:35 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-93e46d33-6bf9-4aaf-b795-0c195c2fce22 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226886477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.3226886477 |
| Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2195086845 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 88375200 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 01:22:25 PM PST 24 |
| Peak memory | 202644 kb |
| Host | smart-e89233cb-7651-4e66-80b5-67bacbc2e5e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195086845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2195086845 |
| Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_regwen.2925620125 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3391613089 ps |
| CPU time | 201.81 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:25:55 PM PST 24 |
| Peak memory | 333456 kb |
| Host | smart-f12716e9-d4b7-4241-81b9-42e60f1a8150 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925620125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2925620125 |
| Directory | /workspace/44.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_smoke.1949335374 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2726981933 ps |
| CPU time | 121.24 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:23:47 PM PST 24 |
| Peak memory | 370292 kb |
| Host | smart-f9dea522-5e7d-4c99-8124-991de675b0e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949335374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1949335374 |
| Directory | /workspace/44.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.4236108050 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 47672585472 ps |
| CPU time | 3572.36 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 02:21:59 PM PST 24 |
| Peak memory | 375548 kb |
| Host | smart-73b4c44b-94fa-4515-8deb-f4a4c1ce8b8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236108050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.4236108050 |
| Directory | /workspace/44.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3598633731 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2661418308 ps |
| CPU time | 249.12 seconds |
| Started | Feb 21 01:21:46 PM PST 24 |
| Finished | Feb 21 01:25:56 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-1e8a2104-38bb-40ce-b290-19fe11f44490 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598633731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3598633731 |
| Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3279776100 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 553357971 ps |
| CPU time | 42.36 seconds |
| Started | Feb 21 01:21:45 PM PST 24 |
| Finished | Feb 21 01:22:28 PM PST 24 |
| Peak memory | 296524 kb |
| Host | smart-0ec6a510-3c02-488e-be38-e9888714b71f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279776100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3279776100 |
| Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.457157343 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 18118829967 ps |
| CPU time | 690.28 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:33:57 PM PST 24 |
| Peak memory | 374544 kb |
| Host | smart-828c7233-de52-4897-a6d7-bdaef07a49bd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457157343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 45.sram_ctrl_access_during_key_req.457157343 |
| Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.2236870557 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 42068456 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:22:29 PM PST 24 |
| Finished | Feb 21 01:22:30 PM PST 24 |
| Peak memory | 201748 kb |
| Host | smart-a5c77afc-d646-4352-a8d6-ed0d9f86187e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236870557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2236870557 |
| Directory | /workspace/45.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_bijection.106844244 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2139781625 ps |
| CPU time | 29 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:22:55 PM PST 24 |
| Peak memory | 202696 kb |
| Host | smart-862d04b7-19ee-4603-9bdb-956ba4f2ec94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106844244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection. 106844244 |
| Directory | /workspace/45.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_executable.1748051576 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2448686494 ps |
| CPU time | 532.42 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:31:21 PM PST 24 |
| Peak memory | 374504 kb |
| Host | smart-24267ac5-2de1-4a9d-a274-c92b7a42e105 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748051576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.1748051576 |
| Directory | /workspace/45.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.2556260740 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 716314310 ps |
| CPU time | 8.61 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 01:22:35 PM PST 24 |
| Peak memory | 210888 kb |
| Host | smart-ff44c2fd-3f28-4399-8b80-0cf126b59dcb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556260740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.2556260740 |
| Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.1327232860 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 318514097 ps |
| CPU time | 29.99 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 01:22:54 PM PST 24 |
| Peak memory | 284316 kb |
| Host | smart-e2d41e3d-5b97-477d-99b8-c8d98f7fed10 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327232860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.1327232860 |
| Directory | /workspace/45.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3041961255 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 92818820 ps |
| CPU time | 2.92 seconds |
| Started | Feb 21 01:22:30 PM PST 24 |
| Finished | Feb 21 01:22:34 PM PST 24 |
| Peak memory | 215652 kb |
| Host | smart-75b2cf38-7417-4b33-911a-84446bd3f741 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041961255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3041961255 |
| Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.774844844 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1510721279 ps |
| CPU time | 5.5 seconds |
| Started | Feb 21 01:22:29 PM PST 24 |
| Finished | Feb 21 01:22:35 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-4c3203d0-2759-4277-beac-78325b7ce46f |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774844844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _mem_walk.774844844 |
| Directory | /workspace/45.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.3440910370 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 57406455463 ps |
| CPU time | 1165.29 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 01:41:50 PM PST 24 |
| Peak memory | 375168 kb |
| Host | smart-accf57c7-2ad8-493a-b637-22bcd2d4cb67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440910370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.3440910370 |
| Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.2853377457 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 355145929 ps |
| CPU time | 17.62 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 01:22:42 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-5385a89c-1ddc-4492-87b6-b53a35cc7da2 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853377457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.2853377457 |
| Directory | /workspace/45.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1942641357 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 18565336046 ps |
| CPU time | 467.09 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:30:13 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-58ecb900-8ec9-43db-bb7b-cfa66e6a5dc0 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942641357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.1942641357 |
| Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.3471904187 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 39321665 ps |
| CPU time | 0.87 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 01:22:26 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-38c7bf2b-2b2c-469b-b5bb-ff72abbceddd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471904187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3471904187 |
| Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_regwen.1896830602 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 13692936991 ps |
| CPU time | 1527.61 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:47:55 PM PST 24 |
| Peak memory | 367972 kb |
| Host | smart-e44cd2f6-5a29-4307-9d02-691ef0c380d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896830602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1896830602 |
| Directory | /workspace/45.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_smoke.2774960453 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 497077602 ps |
| CPU time | 78.68 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:23:48 PM PST 24 |
| Peak memory | 328004 kb |
| Host | smart-14d06bd7-41ee-4b6c-9873-6173c0de8f88 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774960453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2774960453 |
| Directory | /workspace/45.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.671852674 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 24378140829 ps |
| CPU time | 2286.65 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 02:00:32 PM PST 24 |
| Peak memory | 382340 kb |
| Host | smart-7b7fc2af-5c6f-46b7-bdd5-8223dee551ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671852674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_stress_all.671852674 |
| Directory | /workspace/45.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2086538946 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 13017319033 ps |
| CPU time | 327.41 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:27:55 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-d3b05d86-4685-44d5-8cfd-6adc9395af66 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086538946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2086538946 |
| Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2729671671 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 268421662 ps |
| CPU time | 31.06 seconds |
| Started | Feb 21 01:22:24 PM PST 24 |
| Finished | Feb 21 01:22:56 PM PST 24 |
| Peak memory | 303508 kb |
| Host | smart-d57de42b-6856-422d-9dbc-06a51a81319c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729671671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2729671671 |
| Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.457849634 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2606385387 ps |
| CPU time | 700.62 seconds |
| Started | Feb 21 01:22:31 PM PST 24 |
| Finished | Feb 21 01:34:12 PM PST 24 |
| Peak memory | 362256 kb |
| Host | smart-4903679e-3f30-4c45-8a97-fc909cb62746 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457849634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.sram_ctrl_access_during_key_req.457849634 |
| Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.3423689574 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 32970214 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:22:23 PM PST 24 |
| Finished | Feb 21 01:22:24 PM PST 24 |
| Peak memory | 201776 kb |
| Host | smart-4fe369bd-e685-4bbb-8e0e-8c4ce1e9560b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423689574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.3423689574 |
| Directory | /workspace/46.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_bijection.3378743788 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1745993494 ps |
| CPU time | 31.27 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:22:59 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-5f03f822-e8c2-4f03-8563-909b3db56df3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378743788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .3378743788 |
| Directory | /workspace/46.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_executable.1287711541 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 719297350 ps |
| CPU time | 128.8 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:24:34 PM PST 24 |
| Peak memory | 323720 kb |
| Host | smart-c40f2acf-a317-4972-ac2b-0c7425dcf8d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287711541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.1287711541 |
| Directory | /workspace/46.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.1571797576 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1218716572 ps |
| CPU time | 9.29 seconds |
| Started | Feb 21 01:22:30 PM PST 24 |
| Finished | Feb 21 01:22:39 PM PST 24 |
| Peak memory | 213488 kb |
| Host | smart-7b22b0a8-3dea-4334-a68b-f9b942274b50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571797576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1571797576 |
| Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.3585487420 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1804643809 ps |
| CPU time | 159.56 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:25:08 PM PST 24 |
| Peak memory | 367304 kb |
| Host | smart-38622a15-bb05-42c5-b286-63648d3f7c7a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585487420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.3585487420 |
| Directory | /workspace/46.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1407589001 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 586039206 ps |
| CPU time | 4.92 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:22:32 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-31f9c8fe-6638-4c08-b0d4-f5f6bd1aef37 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407589001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1407589001 |
| Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.3348504935 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 137414877 ps |
| CPU time | 8.08 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:22:42 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-cddf78a7-7b9c-4fd8-a3ec-283542121cd9 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348504935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.3348504935 |
| Directory | /workspace/46.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.1670577348 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 27690461286 ps |
| CPU time | 291.13 seconds |
| Started | Feb 21 01:22:29 PM PST 24 |
| Finished | Feb 21 01:27:20 PM PST 24 |
| Peak memory | 321868 kb |
| Host | smart-7def94e4-97e7-4092-afdf-383d491d9604 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670577348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.1670577348 |
| Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.1541556104 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 209628485 ps |
| CPU time | 10.83 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:22:44 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-143b7385-6a34-4cc3-b73f-35f20ed7f3a8 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541556104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.1541556104 |
| Directory | /workspace/46.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4033263807 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 27828730187 ps |
| CPU time | 344.8 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:28:13 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-36811ed5-d6ee-42ac-95b9-78e134537254 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033263807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.4033263807 |
| Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.1330728807 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 29129920 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:22:29 PM PST 24 |
| Finished | Feb 21 01:22:30 PM PST 24 |
| Peak memory | 202892 kb |
| Host | smart-a3fa6bd5-6426-4340-8fcd-3aa906171173 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330728807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1330728807 |
| Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_regwen.586839695 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3002071330 ps |
| CPU time | 952.41 seconds |
| Started | Feb 21 01:22:30 PM PST 24 |
| Finished | Feb 21 01:38:23 PM PST 24 |
| Peak memory | 367036 kb |
| Host | smart-0ac8e29d-1798-4039-beca-f42af5f6938c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586839695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.586839695 |
| Directory | /workspace/46.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_smoke.1533660082 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 993320097 ps |
| CPU time | 15.27 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 01:22:42 PM PST 24 |
| Peak memory | 202680 kb |
| Host | smart-1b0fd1b1-09fe-412e-99f8-2582648ced80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533660082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1533660082 |
| Directory | /workspace/46.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.3334201214 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 35666236944 ps |
| CPU time | 3701.73 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 02:24:10 PM PST 24 |
| Peak memory | 375592 kb |
| Host | smart-ce71c20e-13e2-44aa-abff-c1f246000123 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334201214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.3334201214 |
| Directory | /workspace/46.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.926112070 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5247989476 ps |
| CPU time | 251.97 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:26:41 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-4df10291-5082-412b-ab9e-e1b6378e2c9d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926112070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_stress_pipeline.926112070 |
| Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1199739209 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 453061613 ps |
| CPU time | 19.94 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 01:22:46 PM PST 24 |
| Peak memory | 274032 kb |
| Host | smart-628fb1d7-296c-473f-9396-070e4bb8c863 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199739209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.1199739209 |
| Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1770273607 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3171109600 ps |
| CPU time | 458.75 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:30:04 PM PST 24 |
| Peak memory | 334656 kb |
| Host | smart-8e1c5272-81b1-447b-8c6a-c772b39881d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770273607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.1770273607 |
| Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.3654320672 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 16000576 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 01:22:31 PM PST 24 |
| Finished | Feb 21 01:22:32 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-fb920ed7-7e4f-4d4b-a30d-88dfcf58c6a8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654320672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3654320672 |
| Directory | /workspace/47.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_bijection.1481449532 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 25378353307 ps |
| CPU time | 67.26 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:23:35 PM PST 24 |
| Peak memory | 202796 kb |
| Host | smart-db4a117f-4cb3-4c2a-8ae4-9291fa6e66c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481449532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .1481449532 |
| Directory | /workspace/47.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_executable.674409096 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5735775057 ps |
| CPU time | 286.87 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 01:27:14 PM PST 24 |
| Peak memory | 355252 kb |
| Host | smart-0a8722f7-fe9b-4271-96e4-43598670681d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674409096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executabl e.674409096 |
| Directory | /workspace/47.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.1335902863 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1346679901 ps |
| CPU time | 6.18 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:22:40 PM PST 24 |
| Peak memory | 210880 kb |
| Host | smart-a1f6ca3a-24ff-47ff-b4b5-f446cadb9bec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335902863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.1335902863 |
| Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.2901864278 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 282824017 ps |
| CPU time | 15.76 seconds |
| Started | Feb 21 01:22:30 PM PST 24 |
| Finished | Feb 21 01:22:47 PM PST 24 |
| Peak memory | 260208 kb |
| Host | smart-9d9388b4-aa17-495e-9dad-1477a08c4e94 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901864278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.2901864278 |
| Directory | /workspace/47.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.681763537 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 171763003 ps |
| CPU time | 2.98 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:22:30 PM PST 24 |
| Peak memory | 215424 kb |
| Host | smart-f9f115ce-a221-4b25-afb1-3adfef366169 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681763537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.681763537 |
| Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.1645153652 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1823759856 ps |
| CPU time | 9.78 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:22:35 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-1fd3c7b8-0608-4955-9dbe-113161b3b70c |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645153652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.1645153652 |
| Directory | /workspace/47.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.2130098242 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 6947837462 ps |
| CPU time | 773.37 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:35:20 PM PST 24 |
| Peak memory | 363360 kb |
| Host | smart-d990839f-bf30-4637-ac18-43116f69a3c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130098242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.2130098242 |
| Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.756693533 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 903283868 ps |
| CPU time | 11.42 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:22:37 PM PST 24 |
| Peak memory | 243040 kb |
| Host | smart-42d968fa-020a-4ce3-a5af-8ed021672ebd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756693533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s ram_ctrl_partial_access.756693533 |
| Directory | /workspace/47.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3129644810 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 8049916637 ps |
| CPU time | 309.67 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:27:35 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-dc7088e4-b1a0-465f-98db-48ec94963b4f |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129644810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3129644810 |
| Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.1950798076 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 104763680 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 01:22:23 PM PST 24 |
| Finished | Feb 21 01:22:25 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-27c87dd1-aadc-4581-b33e-e4423c0c1ee9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950798076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1950798076 |
| Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_regwen.367215670 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2399849648 ps |
| CPU time | 1114.98 seconds |
| Started | Feb 21 01:22:25 PM PST 24 |
| Finished | Feb 21 01:41:01 PM PST 24 |
| Peak memory | 373368 kb |
| Host | smart-80321f2e-9267-49d2-8dec-36bbf5f83d60 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367215670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.367215670 |
| Directory | /workspace/47.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_smoke.3137740748 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 117778262 ps |
| CPU time | 88.51 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:23:56 PM PST 24 |
| Peak memory | 330016 kb |
| Host | smart-fcc1c0c4-2663-4fc3-b895-fe4085e5e2ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137740748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3137740748 |
| Directory | /workspace/47.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.1495164211 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 10655358934 ps |
| CPU time | 3632.78 seconds |
| Started | Feb 21 01:22:30 PM PST 24 |
| Finished | Feb 21 02:23:03 PM PST 24 |
| Peak memory | 382744 kb |
| Host | smart-42fd8404-2ae5-41e9-9780-b038bb4d30d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495164211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.1495164211 |
| Directory | /workspace/47.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3492194532 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4425451940 ps |
| CPU time | 122.29 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 01:24:28 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-78669e39-86bf-4429-8cdc-79ff9377d85e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492194532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3492194532 |
| Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1547401060 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1832096210 ps |
| CPU time | 108.52 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:24:17 PM PST 24 |
| Peak memory | 365580 kb |
| Host | smart-15088230-00c0-45de-b72e-ec0b13882840 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547401060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1547401060 |
| Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.667640240 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1108272919 ps |
| CPU time | 127.6 seconds |
| Started | Feb 21 01:22:35 PM PST 24 |
| Finished | Feb 21 01:24:43 PM PST 24 |
| Peak memory | 309352 kb |
| Host | smart-8315ee73-4828-4990-8c15-4dea5fea0ec8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667640240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 48.sram_ctrl_access_during_key_req.667640240 |
| Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.1580325957 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 19100815 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:22:31 PM PST 24 |
| Finished | Feb 21 01:22:32 PM PST 24 |
| Peak memory | 201616 kb |
| Host | smart-9cd2b919-7bb0-42df-a276-80359ebb3714 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580325957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1580325957 |
| Directory | /workspace/48.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_bijection.2329782799 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4212431057 ps |
| CPU time | 53.24 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:23:21 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-c05a306f-71c2-484c-a236-f763975d6d9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329782799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .2329782799 |
| Directory | /workspace/48.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_executable.314974965 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 25040016688 ps |
| CPU time | 751.74 seconds |
| Started | Feb 21 01:22:35 PM PST 24 |
| Finished | Feb 21 01:35:07 PM PST 24 |
| Peak memory | 369008 kb |
| Host | smart-27c85c12-6d45-4fe5-87bf-dacfe4dd4569 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314974965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl e.314974965 |
| Directory | /workspace/48.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.278747195 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1975658871 ps |
| CPU time | 6.82 seconds |
| Started | Feb 21 01:22:28 PM PST 24 |
| Finished | Feb 21 01:22:35 PM PST 24 |
| Peak memory | 210848 kb |
| Host | smart-3e12051e-8379-4b1f-9f88-39db62aa1d84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278747195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc alation.278747195 |
| Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.3271116888 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 150464612 ps |
| CPU time | 102.62 seconds |
| Started | Feb 21 01:22:35 PM PST 24 |
| Finished | Feb 21 01:24:18 PM PST 24 |
| Peak memory | 339560 kb |
| Host | smart-6a398801-dbfe-4c7f-a0e7-944ed4604bd4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271116888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.3271116888 |
| Directory | /workspace/48.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2340348576 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 688456896 ps |
| CPU time | 5.38 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:22:39 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-715d2283-6f73-4aaf-8217-1f05e95086a2 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340348576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2340348576 |
| Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.2284679102 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 6535071576 ps |
| CPU time | 9.94 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:22:43 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-d6887170-a942-4bf4-902b-85b5de904cad |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284679102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.2284679102 |
| Directory | /workspace/48.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.256446144 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 9695400527 ps |
| CPU time | 877.05 seconds |
| Started | Feb 21 01:22:29 PM PST 24 |
| Finished | Feb 21 01:37:07 PM PST 24 |
| Peak memory | 374880 kb |
| Host | smart-f307b851-b9ad-4e26-bf5a-433cafa08cc1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256446144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip le_keys.256446144 |
| Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.1033919504 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1452605808 ps |
| CPU time | 28.13 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:23:02 PM PST 24 |
| Peak memory | 291756 kb |
| Host | smart-34316b56-3eb0-45aa-a961-2294673aeb39 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033919504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1033919504 |
| Directory | /workspace/48.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3866152128 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 12347302309 ps |
| CPU time | 238.52 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:26:31 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-cfbf2dbe-65b6-4f2d-9beb-5b4b54580c15 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866152128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.3866152128 |
| Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_regwen.3119229530 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 34583944034 ps |
| CPU time | 563.54 seconds |
| Started | Feb 21 01:22:35 PM PST 24 |
| Finished | Feb 21 01:31:59 PM PST 24 |
| Peak memory | 356868 kb |
| Host | smart-51cae5d7-2e30-4174-9fca-a150daaff27d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119229530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3119229530 |
| Directory | /workspace/48.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_smoke.43671775 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1016282673 ps |
| CPU time | 2.16 seconds |
| Started | Feb 21 01:22:26 PM PST 24 |
| Finished | Feb 21 01:22:29 PM PST 24 |
| Peak memory | 202692 kb |
| Host | smart-223baeb5-6702-46a9-b10a-2001d34446d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43671775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.43671775 |
| Directory | /workspace/48.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.2604748875 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2808730613 ps |
| CPU time | 544.96 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:31:38 PM PST 24 |
| Peak memory | 345792 kb |
| Host | smart-2c0d817c-cb25-4d54-85b0-7ff8ba9caff2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604748875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.2604748875 |
| Directory | /workspace/48.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1097278681 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 4280282063 ps |
| CPU time | 228.74 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:26:22 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-a6ce24ff-a821-4376-994e-d20b86f319e4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097278681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1097278681 |
| Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.969147898 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 217583798 ps |
| CPU time | 38.66 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:23:11 PM PST 24 |
| Peak memory | 304896 kb |
| Host | smart-1a077b13-fda3-4bce-b28e-4de34460b59e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969147898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_throughput_w_partial_write.969147898 |
| Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1600172336 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 6982099825 ps |
| CPU time | 1265.48 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:43:39 PM PST 24 |
| Peak memory | 373528 kb |
| Host | smart-54f9f089-3441-4a31-9e00-8a1acd2a4ef2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600172336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.1600172336 |
| Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.186464731 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 17968390 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 01:22:35 PM PST 24 |
| Finished | Feb 21 01:22:36 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-bb430e6f-745f-4c5a-b7a0-a111ac428961 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186464731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.186464731 |
| Directory | /workspace/49.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_bijection.2281880394 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 849713068 ps |
| CPU time | 53.52 seconds |
| Started | Feb 21 01:22:31 PM PST 24 |
| Finished | Feb 21 01:23:25 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-6cea94ef-6184-4ec6-9da2-d648c939bb8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281880394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2281880394 |
| Directory | /workspace/49.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.3397858471 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 461407926 ps |
| CPU time | 5.7 seconds |
| Started | Feb 21 01:22:34 PM PST 24 |
| Finished | Feb 21 01:22:40 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-1bf0da60-ec6e-47d0-b773-a2483f41a5f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397858471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.3397858471 |
| Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.3122539619 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 75039639 ps |
| CPU time | 16.85 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:22:51 PM PST 24 |
| Peak memory | 267860 kb |
| Host | smart-eafebb3d-69dd-4c84-b6cf-0139c00ca7b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122539619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.3122539619 |
| Directory | /workspace/49.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3204144229 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 393402910 ps |
| CPU time | 5.16 seconds |
| Started | Feb 21 01:22:31 PM PST 24 |
| Finished | Feb 21 01:22:37 PM PST 24 |
| Peak memory | 211068 kb |
| Host | smart-b5542dd3-39be-43f5-aa0f-0e1a2092b303 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204144229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.3204144229 |
| Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.4072581081 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 275602088 ps |
| CPU time | 4.24 seconds |
| Started | Feb 21 01:22:35 PM PST 24 |
| Finished | Feb 21 01:22:40 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-fe61fe59-7e44-4719-a5e1-93ebe14d929b |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072581081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.4072581081 |
| Directory | /workspace/49.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.688611720 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 15770876532 ps |
| CPU time | 300.33 seconds |
| Started | Feb 21 01:22:27 PM PST 24 |
| Finished | Feb 21 01:27:28 PM PST 24 |
| Peak memory | 372136 kb |
| Host | smart-b3ec1144-b140-40d8-94d8-041cb41bef07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688611720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip le_keys.688611720 |
| Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.2750446430 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2094670400 ps |
| CPU time | 85.69 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:23:59 PM PST 24 |
| Peak memory | 327576 kb |
| Host | smart-cfe8bcae-4e28-4381-9cfd-afe6e33bec0e |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750446430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.2750446430 |
| Directory | /workspace/49.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1693991971 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 13615293112 ps |
| CPU time | 298.87 seconds |
| Started | Feb 21 01:22:30 PM PST 24 |
| Finished | Feb 21 01:27:30 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-793014c5-c7c6-4c3b-9604-05cd74d8fccd |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693991971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1693991971 |
| Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.717071417 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 48911621 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:22:37 PM PST 24 |
| Finished | Feb 21 01:22:40 PM PST 24 |
| Peak memory | 202868 kb |
| Host | smart-f8cc4823-7081-48b8-8d27-795106c8a6f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717071417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.717071417 |
| Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_regwen.50876879 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 119230646611 ps |
| CPU time | 1149.64 seconds |
| Started | Feb 21 01:22:31 PM PST 24 |
| Finished | Feb 21 01:41:41 PM PST 24 |
| Peak memory | 373748 kb |
| Host | smart-dc91444e-3f11-4f3e-9954-6faa41d90e96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50876879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.50876879 |
| Directory | /workspace/49.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_smoke.1660738344 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 105993494 ps |
| CPU time | 23.28 seconds |
| Started | Feb 21 01:22:32 PM PST 24 |
| Finished | Feb 21 01:22:55 PM PST 24 |
| Peak memory | 276680 kb |
| Host | smart-e186d39c-9520-4ca1-9a4f-804af4fc8c5a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660738344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1660738344 |
| Directory | /workspace/49.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.3210334346 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 78332850111 ps |
| CPU time | 1811.23 seconds |
| Started | Feb 21 01:22:36 PM PST 24 |
| Finished | Feb 21 01:52:47 PM PST 24 |
| Peak memory | 374584 kb |
| Host | smart-ec00ace1-5e10-44ee-b8ad-93ab3b048bf9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210334346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.3210334346 |
| Directory | /workspace/49.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1483946867 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4152079277 ps |
| CPU time | 213.09 seconds |
| Started | Feb 21 01:22:30 PM PST 24 |
| Finished | Feb 21 01:26:04 PM PST 24 |
| Peak memory | 202924 kb |
| Host | smart-b82e4b12-3b51-48a2-bf27-59afc206c3d2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483946867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.1483946867 |
| Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3108555423 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 115934881 ps |
| CPU time | 58.54 seconds |
| Started | Feb 21 01:22:33 PM PST 24 |
| Finished | Feb 21 01:23:32 PM PST 24 |
| Peak memory | 306008 kb |
| Host | smart-c279ecb7-ab07-43c6-84bf-6ebb25e281d2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108555423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3108555423 |
| Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.653804673 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 5277633893 ps |
| CPU time | 159.42 seconds |
| Started | Feb 21 01:18:56 PM PST 24 |
| Finished | Feb 21 01:21:35 PM PST 24 |
| Peak memory | 327628 kb |
| Host | smart-950fe468-d288-4441-8581-cba0e83310ff |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653804673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_access_during_key_req.653804673 |
| Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.3278652289 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 59037829 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:00 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-a54632d5-1fad-4255-a8d6-03b261cf7146 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278652289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3278652289 |
| Directory | /workspace/5.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_bijection.1322457134 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1742245918 ps |
| CPU time | 31.02 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:19:34 PM PST 24 |
| Peak memory | 202688 kb |
| Host | smart-39fa0db3-4e26-4882-851f-a13f5e19c75b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322457134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 1322457134 |
| Directory | /workspace/5.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_executable.1134106931 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2757144688 ps |
| CPU time | 791.5 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:32:13 PM PST 24 |
| Peak memory | 373508 kb |
| Host | smart-a791dabb-47f1-4f9f-8772-961d9635becb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134106931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.1134106931 |
| Directory | /workspace/5.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.384842092 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 920232037 ps |
| CPU time | 9.12 seconds |
| Started | Feb 21 01:19:04 PM PST 24 |
| Finished | Feb 21 01:19:13 PM PST 24 |
| Peak memory | 210880 kb |
| Host | smart-bcee6903-767a-452f-9aff-795341a73e6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384842092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca lation.384842092 |
| Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.127332146 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 389480295 ps |
| CPU time | 38.11 seconds |
| Started | Feb 21 01:18:44 PM PST 24 |
| Finished | Feb 21 01:19:23 PM PST 24 |
| Peak memory | 300312 kb |
| Host | smart-7f732e4d-242f-4067-8bf8-b6b77ff028b0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127332146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.127332146 |
| Directory | /workspace/5.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3125406707 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 96878812 ps |
| CPU time | 2.89 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:03 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-facb8d6e-0c22-4b52-96f9-757bc0690e71 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125406707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.3125406707 |
| Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.2629277913 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 451663425 ps |
| CPU time | 8.92 seconds |
| Started | Feb 21 01:18:56 PM PST 24 |
| Finished | Feb 21 01:19:05 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-aee63550-0844-4839-a9a0-b26070a2aa84 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629277913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.2629277913 |
| Directory | /workspace/5.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.513471842 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 8478182391 ps |
| CPU time | 1016.9 seconds |
| Started | Feb 21 01:18:43 PM PST 24 |
| Finished | Feb 21 01:35:40 PM PST 24 |
| Peak memory | 371660 kb |
| Host | smart-99ef4570-1445-4363-a81f-04f5fd0328d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513471842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl e_keys.513471842 |
| Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.668959288 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 350188880 ps |
| CPU time | 17.05 seconds |
| Started | Feb 21 01:18:44 PM PST 24 |
| Finished | Feb 21 01:19:01 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-aad36821-52bc-4daa-b036-a549bcc29398 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668959288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr am_ctrl_partial_access.668959288 |
| Directory | /workspace/5.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1615510830 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 53694235224 ps |
| CPU time | 330.33 seconds |
| Started | Feb 21 01:19:04 PM PST 24 |
| Finished | Feb 21 01:24:35 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-bfe8ae92-4bf9-48d3-8110-badddc0e1f67 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615510830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1615510830 |
| Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.4100051857 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 53773741 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:00 PM PST 24 |
| Peak memory | 202872 kb |
| Host | smart-d4868228-bb4b-42de-a313-df55231de77e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100051857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.4100051857 |
| Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_regwen.2407265585 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 28009092993 ps |
| CPU time | 1458.79 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:43:21 PM PST 24 |
| Peak memory | 375600 kb |
| Host | smart-561a0c4d-368f-437c-aa27-9aaec83d063e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407265585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2407265585 |
| Directory | /workspace/5.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_smoke.2127199645 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 490225381 ps |
| CPU time | 7.1 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:19:05 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-fe4acede-744c-479b-bde3-133a6d77389d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127199645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2127199645 |
| Directory | /workspace/5.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.3325047718 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3322544276 ps |
| CPU time | 782.5 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:32:00 PM PST 24 |
| Peak memory | 374472 kb |
| Host | smart-b46ad2ef-916a-45f6-96e8-cf72916a476c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325047718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3325047718 |
| Directory | /workspace/5.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.39374856 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 4416421780 ps |
| CPU time | 403.73 seconds |
| Started | Feb 21 01:18:44 PM PST 24 |
| Finished | Feb 21 01:25:28 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-78e08ac1-7763-487e-a50d-1b47229886fb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_stress_pipeline.39374856 |
| Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1509912154 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 266512476 ps |
| CPU time | 9.52 seconds |
| Started | Feb 21 01:18:41 PM PST 24 |
| Finished | Feb 21 01:18:50 PM PST 24 |
| Peak memory | 241968 kb |
| Host | smart-6781fb19-3d66-40a1-bd8a-30c3f422e58d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509912154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1509912154 |
| Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1065795668 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 602963796 ps |
| CPU time | 327.33 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:24:30 PM PST 24 |
| Peak memory | 359192 kb |
| Host | smart-f94f6afe-0750-4fc6-b998-03532d52a450 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065795668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1065795668 |
| Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.1325691659 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 15806892 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:19:02 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-0325a066-3275-42bb-a3ba-bd3fe4952ae3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325691659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1325691659 |
| Directory | /workspace/6.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_bijection.3309284243 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1064815846 ps |
| CPU time | 63.54 seconds |
| Started | Feb 21 01:19:01 PM PST 24 |
| Finished | Feb 21 01:20:07 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-021677c8-4c0c-4ac8-921e-d5262714ef79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309284243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 3309284243 |
| Directory | /workspace/6.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_executable.382033729 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 6092242309 ps |
| CPU time | 619.55 seconds |
| Started | Feb 21 01:19:14 PM PST 24 |
| Finished | Feb 21 01:29:34 PM PST 24 |
| Peak memory | 367412 kb |
| Host | smart-4436e1d3-76ce-45b7-a347-d15778a0b51f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382033729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable .382033729 |
| Directory | /workspace/6.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.935979267 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1046499926 ps |
| CPU time | 7.2 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:08 PM PST 24 |
| Peak memory | 211040 kb |
| Host | smart-aa619d67-46c5-470c-b28c-260f43bb3a3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935979267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca lation.935979267 |
| Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.870263516 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 148117856 ps |
| CPU time | 52.58 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:53 PM PST 24 |
| Peak memory | 312400 kb |
| Host | smart-c8d2cb1e-4b31-4576-9cf5-6414023dea46 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870263516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.sram_ctrl_max_throughput.870263516 |
| Directory | /workspace/6.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4249307073 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2279160979 ps |
| CPU time | 6.04 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:06 PM PST 24 |
| Peak memory | 216028 kb |
| Host | smart-a29a3685-e4c2-4907-8613-a5be1207b001 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249307073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.4249307073 |
| Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.1130791373 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 519384699 ps |
| CPU time | 8.23 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:19:12 PM PST 24 |
| Peak memory | 202632 kb |
| Host | smart-08986592-1854-4bf3-81e0-d0a9fbd4b8fe |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130791373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.1130791373 |
| Directory | /workspace/6.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.3203467579 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 15508185587 ps |
| CPU time | 942.73 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:34:45 PM PST 24 |
| Peak memory | 365360 kb |
| Host | smart-0fa00a91-9cdd-4da9-9546-cd1d98b9d16b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203467579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.3203467579 |
| Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.458388820 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1830381920 ps |
| CPU time | 16.84 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:19:18 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-0afe03c6-f375-4562-9432-4c5f07e73874 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458388820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr am_ctrl_partial_access.458388820 |
| Directory | /workspace/6.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.725044877 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 27399881562 ps |
| CPU time | 340.84 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:24:42 PM PST 24 |
| Peak memory | 202780 kb |
| Host | smart-44c902b0-0927-47d5-bafd-c7b6ea6172fb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725044877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.sram_ctrl_partial_access_b2b.725044877 |
| Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.2827747270 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 376702745 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 01:19:17 PM PST 24 |
| Peak memory | 202900 kb |
| Host | smart-ada288a2-faff-4238-9297-58500b2378c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827747270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2827747270 |
| Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2815582547 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 821279445 ps |
| CPU time | 274.13 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:23:54 PM PST 24 |
| Peak memory | 351596 kb |
| Host | smart-3292ef0a-6d39-46d3-9fef-f365eeaf2c91 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815582547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2815582547 |
| Directory | /workspace/6.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_smoke.3777844848 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 711007570 ps |
| CPU time | 11.38 seconds |
| Started | Feb 21 01:19:04 PM PST 24 |
| Finished | Feb 21 01:19:16 PM PST 24 |
| Peak memory | 202056 kb |
| Host | smart-cfcfc729-b3d4-4fda-ae10-36313ab45940 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777844848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3777844848 |
| Directory | /workspace/6.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.3189948265 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 77803666052 ps |
| CPU time | 807.81 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:32:28 PM PST 24 |
| Peak memory | 382716 kb |
| Host | smart-1aff3ce2-1c88-40f6-8273-ad5de1288b3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189948265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.3189948265 |
| Directory | /workspace/6.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.773910728 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 9601621337 ps |
| CPU time | 287.75 seconds |
| Started | Feb 21 01:19:02 PM PST 24 |
| Finished | Feb 21 01:23:51 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-81853c40-6ff8-4a2f-b1ac-e09695cf3765 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773910728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_stress_pipeline.773910728 |
| Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3538080296 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 126381767 ps |
| CPU time | 78.67 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:20:20 PM PST 24 |
| Peak memory | 336012 kb |
| Host | smart-096827cd-cabb-4bda-a5f9-96515828dc8d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538080296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3538080296 |
| Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2618480283 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 5634415187 ps |
| CPU time | 813.88 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:32:33 PM PST 24 |
| Peak memory | 372020 kb |
| Host | smart-be8d083b-ac3c-449a-a05f-a12599dfd119 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618480283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.2618480283 |
| Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.730350428 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 14102334 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:19:25 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-89969bb6-8e63-488e-b755-48a604d65503 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730350428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.730350428 |
| Directory | /workspace/7.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_bijection.932180811 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6904646890 ps |
| CPU time | 25.59 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:19:29 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-281a8b87-7e07-45ff-9119-5ea4d3e93d0d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932180811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.932180811 |
| Directory | /workspace/7.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_executable.3856336912 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 16177893414 ps |
| CPU time | 711.04 seconds |
| Started | Feb 21 01:19:12 PM PST 24 |
| Finished | Feb 21 01:31:04 PM PST 24 |
| Peak memory | 377628 kb |
| Host | smart-698bdfc8-f0dc-4f6e-a778-e82dbf1f2c4b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856336912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.3856336912 |
| Directory | /workspace/7.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.3913840416 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 451283310 ps |
| CPU time | 6.95 seconds |
| Started | Feb 21 01:19:12 PM PST 24 |
| Finished | Feb 21 01:19:19 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-472cda2d-6faa-4ecf-ba57-c66fbbe3353d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913840416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.3913840416 |
| Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.2080236870 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 541381930 ps |
| CPU time | 97.86 seconds |
| Started | Feb 21 01:19:02 PM PST 24 |
| Finished | Feb 21 01:20:42 PM PST 24 |
| Peak memory | 366684 kb |
| Host | smart-16c821f5-a1a4-409b-aefc-0e86c95b9427 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080236870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2080236870 |
| Directory | /workspace/7.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2734890761 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 586781860 ps |
| CPU time | 5.37 seconds |
| Started | Feb 21 01:19:04 PM PST 24 |
| Finished | Feb 21 01:19:10 PM PST 24 |
| Peak memory | 210836 kb |
| Host | smart-93a3c90e-d334-4f6c-8079-248db917ab88 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734890761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.2734890761 |
| Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.100944658 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 880211029 ps |
| CPU time | 8.79 seconds |
| Started | Feb 21 01:19:39 PM PST 24 |
| Finished | Feb 21 01:19:49 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-48de4891-2422-4084-a993-af40f6049e95 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100944658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ mem_walk.100944658 |
| Directory | /workspace/7.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.4044079934 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 41403376596 ps |
| CPU time | 676.59 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:30:18 PM PST 24 |
| Peak memory | 360268 kb |
| Host | smart-c4ed840e-6775-4d0d-8328-5a86ec01403a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044079934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.4044079934 |
| Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.2866220293 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 500318005 ps |
| CPU time | 7.78 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:19:07 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-8ceff914-946b-45e7-a899-fa6df4525cca |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866220293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.2866220293 |
| Directory | /workspace/7.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.894813109 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 90355389576 ps |
| CPU time | 397.95 seconds |
| Started | Feb 21 01:19:20 PM PST 24 |
| Finished | Feb 21 01:26:01 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-fa75c4e1-6086-4c1c-b5f4-893980a35ca1 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894813109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.sram_ctrl_partial_access_b2b.894813109 |
| Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.984712610 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 90112959 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 01:19:17 PM PST 24 |
| Peak memory | 202896 kb |
| Host | smart-e902e9ab-8585-4ad5-b5f5-a204fa1ac209 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984712610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.984712610 |
| Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_regwen.3563889851 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3533248477 ps |
| CPU time | 279.41 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:23:41 PM PST 24 |
| Peak memory | 367992 kb |
| Host | smart-bb9e6cfc-4af3-4334-bdd7-b12bdf1d74e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563889851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3563889851 |
| Directory | /workspace/7.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_smoke.600036389 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1492313521 ps |
| CPU time | 4.91 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:19:07 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-bfc46ac6-45da-459a-aaec-5e0392cb9ff0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600036389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.600036389 |
| Directory | /workspace/7.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.1139808060 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 12288318460 ps |
| CPU time | 3079.19 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 02:10:35 PM PST 24 |
| Peak memory | 375556 kb |
| Host | smart-921409de-b794-49db-a976-a6aa1c3ae0e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139808060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.1139808060 |
| Directory | /workspace/7.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4041658303 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2054560927 ps |
| CPU time | 198.44 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:22:23 PM PST 24 |
| Peak memory | 202640 kb |
| Host | smart-b494adf8-6c08-48dc-a709-b63a027b6788 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041658303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.4041658303 |
| Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4078734113 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 278034081 ps |
| CPU time | 11.43 seconds |
| Started | Feb 21 01:19:26 PM PST 24 |
| Finished | Feb 21 01:19:38 PM PST 24 |
| Peak memory | 251712 kb |
| Host | smart-4825f93a-3d36-4f0d-8a31-9a395e6d8576 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078734113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.4078734113 |
| Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.156406865 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2156611737 ps |
| CPU time | 563.03 seconds |
| Started | Feb 21 01:19:30 PM PST 24 |
| Finished | Feb 21 01:28:53 PM PST 24 |
| Peak memory | 369564 kb |
| Host | smart-f6c98eca-e322-4506-a0b3-4c4422004eb7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156406865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_access_during_key_req.156406865 |
| Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.2141429758 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 29620939 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 01:19:17 PM PST 24 |
| Finished | Feb 21 01:19:18 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-ed09fb74-5b56-44d2-816d-eedf9c5fbc6e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141429758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2141429758 |
| Directory | /workspace/8.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_bijection.1695662326 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4180080338 ps |
| CPU time | 30.04 seconds |
| Started | Feb 21 01:19:16 PM PST 24 |
| Finished | Feb 21 01:19:47 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-6380b613-38fc-47c8-bcd5-fcb859601f02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695662326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 1695662326 |
| Directory | /workspace/8.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_executable.488563283 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2654315660 ps |
| CPU time | 154.74 seconds |
| Started | Feb 21 01:18:59 PM PST 24 |
| Finished | Feb 21 01:21:34 PM PST 24 |
| Peak memory | 365432 kb |
| Host | smart-873e19b0-49a6-47c4-b8c2-79a1a65cec00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488563283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable .488563283 |
| Directory | /workspace/8.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.2189070225 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 567151815 ps |
| CPU time | 7.1 seconds |
| Started | Feb 21 01:19:45 PM PST 24 |
| Finished | Feb 21 01:19:53 PM PST 24 |
| Peak memory | 210876 kb |
| Host | smart-e1403060-9f31-455b-9261-4f65701c2be4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189070225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.2189070225 |
| Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.762405060 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 127632446 ps |
| CPU time | 77.8 seconds |
| Started | Feb 21 01:19:23 PM PST 24 |
| Finished | Feb 21 01:20:42 PM PST 24 |
| Peak memory | 341112 kb |
| Host | smart-0888c525-0113-4894-b83e-a19e3eafe881 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762405060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.sram_ctrl_max_throughput.762405060 |
| Directory | /workspace/8.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1043557476 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 234726889 ps |
| CPU time | 4.81 seconds |
| Started | Feb 21 01:19:16 PM PST 24 |
| Finished | Feb 21 01:19:21 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-7c040725-e3c2-4836-abcb-e8a7b51fe731 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043557476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1043557476 |
| Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.3639126257 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 76634257 ps |
| CPU time | 4.33 seconds |
| Started | Feb 21 01:19:02 PM PST 24 |
| Finished | Feb 21 01:19:08 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-1afb7c12-92f9-41af-9936-6f60917544b3 |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639126257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.3639126257 |
| Directory | /workspace/8.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.617995788 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1523652642 ps |
| CPU time | 291.86 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:23:50 PM PST 24 |
| Peak memory | 357268 kb |
| Host | smart-f1b1114f-1204-42a2-ba2c-523724a614df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617995788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl e_keys.617995788 |
| Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.1264945176 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 158561726 ps |
| CPU time | 7.91 seconds |
| Started | Feb 21 01:19:28 PM PST 24 |
| Finished | Feb 21 01:19:37 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-d83024a5-3ced-4c06-b1be-e60a41ef642b |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264945176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.1264945176 |
| Directory | /workspace/8.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.137614231 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 27429965457 ps |
| CPU time | 334.51 seconds |
| Started | Feb 21 01:18:58 PM PST 24 |
| Finished | Feb 21 01:24:32 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-c37e2cb7-559c-48ab-aacc-63e2953111fb |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137614231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.sram_ctrl_partial_access_b2b.137614231 |
| Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.665734243 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 84579985 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:19:20 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-85aeeffb-675c-47cf-a67c-7f11a2d38606 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665734243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.665734243 |
| Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_regwen.2322196945 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2984565821 ps |
| CPU time | 694.06 seconds |
| Started | Feb 21 01:19:30 PM PST 24 |
| Finished | Feb 21 01:31:05 PM PST 24 |
| Peak memory | 367444 kb |
| Host | smart-b8b0b45c-f000-4c37-bb80-ae50efee30fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322196945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2322196945 |
| Directory | /workspace/8.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_smoke.3204419088 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1461507169 ps |
| CPU time | 131.83 seconds |
| Started | Feb 21 01:19:00 PM PST 24 |
| Finished | Feb 21 01:21:14 PM PST 24 |
| Peak memory | 368664 kb |
| Host | smart-b94a6f8b-c45c-432b-b9bf-4fa5203ab182 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204419088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3204419088 |
| Directory | /workspace/8.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.782069576 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 63830339101 ps |
| CPU time | 4177.31 seconds |
| Started | Feb 21 01:19:02 PM PST 24 |
| Finished | Feb 21 02:28:41 PM PST 24 |
| Peak memory | 383132 kb |
| Host | smart-bcc57aa5-dd9e-4676-b533-b5b42e3caf6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782069576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_stress_all.782069576 |
| Directory | /workspace/8.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1583383500 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 7611543192 ps |
| CPU time | 180.85 seconds |
| Started | Feb 21 01:19:12 PM PST 24 |
| Finished | Feb 21 01:22:14 PM PST 24 |
| Peak memory | 202792 kb |
| Host | smart-52a3fc67-0987-4de7-8dcf-0865efb4bf08 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583383500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.1583383500 |
| Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3420665958 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 151363727 ps |
| CPU time | 121.3 seconds |
| Started | Feb 21 01:19:04 PM PST 24 |
| Finished | Feb 21 01:21:06 PM PST 24 |
| Peak memory | 362928 kb |
| Host | smart-0694e056-4d2b-4d7e-ae7b-cf366c2e0f0a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420665958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3420665958 |
| Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3689959911 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5833355459 ps |
| CPU time | 1190.5 seconds |
| Started | Feb 21 01:19:14 PM PST 24 |
| Finished | Feb 21 01:39:05 PM PST 24 |
| Peak memory | 374468 kb |
| Host | smart-1fdfbce3-7311-4335-8f76-bb06e6199df7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689959911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3689959911 |
| Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.2280378924 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 32295010 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 01:19:08 PM PST 24 |
| Finished | Feb 21 01:19:09 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-c64195ed-8c67-4fb4-aead-c3017f962b4f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280378924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2280378924 |
| Directory | /workspace/9.sram_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_bijection.1832242257 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3692726896 ps |
| CPU time | 53.49 seconds |
| Started | Feb 21 01:19:12 PM PST 24 |
| Finished | Feb 21 01:20:06 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-9fd00296-07c0-4b13-8bd3-c13f1f623d2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832242257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 1832242257 |
| Directory | /workspace/9.sram_ctrl_bijection/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_executable.1208133925 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1551695789 ps |
| CPU time | 387.41 seconds |
| Started | Feb 21 01:19:13 PM PST 24 |
| Finished | Feb 21 01:25:41 PM PST 24 |
| Peak memory | 337512 kb |
| Host | smart-62cc7d84-fe19-4899-b02f-550bafe24de9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208133925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1208133925 |
| Directory | /workspace/9.sram_ctrl_executable/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.2003718684 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2479443273 ps |
| CPU time | 7.77 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:19:12 PM PST 24 |
| Peak memory | 213812 kb |
| Host | smart-9593bac8-ef7b-4c9d-b9e6-b7f18be89926 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003718684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.2003718684 |
| Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.4076220115 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 361234622 ps |
| CPU time | 45.8 seconds |
| Started | Feb 21 01:19:18 PM PST 24 |
| Finished | Feb 21 01:20:04 PM PST 24 |
| Peak memory | 302424 kb |
| Host | smart-90ed15c0-b7fe-483e-8ad5-226d0f7485aa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076220115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.4076220115 |
| Directory | /workspace/9.sram_ctrl_max_throughput/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1493399291 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 66627915 ps |
| CPU time | 4.42 seconds |
| Started | Feb 21 01:19:20 PM PST 24 |
| Finished | Feb 21 01:19:26 PM PST 24 |
| Peak memory | 210844 kb |
| Host | smart-1940cd6e-5377-4d37-a018-057e3fb297a5 |
| User | root |
| Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493399291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1493399291 |
| Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.3431822476 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 453646499 ps |
| CPU time | 5.17 seconds |
| Started | Feb 21 01:19:03 PM PST 24 |
| Finished | Feb 21 01:19:09 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-07e7d96c-c557-42b7-a8d3-f3e5c9cbe7cf |
| User | root |
| Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431822476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3431822476 |
| Directory | /workspace/9.sram_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.2005096947 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 50227652984 ps |
| CPU time | 1147.61 seconds |
| Started | Feb 21 01:19:14 PM PST 24 |
| Finished | Feb 21 01:38:22 PM PST 24 |
| Peak memory | 375016 kb |
| Host | smart-8e0dd8e9-b47c-44be-962e-b7ad29b62b21 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005096947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.2005096947 |
| Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.1425119194 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 2862492884 ps |
| CPU time | 68.38 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 01:20:24 PM PST 24 |
| Peak memory | 319004 kb |
| Host | smart-a197e3eb-1c30-464e-bf8e-4e7393fda6d5 |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425119194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.1425119194 |
| Directory | /workspace/9.sram_ctrl_partial_access/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3886460631 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 30483891386 ps |
| CPU time | 343.47 seconds |
| Started | Feb 21 01:19:14 PM PST 24 |
| Finished | Feb 21 01:24:58 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-7a145d29-fb70-4d4a-815c-a796bc1082ca |
| User | root |
| Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886460631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.3886460631 |
| Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.710899625 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 32056710 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 01:19:05 PM PST 24 |
| Finished | Feb 21 01:19:06 PM PST 24 |
| Peak memory | 202860 kb |
| Host | smart-5e3c129b-0e3c-4ff4-a590-047677812eb7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710899625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.710899625 |
| Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_regwen.1578319951 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 8081202692 ps |
| CPU time | 609.13 seconds |
| Started | Feb 21 01:19:19 PM PST 24 |
| Finished | Feb 21 01:29:29 PM PST 24 |
| Peak memory | 367184 kb |
| Host | smart-8c1ea250-619e-4ac5-bb24-06b641b69716 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578319951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1578319951 |
| Directory | /workspace/9.sram_ctrl_regwen/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_smoke.3236549291 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 287012741 ps |
| CPU time | 4.4 seconds |
| Started | Feb 21 01:19:15 PM PST 24 |
| Finished | Feb 21 01:19:20 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-fd238f9c-65af-422a-89a8-3b538daa8347 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236549291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3236549291 |
| Directory | /workspace/9.sram_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.1174704137 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 92786732190 ps |
| CPU time | 1026.15 seconds |
| Started | Feb 21 01:19:16 PM PST 24 |
| Finished | Feb 21 01:36:23 PM PST 24 |
| Peak memory | 367444 kb |
| Host | smart-0e8a8c45-abdb-4c18-853c-3646548216f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174704137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.1174704137 |
| Directory | /workspace/9.sram_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.37675026 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 5572199549 ps |
| CPU time | 264.74 seconds |
| Started | Feb 21 01:19:16 PM PST 24 |
| Finished | Feb 21 01:23:41 PM PST 24 |
| Peak memory | 202800 kb |
| Host | smart-d48dbd73-858e-4c7c-b3f2-c3d9debe454c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37675026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_stress_pipeline.37675026 |
| Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2635230683 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 119769998 ps |
| CPU time | 61.75 seconds |
| Started | Feb 21 01:19:13 PM PST 24 |
| Finished | Feb 21 01:20:15 PM PST 24 |
| Peak memory | 325308 kb |
| Host | smart-9a49d6a1-e94d-4429-9bd6-76336c6a7286 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635230683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2635230683 |
| Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |