Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	144829540	1			T1	77824		T2	1924		T3	68510
instr_valid_dis	110105486	1			T1	77824		T2	1924		T3	34974
instr_en	27063633	1			T3	5848		T10	552376		T6	75186

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11230978	1			T3	19260		T10	192070		T6	136238
sram_ifetch_valid_disable	111561486	1			T1	77824		T2	1924		T3	15714
sram_ifetch_enable	22037076	1			T3	33536		T10	140688		T6	52596

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	144829540	1			T1	77824		T2	1924		T3	68510
hw_debug_en_valid_off	112120446	1			T1	77824		T2	1924		T4	9312
hw_debug_en_on	22320434	1			T3	40822		T10	351776		T6	115226

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111561486	1			T1	77824		T2	1924		T3	15714
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97933468	1			T1	77824		T2	1924		T3	15714
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10401487	1			T10	338092		T6	524		T38	118818
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4424170	1			T10	99438		T6	99354		T13	35708
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1601494	1			T10	26778		T6	13622		T13	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2182212	1			T10	53156		T6	60086		T13	15708
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4569474	1			T3	19260		T10	92632		T6	34826
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1577658	1			T3	19260		T10	16346		T6	34826
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2455450	1			T10	76286		T38	29466		T13	14714
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8410802	1			T3	15714		T10	183016		T6	80400
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3111562	1			T3	15714		T10	55238		T6	64304
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4152570	1			T10	127778		T6	524		T38	98852

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10718472	1			T3	5848		T10	84842		T6	14576
lc_exec_en	9340158	1			T3	5848		T10	76128		T13	70440
valid_exec_dis	106968194	1			T1	77824		T2	1924		T4	9312
invalid_exec_dis	33268054	1			T3	52796		T10	332758		T6	188834