Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151363040	1			T1	319078		T2	65536		T3	8154
instr_valid_dis	111388025	1			T1	319078		T2	65536		T3	8154
instr_en	27557902	1			T5	90242		T9	383512		T12	40

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12159924	1			T5	102698		T9	80842		T12	28072
sram_ifetch_valid_disable	115804788	1			T1	319078		T2	65536		T3	8154
sram_ifetch_enable	23398328	1			T5	76802		T9	104666		T12	40

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151363040	1			T1	319078		T2	65536		T3	8154
hw_debug_en_valid_off	117066304	1			T1	319078		T2	65536		T3	8154
hw_debug_en_on	22727216	1			T5	153000		T9	309884		T18	188236

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115804788	1			T1	319078		T2	65536		T3	8154
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100492323	1			T1	319078		T2	65536		T3	8154
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10697174	1			T5	49056		T9	198004		T38	46356
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5308032	1			T5	12326		T12	28072		T18	107654
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1394354	1			T12	28072		T106	23774		T112	33706
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2509198	1			T5	12326		T104	11788		T23	11840
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4738498	1			T5	57224		T9	80842		T18	125498
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1757836	1			T5	57224		T106	43528		T94	53672
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1985012	1			T9	80842		T38	23604		T23	97588
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10026222	1			T5	62108		T9	198004		T18	16356
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3591682	1			T5	14490		T105	16538		T111	27220
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4464254	1			T5	47618		T9	198004		T38	8826

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11476620	1			T5	28860		T9	104666		T12	40
lc_exec_en	7962496	1			T5	33668		T9	31038		T18	46382
valid_exec_dis	108371962	1			T1	319078		T2	65536		T3	8154
invalid_exec_dis	35558252	1			T5	179500		T9	185508		T12	28112