Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45085081	1			T1	145112		T2	32768		T3	1368
triple_byte_access	2592370	1			T1	2864		T3	26		T4	6
halfword_access	3887088	1			T1	4343		T3	36		T4	8
byte_access	5193740	1			T1	5808		T3	55		T4	10
zero_access	1306504	1			T1	1412		T3	19		T4	2

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28987421

1

T1

79568

T2

16384

T3

746

auto[1]

29077362

1

T1

79971

T2

16384

T3

758

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22502099	1			T1	72458		T2	16384		T3	680
auto[0]	triple_byte_access	1293177	1			T1	1398		T3	13		T4	5
auto[0]	halfword_access	1940622	1			T1	2154		T3	17		T4	7
auto[0]	byte_access	2594355	1			T1	2864		T3	23		T4	6
auto[0]	zero_access	657168	1			T1	694		T3	13		T4	1
auto[1]	word_access	22582982	1			T1	72654		T2	16384		T3	688
auto[1]	triple_byte_access	1299193	1			T1	1466		T3	13		T4	1
auto[1]	halfword_access	1946466	1			T1	2189		T3	19		T4	1
auto[1]	byte_access	2599385	1			T1	2944		T3	32		T4	4
auto[1]	zero_access	649336	1			T1	718		T3	6		T4	1