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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 100.00 97.48 100.00 100.00 99.14 99.70 98.52


Total test records in report: 957
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T800 /workspace/coverage/default/6.sram_ctrl_alert_test.2249519096 Feb 29 02:21:26 PM PST 24 Feb 29 02:21:27 PM PST 24 32408557 ps
T801 /workspace/coverage/default/37.sram_ctrl_ram_cfg.2355922323 Feb 29 02:26:01 PM PST 24 Feb 29 02:26:03 PM PST 24 30440603 ps
T802 /workspace/coverage/default/42.sram_ctrl_mem_walk.1069800811 Feb 29 02:27:23 PM PST 24 Feb 29 02:27:32 PM PST 24 267131085 ps
T803 /workspace/coverage/default/44.sram_ctrl_mem_walk.3653810748 Feb 29 02:27:33 PM PST 24 Feb 29 02:27:43 PM PST 24 457839238 ps
T804 /workspace/coverage/default/45.sram_ctrl_ram_cfg.2902510798 Feb 29 02:27:45 PM PST 24 Feb 29 02:27:46 PM PST 24 27793517 ps
T805 /workspace/coverage/default/48.sram_ctrl_multiple_keys.927457391 Feb 29 02:28:27 PM PST 24 Feb 29 02:36:42 PM PST 24 11884434226 ps
T806 /workspace/coverage/default/44.sram_ctrl_lc_escalation.2044251511 Feb 29 02:27:31 PM PST 24 Feb 29 02:27:41 PM PST 24 422561199 ps
T807 /workspace/coverage/default/14.sram_ctrl_smoke.1774837773 Feb 29 02:22:00 PM PST 24 Feb 29 02:22:04 PM PST 24 105607278 ps
T808 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2188114810 Feb 29 02:22:51 PM PST 24 Feb 29 02:46:25 PM PST 24 4531164619 ps
T809 /workspace/coverage/default/24.sram_ctrl_mem_walk.503218168 Feb 29 02:23:37 PM PST 24 Feb 29 02:23:42 PM PST 24 228210008 ps
T810 /workspace/coverage/default/43.sram_ctrl_ram_cfg.3301350253 Feb 29 02:27:25 PM PST 24 Feb 29 02:27:27 PM PST 24 32999760 ps
T811 /workspace/coverage/default/0.sram_ctrl_alert_test.4164854225 Feb 29 02:20:54 PM PST 24 Feb 29 02:20:55 PM PST 24 21424097 ps
T812 /workspace/coverage/default/33.sram_ctrl_multiple_keys.1951909294 Feb 29 02:24:58 PM PST 24 Feb 29 02:25:20 PM PST 24 1488608942 ps
T35 /workspace/coverage/default/2.sram_ctrl_sec_cm.2096877831 Feb 29 02:21:10 PM PST 24 Feb 29 02:21:12 PM PST 24 203145654 ps
T813 /workspace/coverage/default/43.sram_ctrl_alert_test.148245090 Feb 29 02:27:25 PM PST 24 Feb 29 02:27:25 PM PST 24 17703135 ps
T814 /workspace/coverage/default/14.sram_ctrl_max_throughput.158950425 Feb 29 02:22:03 PM PST 24 Feb 29 02:22:09 PM PST 24 97177714 ps
T815 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2807500874 Feb 29 02:27:24 PM PST 24 Feb 29 02:29:24 PM PST 24 541386737 ps
T816 /workspace/coverage/default/38.sram_ctrl_mem_walk.2936379929 Feb 29 02:26:11 PM PST 24 Feb 29 02:26:22 PM PST 24 1748000630 ps
T817 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3564077161 Feb 29 02:25:29 PM PST 24 Feb 29 02:25:31 PM PST 24 27629958 ps
T818 /workspace/coverage/default/22.sram_ctrl_max_throughput.3271891232 Feb 29 02:23:09 PM PST 24 Feb 29 02:25:23 PM PST 24 141057116 ps
T819 /workspace/coverage/default/32.sram_ctrl_multiple_keys.745878363 Feb 29 02:24:46 PM PST 24 Feb 29 02:27:59 PM PST 24 6340608655 ps
T820 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1221165182 Feb 29 02:22:23 PM PST 24 Feb 29 02:22:29 PM PST 24 940702222 ps
T821 /workspace/coverage/default/34.sram_ctrl_bijection.3866338986 Feb 29 02:25:15 PM PST 24 Feb 29 02:26:15 PM PST 24 1929163797 ps
T822 /workspace/coverage/default/16.sram_ctrl_max_throughput.2349527393 Feb 29 02:22:11 PM PST 24 Feb 29 02:23:26 PM PST 24 216837656 ps
T823 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3254037087 Feb 29 02:22:10 PM PST 24 Feb 29 02:22:11 PM PST 24 162275936 ps
T824 /workspace/coverage/default/31.sram_ctrl_partial_access.2113717903 Feb 29 02:24:33 PM PST 24 Feb 29 02:26:39 PM PST 24 227626178 ps
T825 /workspace/coverage/default/11.sram_ctrl_max_throughput.1581294167 Feb 29 02:21:37 PM PST 24 Feb 29 02:21:59 PM PST 24 107253473 ps
T826 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4028031430 Feb 29 02:21:30 PM PST 24 Feb 29 02:24:21 PM PST 24 7313758226 ps
T827 /workspace/coverage/default/49.sram_ctrl_lc_escalation.1603514753 Feb 29 02:28:43 PM PST 24 Feb 29 02:28:45 PM PST 24 163285479 ps
T828 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3731816498 Feb 29 02:21:10 PM PST 24 Feb 29 02:24:02 PM PST 24 1670855243 ps
T829 /workspace/coverage/default/10.sram_ctrl_smoke.2124632941 Feb 29 02:21:40 PM PST 24 Feb 29 02:23:44 PM PST 24 1257702505 ps
T830 /workspace/coverage/default/39.sram_ctrl_smoke.3138120854 Feb 29 02:26:14 PM PST 24 Feb 29 02:26:22 PM PST 24 175915651 ps
T831 /workspace/coverage/default/46.sram_ctrl_regwen.1678161158 Feb 29 02:27:47 PM PST 24 Feb 29 02:42:32 PM PST 24 31608414159 ps
T832 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.54913594 Feb 29 02:23:35 PM PST 24 Feb 29 02:32:05 PM PST 24 88244263740 ps
T833 /workspace/coverage/default/41.sram_ctrl_max_throughput.3853366853 Feb 29 02:26:47 PM PST 24 Feb 29 02:26:49 PM PST 24 41459840 ps
T834 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2943511291 Feb 29 02:27:25 PM PST 24 Feb 29 02:58:37 PM PST 24 3968655572 ps
T835 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1607973692 Feb 29 02:23:36 PM PST 24 Feb 29 02:24:03 PM PST 24 101941882 ps
T836 /workspace/coverage/default/45.sram_ctrl_regwen.2401870585 Feb 29 02:27:45 PM PST 24 Feb 29 02:42:25 PM PST 24 11734904806 ps
T837 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3989967860 Feb 29 02:25:29 PM PST 24 Feb 29 02:25:33 PM PST 24 48520222 ps
T838 /workspace/coverage/default/30.sram_ctrl_alert_test.994127993 Feb 29 02:24:34 PM PST 24 Feb 29 02:24:36 PM PST 24 30763299 ps
T839 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3094312518 Feb 29 02:26:23 PM PST 24 Feb 29 02:31:25 PM PST 24 10999364766 ps
T840 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2519829619 Feb 29 02:21:33 PM PST 24 Feb 29 02:41:28 PM PST 24 2960599705 ps
T841 /workspace/coverage/default/37.sram_ctrl_max_throughput.2879453671 Feb 29 02:25:48 PM PST 24 Feb 29 02:26:18 PM PST 24 90102360 ps
T842 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.721707713 Feb 29 02:28:41 PM PST 24 Feb 29 02:29:05 PM PST 24 399761482 ps
T843 /workspace/coverage/default/18.sram_ctrl_alert_test.3898295804 Feb 29 02:22:37 PM PST 24 Feb 29 02:22:38 PM PST 24 15371947 ps
T844 /workspace/coverage/default/37.sram_ctrl_executable.2112214609 Feb 29 02:25:48 PM PST 24 Feb 29 02:47:13 PM PST 24 6758716253 ps
T845 /workspace/coverage/default/8.sram_ctrl_regwen.3150043365 Feb 29 02:21:26 PM PST 24 Feb 29 02:28:30 PM PST 24 4241994960 ps
T846 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1644336580 Feb 29 02:22:26 PM PST 24 Feb 29 02:27:05 PM PST 24 55682840239 ps
T847 /workspace/coverage/default/26.sram_ctrl_alert_test.365715486 Feb 29 02:23:50 PM PST 24 Feb 29 02:23:51 PM PST 24 13979786 ps
T848 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1504816589 Feb 29 02:24:04 PM PST 24 Feb 29 02:31:20 PM PST 24 16628637449 ps
T849 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.833747864 Feb 29 02:25:15 PM PST 24 Feb 29 02:32:17 PM PST 24 16761895705 ps
T850 /workspace/coverage/default/38.sram_ctrl_alert_test.2049341284 Feb 29 02:26:15 PM PST 24 Feb 29 02:26:16 PM PST 24 15363874 ps
T851 /workspace/coverage/default/42.sram_ctrl_bijection.1307353025 Feb 29 02:26:48 PM PST 24 Feb 29 02:28:05 PM PST 24 4458723534 ps
T852 /workspace/coverage/default/7.sram_ctrl_multiple_keys.794915720 Feb 29 02:21:33 PM PST 24 Feb 29 02:22:12 PM PST 24 9250302324 ps
T853 /workspace/coverage/default/21.sram_ctrl_regwen.3961896760 Feb 29 02:23:05 PM PST 24 Feb 29 02:39:53 PM PST 24 1571980820 ps
T854 /workspace/coverage/default/1.sram_ctrl_bijection.1132803538 Feb 29 02:20:56 PM PST 24 Feb 29 02:21:12 PM PST 24 493198896 ps
T855 /workspace/coverage/default/41.sram_ctrl_bijection.1917735162 Feb 29 02:26:36 PM PST 24 Feb 29 02:27:36 PM PST 24 953860306 ps
T856 /workspace/coverage/default/36.sram_ctrl_smoke.1548981019 Feb 29 02:25:42 PM PST 24 Feb 29 02:25:57 PM PST 24 598154687 ps
T857 /workspace/coverage/default/38.sram_ctrl_smoke.1260405961 Feb 29 02:25:59 PM PST 24 Feb 29 02:26:02 PM PST 24 113824300 ps
T858 /workspace/coverage/default/40.sram_ctrl_bijection.3525523158 Feb 29 02:26:24 PM PST 24 Feb 29 02:27:01 PM PST 24 3265248148 ps
T859 /workspace/coverage/default/28.sram_ctrl_executable.3280962067 Feb 29 02:24:18 PM PST 24 Feb 29 02:30:19 PM PST 24 4298595264 ps
T860 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2627698740 Feb 29 02:22:02 PM PST 24 Feb 29 02:24:32 PM PST 24 648116310 ps
T76 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2385577644 Feb 29 02:21:25 PM PST 24 Feb 29 02:21:28 PM PST 24 377743816 ps
T861 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2224567891 Feb 29 02:25:59 PM PST 24 Feb 29 02:31:28 PM PST 24 11724403691 ps
T862 /workspace/coverage/default/45.sram_ctrl_lc_escalation.911707396 Feb 29 02:27:37 PM PST 24 Feb 29 02:27:40 PM PST 24 179835349 ps
T863 /workspace/coverage/default/12.sram_ctrl_bijection.3148385553 Feb 29 02:21:37 PM PST 24 Feb 29 02:22:47 PM PST 24 1110481898 ps
T864 /workspace/coverage/default/47.sram_ctrl_max_throughput.3687602911 Feb 29 02:28:13 PM PST 24 Feb 29 02:28:16 PM PST 24 151975107 ps
T865 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1644980105 Feb 29 02:24:18 PM PST 24 Feb 29 02:29:36 PM PST 24 4367825530 ps
T866 /workspace/coverage/default/23.sram_ctrl_bijection.2027416959 Feb 29 02:23:20 PM PST 24 Feb 29 02:24:18 PM PST 24 7550973566 ps
T867 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.770804854 Feb 29 02:27:46 PM PST 24 Feb 29 02:27:49 PM PST 24 167407850 ps
T868 /workspace/coverage/default/37.sram_ctrl_multiple_keys.412350578 Feb 29 02:25:48 PM PST 24 Feb 29 02:27:03 PM PST 24 1169895990 ps
T869 /workspace/coverage/default/4.sram_ctrl_bijection.2143695239 Feb 29 02:21:22 PM PST 24 Feb 29 02:22:10 PM PST 24 9102130169 ps
T870 /workspace/coverage/default/4.sram_ctrl_mem_walk.248989816 Feb 29 02:21:25 PM PST 24 Feb 29 02:21:35 PM PST 24 134970468 ps
T871 /workspace/coverage/default/24.sram_ctrl_multiple_keys.1553314211 Feb 29 02:23:35 PM PST 24 Feb 29 02:41:13 PM PST 24 13029210288 ps
T872 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1513796605 Feb 29 02:25:37 PM PST 24 Feb 29 02:31:31 PM PST 24 16845144349 ps
T873 /workspace/coverage/default/5.sram_ctrl_multiple_keys.1993491745 Feb 29 02:21:23 PM PST 24 Feb 29 02:37:18 PM PST 24 2309972780 ps
T874 /workspace/coverage/default/18.sram_ctrl_smoke.4192069369 Feb 29 02:22:24 PM PST 24 Feb 29 02:23:01 PM PST 24 2536498142 ps
T875 /workspace/coverage/default/32.sram_ctrl_bijection.2113094824 Feb 29 02:24:47 PM PST 24 Feb 29 02:25:38 PM PST 24 5579273107 ps
T876 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2264644463 Feb 29 02:21:11 PM PST 24 Feb 29 02:21:12 PM PST 24 83767219 ps
T877 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1876071426 Feb 29 02:22:50 PM PST 24 Feb 29 02:40:35 PM PST 24 9123681004 ps
T878 /workspace/coverage/default/16.sram_ctrl_multiple_keys.3245062513 Feb 29 02:22:12 PM PST 24 Feb 29 02:30:47 PM PST 24 20183832803 ps
T879 /workspace/coverage/default/28.sram_ctrl_mem_walk.800036404 Feb 29 02:24:19 PM PST 24 Feb 29 02:24:30 PM PST 24 5004356173 ps
T880 /workspace/coverage/default/8.sram_ctrl_stress_all.342850628 Feb 29 02:21:26 PM PST 24 Feb 29 02:59:02 PM PST 24 135874457311 ps
T881 /workspace/coverage/default/29.sram_ctrl_executable.1838622544 Feb 29 02:24:18 PM PST 24 Feb 29 02:35:58 PM PST 24 7489874210 ps
T882 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1546207352 Feb 29 02:25:29 PM PST 24 Feb 29 02:25:35 PM PST 24 1150610737 ps
T883 /workspace/coverage/default/9.sram_ctrl_lc_escalation.825012425 Feb 29 02:21:26 PM PST 24 Feb 29 02:21:35 PM PST 24 1358473568 ps
T884 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3493283517 Feb 29 02:22:26 PM PST 24 Feb 29 02:34:57 PM PST 24 3043056940 ps
T885 /workspace/coverage/default/48.sram_ctrl_smoke.2761656808 Feb 29 02:28:28 PM PST 24 Feb 29 02:28:41 PM PST 24 476241698 ps
T886 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.157878401 Feb 29 02:26:10 PM PST 24 Feb 29 02:26:15 PM PST 24 155057820 ps
T887 /workspace/coverage/default/24.sram_ctrl_lc_escalation.755094892 Feb 29 02:23:36 PM PST 24 Feb 29 02:23:43 PM PST 24 198093689 ps
T888 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1232029760 Feb 29 02:23:01 PM PST 24 Feb 29 02:41:48 PM PST 24 15762204133 ps
T889 /workspace/coverage/default/30.sram_ctrl_ram_cfg.4110332494 Feb 29 02:24:35 PM PST 24 Feb 29 02:24:36 PM PST 24 49834541 ps
T89 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.659546117 Feb 29 12:48:07 PM PST 24 Feb 29 12:48:08 PM PST 24 37781013 ps
T82 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.521494005 Feb 29 12:48:30 PM PST 24 Feb 29 12:48:31 PM PST 24 23319564 ps
T52 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3730033692 Feb 29 12:48:25 PM PST 24 Feb 29 12:48:25 PM PST 24 22493834 ps
T53 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.967698491 Feb 29 12:48:43 PM PST 24 Feb 29 12:48:50 PM PST 24 1543467008 ps
T54 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1392724148 Feb 29 12:48:47 PM PST 24 Feb 29 12:48:54 PM PST 24 18953719 ps
T55 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3315664624 Feb 29 12:48:16 PM PST 24 Feb 29 12:48:17 PM PST 24 38316561 ps
T27 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1580187062 Feb 29 12:48:40 PM PST 24 Feb 29 12:48:42 PM PST 24 2027840236 ps
T56 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1081283111 Feb 29 12:48:34 PM PST 24 Feb 29 12:48:40 PM PST 24 3390023876 ps
T57 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3716386466 Feb 29 12:48:19 PM PST 24 Feb 29 12:48:20 PM PST 24 19546317 ps
T83 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2201649774 Feb 29 12:48:29 PM PST 24 Feb 29 12:48:36 PM PST 24 260965907 ps
T30 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2865130202 Feb 29 12:48:24 PM PST 24 Feb 29 12:48:27 PM PST 24 816085062 ps
T90 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2988583456 Feb 29 12:48:24 PM PST 24 Feb 29 12:48:25 PM PST 24 19108802 ps
T84 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.320258500 Feb 29 12:48:21 PM PST 24 Feb 29 12:48:22 PM PST 24 16127302 ps
T28 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2573486642 Feb 29 12:48:15 PM PST 24 Feb 29 12:48:17 PM PST 24 378004096 ps
T42 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1898149655 Feb 29 12:48:31 PM PST 24 Feb 29 12:48:36 PM PST 24 133393540 ps
T58 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3077177472 Feb 29 12:48:24 PM PST 24 Feb 29 12:48:26 PM PST 24 93177005 ps
T59 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1758508169 Feb 29 12:48:39 PM PST 24 Feb 29 12:48:40 PM PST 24 21123295 ps
T890 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1145145973 Feb 29 12:48:16 PM PST 24 Feb 29 12:48:17 PM PST 24 18698836 ps
T43 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3599475090 Feb 29 12:48:14 PM PST 24 Feb 29 12:48:19 PM PST 24 308828923 ps
T60 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2480916469 Feb 29 12:48:24 PM PST 24 Feb 29 12:48:25 PM PST 24 40468394 ps
T44 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2384388985 Feb 29 12:48:43 PM PST 24 Feb 29 12:48:48 PM PST 24 140196510 ps
T45 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1509055082 Feb 29 12:48:18 PM PST 24 Feb 29 12:48:23 PM PST 24 40186772 ps
T29 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.257372213 Feb 29 12:48:36 PM PST 24 Feb 29 12:48:39 PM PST 24 89352500 ps
T46 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4003500330 Feb 29 12:48:31 PM PST 24 Feb 29 12:48:35 PM PST 24 33738306 ps
T47 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2551742707 Feb 29 12:48:25 PM PST 24 Feb 29 12:48:39 PM PST 24 170980968 ps
T48 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2247745797 Feb 29 12:48:13 PM PST 24 Feb 29 12:48:17 PM PST 24 213988684 ps
T61 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1254342331 Feb 29 12:48:17 PM PST 24 Feb 29 12:48:19 PM PST 24 35688041 ps
T49 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.420841636 Feb 29 12:48:33 PM PST 24 Feb 29 12:48:36 PM PST 24 194822956 ps
T50 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2571661663 Feb 29 12:48:05 PM PST 24 Feb 29 12:48:07 PM PST 24 48430369 ps
T91 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1495961866 Feb 29 12:48:00 PM PST 24 Feb 29 12:48:03 PM PST 24 353911587 ps
T891 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2121474416 Feb 29 12:48:16 PM PST 24 Feb 29 12:48:21 PM PST 24 13429725 ps
T99 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3066851604 Feb 29 12:48:25 PM PST 24 Feb 29 12:48:26 PM PST 24 277861743 ps
T95 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1423555174 Feb 29 12:48:16 PM PST 24 Feb 29 12:48:20 PM PST 24 831423466 ps
T892 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3086033036 Feb 29 12:47:57 PM PST 24 Feb 29 12:47:58 PM PST 24 16361903 ps
T51 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2878071177 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:05 PM PST 24 783446925 ps
T893 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2975774808 Feb 29 12:48:10 PM PST 24 Feb 29 12:48:12 PM PST 24 70445118 ps
T894 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4033620819 Feb 29 12:48:26 PM PST 24 Feb 29 12:48:31 PM PST 24 144639353 ps
T97 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2036065733 Feb 29 12:48:08 PM PST 24 Feb 29 12:48:11 PM PST 24 554148254 ps
T895 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1308791879 Feb 29 12:48:17 PM PST 24 Feb 29 12:48:23 PM PST 24 12493822 ps
T66 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.244232256 Feb 29 12:48:07 PM PST 24 Feb 29 12:48:12 PM PST 24 796309659 ps
T896 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1416145457 Feb 29 12:48:08 PM PST 24 Feb 29 12:48:09 PM PST 24 21447985 ps
T897 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2988824786 Feb 29 12:48:27 PM PST 24 Feb 29 12:48:28 PM PST 24 26149616 ps
T67 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1862218210 Feb 29 12:48:40 PM PST 24 Feb 29 12:48:50 PM PST 24 409886260 ps
T898 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1949109462 Feb 29 12:48:33 PM PST 24 Feb 29 12:48:34 PM PST 24 64188860 ps
T899 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.191849614 Feb 29 12:48:00 PM PST 24 Feb 29 12:48:01 PM PST 24 18688671 ps
T92 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3268365682 Feb 29 12:48:21 PM PST 24 Feb 29 12:48:28 PM PST 24 99302252 ps
T900 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3250361531 Feb 29 12:48:21 PM PST 24 Feb 29 12:48:22 PM PST 24 92972710 ps
T68 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2221946335 Feb 29 12:48:43 PM PST 24 Feb 29 12:48:49 PM PST 24 7820599611 ps
T69 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.935778141 Feb 29 12:47:58 PM PST 24 Feb 29 12:47:59 PM PST 24 18836224 ps
T901 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2587014421 Feb 29 12:47:58 PM PST 24 Feb 29 12:48:01 PM PST 24 1506351577 ps
T902 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.430917645 Feb 29 12:48:33 PM PST 24 Feb 29 12:48:35 PM PST 24 253753637 ps
T903 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3964038281 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:04 PM PST 24 103761795 ps
T904 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3693506147 Feb 29 12:48:27 PM PST 24 Feb 29 12:48:28 PM PST 24 94394982 ps
T905 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.371522593 Feb 29 12:48:24 PM PST 24 Feb 29 12:48:28 PM PST 24 855658317 ps
T70 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.421146421 Feb 29 12:48:12 PM PST 24 Feb 29 12:48:15 PM PST 24 217033463 ps
T906 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1600332326 Feb 29 12:48:17 PM PST 24 Feb 29 12:48:18 PM PST 24 22103878 ps
T907 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3942910525 Feb 29 12:48:23 PM PST 24 Feb 29 12:48:24 PM PST 24 22414099 ps
T908 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.583256265 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:04 PM PST 24 29138333 ps
T909 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4114429545 Feb 29 12:48:23 PM PST 24 Feb 29 12:48:28 PM PST 24 1653253311 ps
T98 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2514356381 Feb 29 12:48:17 PM PST 24 Feb 29 12:48:20 PM PST 24 205141633 ps
T910 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.85814869 Feb 29 12:48:00 PM PST 24 Feb 29 12:48:02 PM PST 24 40879368 ps
T96 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1105447231 Feb 29 12:48:22 PM PST 24 Feb 29 12:48:24 PM PST 24 197392206 ps
T100 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3963035560 Feb 29 12:48:10 PM PST 24 Feb 29 12:48:12 PM PST 24 122537057 ps
T77 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2578052264 Feb 29 12:48:05 PM PST 24 Feb 29 12:48:16 PM PST 24 676241044 ps
T78 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1209202287 Feb 29 12:48:24 PM PST 24 Feb 29 12:48:37 PM PST 24 423429689 ps
T911 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3649198140 Feb 29 12:48:22 PM PST 24 Feb 29 12:48:28 PM PST 24 557790376 ps
T912 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.198139805 Feb 29 12:48:10 PM PST 24 Feb 29 12:48:11 PM PST 24 33816305 ps
T913 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2870261803 Feb 29 12:48:22 PM PST 24 Feb 29 12:48:22 PM PST 24 58952411 ps
T914 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3447934704 Feb 29 12:48:29 PM PST 24 Feb 29 12:48:30 PM PST 24 47342763 ps
T915 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1177991633 Feb 29 12:47:57 PM PST 24 Feb 29 12:47:57 PM PST 24 55907646 ps
T916 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3345346922 Feb 29 12:48:13 PM PST 24 Feb 29 12:48:14 PM PST 24 35261993 ps
T917 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3733571784 Feb 29 12:48:35 PM PST 24 Feb 29 12:48:37 PM PST 24 237993677 ps
T918 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3250223353 Feb 29 12:48:17 PM PST 24 Feb 29 12:48:19 PM PST 24 53036281 ps
T919 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3081376268 Feb 29 12:48:41 PM PST 24 Feb 29 12:48:43 PM PST 24 450238476 ps
T920 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.978028574 Feb 29 12:48:27 PM PST 24 Feb 29 12:48:32 PM PST 24 290833506 ps
T921 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1159183602 Feb 29 12:48:38 PM PST 24 Feb 29 12:48:40 PM PST 24 39080322 ps
T922 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1378699900 Feb 29 12:48:10 PM PST 24 Feb 29 12:48:11 PM PST 24 13257355 ps
T923 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.68590997 Feb 29 12:48:22 PM PST 24 Feb 29 12:48:26 PM PST 24 139128540 ps
T924 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2318763257 Feb 29 12:48:13 PM PST 24 Feb 29 12:48:15 PM PST 24 63527721 ps
T925 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.354409410 Feb 29 12:48:12 PM PST 24 Feb 29 12:48:13 PM PST 24 19256109 ps
T926 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2168408564 Feb 29 12:48:48 PM PST 24 Feb 29 12:48:50 PM PST 24 55105034 ps
T927 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1227076043 Feb 29 12:48:26 PM PST 24 Feb 29 12:48:27 PM PST 24 88714499 ps
T928 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3028196504 Feb 29 12:48:05 PM PST 24 Feb 29 12:48:09 PM PST 24 78300680 ps
T929 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2266045515 Feb 29 12:47:57 PM PST 24 Feb 29 12:47:58 PM PST 24 24087332 ps
T930 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.545982406 Feb 29 12:48:15 PM PST 24 Feb 29 12:48:16 PM PST 24 50110614 ps
T931 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4179031521 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:07 PM PST 24 466599345 ps
T932 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3321543566 Feb 29 12:48:07 PM PST 24 Feb 29 12:48:09 PM PST 24 76122044 ps
T933 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2975056271 Feb 29 12:48:47 PM PST 24 Feb 29 12:48:49 PM PST 24 30183686 ps
T934 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.971270111 Feb 29 12:48:04 PM PST 24 Feb 29 12:48:05 PM PST 24 16978985 ps
T935 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.820957798 Feb 29 12:48:06 PM PST 24 Feb 29 12:48:12 PM PST 24 436453087 ps
T936 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4017958250 Feb 29 12:48:37 PM PST 24 Feb 29 12:48:39 PM PST 24 19122026 ps
T937 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3120341224 Feb 29 12:47:58 PM PST 24 Feb 29 12:48:01 PM PST 24 40935186 ps
T938 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2310116319 Feb 29 12:48:43 PM PST 24 Feb 29 12:48:47 PM PST 24 137773394 ps
T101 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2353755507 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:05 PM PST 24 250288684 ps
T102 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3679458410 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:04 PM PST 24 993119579 ps
T939 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.607327989 Feb 29 12:48:22 PM PST 24 Feb 29 12:48:28 PM PST 24 4307999482 ps
T940 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.836894339 Feb 29 12:48:20 PM PST 24 Feb 29 12:48:21 PM PST 24 17458775 ps
T941 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2113854660 Feb 29 12:48:33 PM PST 24 Feb 29 12:48:36 PM PST 24 567943414 ps
T942 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1617264152 Feb 29 12:48:23 PM PST 24 Feb 29 12:48:29 PM PST 24 1321811680 ps
T943 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2050412855 Feb 29 12:48:30 PM PST 24 Feb 29 12:48:30 PM PST 24 25713787 ps
T944 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3899749534 Feb 29 12:48:28 PM PST 24 Feb 29 12:48:33 PM PST 24 172191580 ps
T945 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2130416969 Feb 29 12:48:37 PM PST 24 Feb 29 12:48:39 PM PST 24 297519882 ps
T946 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3685052594 Feb 29 12:48:30 PM PST 24 Feb 29 12:48:32 PM PST 24 36152681 ps
T947 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3283591425 Feb 29 12:48:34 PM PST 24 Feb 29 12:48:35 PM PST 24 31096033 ps
T948 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.25804773 Feb 29 12:48:46 PM PST 24 Feb 29 12:48:51 PM PST 24 330725009 ps
T949 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4050515504 Feb 29 12:48:34 PM PST 24 Feb 29 12:48:36 PM PST 24 22953947 ps
T950 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.86859913 Feb 29 12:48:30 PM PST 24 Feb 29 12:48:31 PM PST 24 40521905 ps
T951 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3707794638 Feb 29 12:48:40 PM PST 24 Feb 29 12:48:51 PM PST 24 2083497344 ps
T952 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3333894563 Feb 29 12:48:24 PM PST 24 Feb 29 12:48:25 PM PST 24 19704252 ps
T103 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.53611092 Feb 29 12:48:38 PM PST 24 Feb 29 12:48:41 PM PST 24 107101080 ps
T953 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3481849377 Feb 29 12:48:16 PM PST 24 Feb 29 12:48:25 PM PST 24 654314969 ps
T954 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.15101565 Feb 29 12:48:43 PM PST 24 Feb 29 12:48:45 PM PST 24 28631644 ps
T955 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1120617269 Feb 29 12:48:36 PM PST 24 Feb 29 12:48:47 PM PST 24 361863804 ps
T956 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.295495173 Feb 29 12:48:12 PM PST 24 Feb 29 12:48:12 PM PST 24 23639108 ps
T957 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1324447519 Feb 29 12:48:15 PM PST 24 Feb 29 12:48:16 PM PST 24 17642575 ps

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.3920134510
Short name T3
Test name
Test status
Simulation time 1005743261 ps
CPU time 15.77 seconds
Started Feb 29 02:24:58 PM PST 24
Finished Feb 29 02:25:14 PM PST 24
Peak memory 210936 kb
Host smart-e31c21fa-5e2b-4bfc-a425-1bc9d6dc8563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920134510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.3920134510
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.3581579028
Short name T5
Test name
Test status
Simulation time 58664940206 ps
CPU time 818.75 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:35:51 PM PST 24
Peak memory 373632 kb
Host smart-2ee16359-b993-4b9c-a467-9fdd100119f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581579028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.3581579028
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1580187062
Short name T27
Test name
Test status
Simulation time 2027840236 ps
CPU time 2.19 seconds
Started Feb 29 12:48:40 PM PST 24
Finished Feb 29 12:48:42 PM PST 24
Peak memory 202396 kb
Host smart-23e24943-a773-49a0-9ad7-98c35b1fd4c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580187062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.1580187062
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3599475090
Short name T43
Test name
Test status
Simulation time 308828923 ps
CPU time 4.1 seconds
Started Feb 29 12:48:14 PM PST 24
Finished Feb 29 12:48:19 PM PST 24
Peak memory 202444 kb
Host smart-ec6ecbae-0d09-4b24-8c0c-ebfc7f438ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599475090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.3599475090
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.22912941
Short name T23
Test name
Test status
Simulation time 22113831717 ps
CPU time 1429.05 seconds
Started Feb 29 02:27:13 PM PST 24
Finished Feb 29 02:51:03 PM PST 24
Peak memory 364900 kb
Host smart-870889e5-3a09-4db7-9d6b-2ccf6e4920cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22912941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.sram_ctrl_stress_all.22912941
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.977848705
Short name T16
Test name
Test status
Simulation time 211732931 ps
CPU time 3.19 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:21:14 PM PST 24
Peak memory 221404 kb
Host smart-b6232afb-3379-4398-a5a4-2b374fa4c789
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977848705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_sec_cm.977848705
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2360197115
Short name T65
Test name
Test status
Simulation time 60763922611 ps
CPU time 384.61 seconds
Started Feb 29 02:22:26 PM PST 24
Finished Feb 29 02:28:52 PM PST 24
Peak memory 202692 kb
Host smart-b38563ad-6981-404b-a787-0359f7598289
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360197115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2360197115
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.1129157009
Short name T94
Test name
Test status
Simulation time 140007525204 ps
CPU time 1640.57 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:50:57 PM PST 24
Peak memory 369184 kb
Host smart-88201fb0-73be-4b86-871e-b66307660291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129157009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.1129157009
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1081283111
Short name T56
Test name
Test status
Simulation time 3390023876 ps
CPU time 4.89 seconds
Started Feb 29 12:48:34 PM PST 24
Finished Feb 29 12:48:40 PM PST 24
Peak memory 202472 kb
Host smart-ce04090c-c336-4219-947e-6f2bb7d83adc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081283111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1081283111
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3498669073
Short name T71
Test name
Test status
Simulation time 31977360028 ps
CPU time 663.11 seconds
Started Feb 29 02:21:42 PM PST 24
Finished Feb 29 02:32:46 PM PST 24
Peak memory 363836 kb
Host smart-f555b6c5-e5d5-483b-8ce7-6f291ff68225
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498669073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.3498669073
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.464840508
Short name T246
Test name
Test status
Simulation time 84757235 ps
CPU time 1.07 seconds
Started Feb 29 02:21:36 PM PST 24
Finished Feb 29 02:21:37 PM PST 24
Peak memory 202900 kb
Host smart-d5c61d7f-8d51-419d-bb9c-73a1a5c8c659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464840508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.464840508
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.3092666926
Short name T21
Test name
Test status
Simulation time 14353281 ps
CPU time 0.65 seconds
Started Feb 29 02:22:14 PM PST 24
Finished Feb 29 02:22:15 PM PST 24
Peak memory 201532 kb
Host smart-63c7495d-1916-4cad-9ecb-a515b3c75e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092666926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.3092666926
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3963035560
Short name T100
Test name
Test status
Simulation time 122537057 ps
CPU time 1.48 seconds
Started Feb 29 12:48:10 PM PST 24
Finished Feb 29 12:48:12 PM PST 24
Peak memory 202344 kb
Host smart-a12889ff-e8d3-46c9-95fa-36682eeee455
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963035560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.3963035560
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.923913656
Short name T263
Test name
Test status
Simulation time 278436895904 ps
CPU time 5222.61 seconds
Started Feb 29 02:22:26 PM PST 24
Finished Feb 29 03:49:30 PM PST 24
Peak memory 375528 kb
Host smart-2180c2cf-bcf5-4499-a07c-987776c021a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923913656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_stress_all.923913656
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2353755507
Short name T101
Test name
Test status
Simulation time 250288684 ps
CPU time 2.06 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 202388 kb
Host smart-7f5c4dc7-a349-40f7-aa32-2c9ac8e81eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353755507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2353755507
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.2098062
Short name T104
Test name
Test status
Simulation time 32334837626 ps
CPU time 673.45 seconds
Started Feb 29 02:23:51 PM PST 24
Finished Feb 29 02:35:04 PM PST 24
Peak memory 349964 kb
Host smart-f668f8de-267c-45e5-81e1-402cbdf6ca92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2098062
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3268365682
Short name T92
Test name
Test status
Simulation time 99302252 ps
CPU time 1.5 seconds
Started Feb 29 12:48:21 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 202300 kb
Host smart-f4d9cf33-88f0-4b0e-967e-4ea3d3963b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268365682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.3268365682
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.198139805
Short name T912
Test name
Test status
Simulation time 33816305 ps
CPU time 0.7 seconds
Started Feb 29 12:48:10 PM PST 24
Finished Feb 29 12:48:11 PM PST 24
Peak memory 201924 kb
Host smart-52263bd0-e4b5-4cb6-9d14-04fbe43bbbc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198139805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_aliasing.198139805
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3077177472
Short name T58
Test name
Test status
Simulation time 93177005 ps
CPU time 1.78 seconds
Started Feb 29 12:48:24 PM PST 24
Finished Feb 29 12:48:26 PM PST 24
Peak memory 202348 kb
Host smart-cba9be4e-990c-499f-998c-75500ac92ce1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077177472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.3077177472
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3315664624
Short name T55
Test name
Test status
Simulation time 38316561 ps
CPU time 0.7 seconds
Started Feb 29 12:48:16 PM PST 24
Finished Feb 29 12:48:17 PM PST 24
Peak memory 202156 kb
Host smart-fcc8fec3-d4f2-4dbb-8ef8-2d2548642292
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315664624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.3315664624
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3086033036
Short name T892
Test name
Test status
Simulation time 16361903 ps
CPU time 0.65 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 201052 kb
Host smart-71f02bef-46e9-4bc7-b280-96e1ddf1f88c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086033036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.3086033036
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.820957798
Short name T935
Test name
Test status
Simulation time 436453087 ps
CPU time 5.57 seconds
Started Feb 29 12:48:06 PM PST 24
Finished Feb 29 12:48:12 PM PST 24
Peak memory 210584 kb
Host smart-97514ce1-a3ef-4c1a-9a09-7b74f443834c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820957798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.820957798
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2266045515
Short name T929
Test name
Test status
Simulation time 24087332 ps
CPU time 0.68 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 202104 kb
Host smart-dff9d339-0ddf-464b-bfd7-87c082f324db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266045515 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2266045515
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2571661663
Short name T50
Test name
Test status
Simulation time 48430369 ps
CPU time 2.04 seconds
Started Feb 29 12:48:05 PM PST 24
Finished Feb 29 12:48:07 PM PST 24
Peak memory 202368 kb
Host smart-9a4a2eb8-312c-46c6-9383-dccd14dcfd13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571661663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.2571661663
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2988583456
Short name T90
Test name
Test status
Simulation time 19108802 ps
CPU time 0.71 seconds
Started Feb 29 12:48:24 PM PST 24
Finished Feb 29 12:48:25 PM PST 24
Peak memory 202156 kb
Host smart-b3228b34-e2f2-47b5-bfcd-19805badc1a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988583456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.2988583456
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1495961866
Short name T91
Test name
Test status
Simulation time 353911587 ps
CPU time 2.25 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 202316 kb
Host smart-c189e77a-60fd-4bc7-91ac-7a462e2d6be3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495961866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.1495961866
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1949109462
Short name T898
Test name
Test status
Simulation time 64188860 ps
CPU time 0.66 seconds
Started Feb 29 12:48:33 PM PST 24
Finished Feb 29 12:48:34 PM PST 24
Peak memory 202372 kb
Host smart-ab35d9b3-914d-4c58-bf2b-7f653651f0ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949109462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1949109462
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.354409410
Short name T925
Test name
Test status
Simulation time 19256109 ps
CPU time 0.73 seconds
Started Feb 29 12:48:12 PM PST 24
Finished Feb 29 12:48:13 PM PST 24
Peak memory 202124 kb
Host smart-e81499f8-0d01-4a9f-bd7b-87b8827116b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354409410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_csr_rw.354409410
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4179031521
Short name T931
Test name
Test status
Simulation time 466599345 ps
CPU time 3.39 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:07 PM PST 24
Peak memory 202472 kb
Host smart-83741c68-b568-4052-918c-c6d945aea228
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179031521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.4179031521
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.15101565
Short name T954
Test name
Test status
Simulation time 28631644 ps
CPU time 0.7 seconds
Started Feb 29 12:48:43 PM PST 24
Finished Feb 29 12:48:45 PM PST 24
Peak memory 202056 kb
Host smart-8a509afe-deeb-41ba-9e8d-3d9ae5c98274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15101565 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.15101565
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2865130202
Short name T30
Test name
Test status
Simulation time 816085062 ps
CPU time 3.62 seconds
Started Feb 29 12:48:24 PM PST 24
Finished Feb 29 12:48:27 PM PST 24
Peak memory 202376 kb
Host smart-fe7b6319-953f-402e-bc34-eb133a2bb72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865130202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.2865130202
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.971270111
Short name T934
Test name
Test status
Simulation time 16978985 ps
CPU time 0.66 seconds
Started Feb 29 12:48:04 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 201956 kb
Host smart-ad2bbacf-876f-46c0-b38a-1d0f5da95745
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971270111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 10.sram_ctrl_csr_rw.971270111
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1209202287
Short name T78
Test name
Test status
Simulation time 423429689 ps
CPU time 12.23 seconds
Started Feb 29 12:48:24 PM PST 24
Finished Feb 29 12:48:37 PM PST 24
Peak memory 202560 kb
Host smart-e9b1b996-e9b5-4e37-b762-b7eca1e46bbb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209202287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.1209202287
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3333894563
Short name T952
Test name
Test status
Simulation time 19704252 ps
CPU time 0.7 seconds
Started Feb 29 12:48:24 PM PST 24
Finished Feb 29 12:48:25 PM PST 24
Peak memory 202132 kb
Host smart-f64d457c-1aa2-4fa2-a7b8-0f27235d2a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333894563 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3333894563
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2514356381
Short name T98
Test name
Test status
Simulation time 205141633 ps
CPU time 2.3 seconds
Started Feb 29 12:48:17 PM PST 24
Finished Feb 29 12:48:20 PM PST 24
Peak memory 202412 kb
Host smart-8d67dc00-fb94-4eca-8b04-57b9b324a83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514356381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2514356381
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2121474416
Short name T891
Test name
Test status
Simulation time 13429725 ps
CPU time 0.65 seconds
Started Feb 29 12:48:16 PM PST 24
Finished Feb 29 12:48:21 PM PST 24
Peak memory 202136 kb
Host smart-973b08cc-3847-4ec2-9c1e-aba57acec789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121474416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2121474416
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3481849377
Short name T953
Test name
Test status
Simulation time 654314969 ps
CPU time 8.49 seconds
Started Feb 29 12:48:16 PM PST 24
Finished Feb 29 12:48:25 PM PST 24
Peak memory 202508 kb
Host smart-a6fa81ba-bd43-408a-8f25-6d7e4c37480d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481849377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.3481849377
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.521494005
Short name T82
Test name
Test status
Simulation time 23319564 ps
CPU time 0.73 seconds
Started Feb 29 12:48:30 PM PST 24
Finished Feb 29 12:48:31 PM PST 24
Peak memory 202168 kb
Host smart-27d0e12d-3b72-4609-8133-ae5643599ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521494005 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.521494005
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2318763257
Short name T924
Test name
Test status
Simulation time 63527721 ps
CPU time 2.36 seconds
Started Feb 29 12:48:13 PM PST 24
Finished Feb 29 12:48:15 PM PST 24
Peak memory 202436 kb
Host smart-f701826a-f54b-4d32-a6fe-9eec9018bbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318763257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.2318763257
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2036065733
Short name T97
Test name
Test status
Simulation time 554148254 ps
CPU time 2.08 seconds
Started Feb 29 12:48:08 PM PST 24
Finished Feb 29 12:48:11 PM PST 24
Peak memory 202308 kb
Host smart-f4676c57-8aeb-475f-b3b5-5301a9ee75e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036065733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.2036065733
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.659546117
Short name T89
Test name
Test status
Simulation time 37781013 ps
CPU time 0.67 seconds
Started Feb 29 12:48:07 PM PST 24
Finished Feb 29 12:48:08 PM PST 24
Peak memory 201092 kb
Host smart-13c2d6ed-4dcb-4624-9749-ca124a3c8e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659546117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_csr_rw.659546117
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2587014421
Short name T901
Test name
Test status
Simulation time 1506351577 ps
CPU time 3.42 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 202520 kb
Host smart-4711336d-9b7f-45c2-bc8a-e06e876c43ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587014421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2587014421
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4050515504
Short name T949
Test name
Test status
Simulation time 22953947 ps
CPU time 0.77 seconds
Started Feb 29 12:48:34 PM PST 24
Finished Feb 29 12:48:36 PM PST 24
Peak memory 202136 kb
Host smart-59988f1a-41c9-4850-b98c-7306586d99d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050515504 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.4050515504
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2247745797
Short name T48
Test name
Test status
Simulation time 213988684 ps
CPU time 3.57 seconds
Started Feb 29 12:48:13 PM PST 24
Finished Feb 29 12:48:17 PM PST 24
Peak memory 202396 kb
Host smart-a251d12e-ebfa-435a-9ff2-10b31f0166a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247745797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.2247745797
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.53611092
Short name T103
Test name
Test status
Simulation time 107101080 ps
CPU time 1.49 seconds
Started Feb 29 12:48:38 PM PST 24
Finished Feb 29 12:48:41 PM PST 24
Peak memory 202392 kb
Host smart-cad13bd2-e3b3-4372-bcda-b0ac7a973187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53611092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.sram_ctrl_tl_intg_err.53611092
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4017958250
Short name T936
Test name
Test status
Simulation time 19122026 ps
CPU time 0.65 seconds
Started Feb 29 12:48:37 PM PST 24
Finished Feb 29 12:48:39 PM PST 24
Peak memory 202144 kb
Host smart-7baaedce-34fe-4ae6-95e5-773d09eb897a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017958250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.4017958250
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1862218210
Short name T67
Test name
Test status
Simulation time 409886260 ps
CPU time 10.51 seconds
Started Feb 29 12:48:40 PM PST 24
Finished Feb 29 12:48:50 PM PST 24
Peak memory 202408 kb
Host smart-bcd1c96e-1917-4ee1-bc1a-1692e6904aa8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862218210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.1862218210
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3716386466
Short name T57
Test name
Test status
Simulation time 19546317 ps
CPU time 0.8 seconds
Started Feb 29 12:48:19 PM PST 24
Finished Feb 29 12:48:20 PM PST 24
Peak memory 202128 kb
Host smart-df1d1a0b-6ae9-4f64-ad6e-103e9e4b3b24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716386466 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3716386466
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2975774808
Short name T893
Test name
Test status
Simulation time 70445118 ps
CPU time 1.43 seconds
Started Feb 29 12:48:10 PM PST 24
Finished Feb 29 12:48:12 PM PST 24
Peak memory 202348 kb
Host smart-df6f07b3-3173-40e6-9ad8-22f29629b67b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975774808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.2975774808
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2573486642
Short name T28
Test name
Test status
Simulation time 378004096 ps
CPU time 1.45 seconds
Started Feb 29 12:48:15 PM PST 24
Finished Feb 29 12:48:17 PM PST 24
Peak memory 202384 kb
Host smart-0a699d23-a487-4bfa-bfde-cd8bdbb1f4c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573486642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.2573486642
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.86859913
Short name T950
Test name
Test status
Simulation time 40521905 ps
CPU time 0.64 seconds
Started Feb 29 12:48:30 PM PST 24
Finished Feb 29 12:48:31 PM PST 24
Peak memory 201992 kb
Host smart-f92bd280-88fd-41a9-bc42-30eca22f6ffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86859913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.sram_ctrl_csr_rw.86859913
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2221946335
Short name T68
Test name
Test status
Simulation time 7820599611 ps
CPU time 5.22 seconds
Started Feb 29 12:48:43 PM PST 24
Finished Feb 29 12:48:49 PM PST 24
Peak memory 202500 kb
Host smart-aecf690a-3e23-481a-9df3-e11b1ed41e50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221946335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2221946335
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.320258500
Short name T84
Test name
Test status
Simulation time 16127302 ps
CPU time 0.76 seconds
Started Feb 29 12:48:21 PM PST 24
Finished Feb 29 12:48:22 PM PST 24
Peak memory 202048 kb
Host smart-9e40780a-651a-4eb2-9190-e4b4777904cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320258500 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.320258500
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.420841636
Short name T49
Test name
Test status
Simulation time 194822956 ps
CPU time 3.37 seconds
Started Feb 29 12:48:33 PM PST 24
Finished Feb 29 12:48:36 PM PST 24
Peak memory 202428 kb
Host smart-da823cb7-07ac-432f-9fb7-a1aaed1120cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420841636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_tl_errors.420841636
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3733571784
Short name T917
Test name
Test status
Simulation time 237993677 ps
CPU time 1.36 seconds
Started Feb 29 12:48:35 PM PST 24
Finished Feb 29 12:48:37 PM PST 24
Peak memory 202280 kb
Host smart-f353421c-e11f-414c-bcd9-f31f2e714dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733571784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3733571784
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3730033692
Short name T52
Test name
Test status
Simulation time 22493834 ps
CPU time 0.71 seconds
Started Feb 29 12:48:25 PM PST 24
Finished Feb 29 12:48:25 PM PST 24
Peak memory 201176 kb
Host smart-0dae8e97-e5da-45f2-a07a-4be5cf1b8eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730033692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3730033692
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3649198140
Short name T911
Test name
Test status
Simulation time 557790376 ps
CPU time 5.62 seconds
Started Feb 29 12:48:22 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 202448 kb
Host smart-f174a162-c7df-4863-a655-57447109b921
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649198140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3649198140
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1308791879
Short name T895
Test name
Test status
Simulation time 12493822 ps
CPU time 0.69 seconds
Started Feb 29 12:48:17 PM PST 24
Finished Feb 29 12:48:23 PM PST 24
Peak memory 201384 kb
Host smart-4c49ebed-de93-4990-b388-4a5ea1788722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308791879 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1308791879
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.978028574
Short name T920
Test name
Test status
Simulation time 290833506 ps
CPU time 4.35 seconds
Started Feb 29 12:48:27 PM PST 24
Finished Feb 29 12:48:32 PM PST 24
Peak memory 202476 kb
Host smart-0e460318-a374-4bba-ba11-e94a1f487564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978028574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_tl_errors.978028574
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2988824786
Short name T897
Test name
Test status
Simulation time 26149616 ps
CPU time 0.64 seconds
Started Feb 29 12:48:27 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 202108 kb
Host smart-d96cc76b-1685-4f1f-9ae7-33b93d6f4935
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988824786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.2988824786
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1120617269
Short name T955
Test name
Test status
Simulation time 361863804 ps
CPU time 9.84 seconds
Started Feb 29 12:48:36 PM PST 24
Finished Feb 29 12:48:47 PM PST 24
Peak memory 202440 kb
Host smart-d687069c-edc7-4615-a0a1-fb3378b4511f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120617269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1120617269
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3942910525
Short name T907
Test name
Test status
Simulation time 22414099 ps
CPU time 0.75 seconds
Started Feb 29 12:48:23 PM PST 24
Finished Feb 29 12:48:24 PM PST 24
Peak memory 202028 kb
Host smart-814ab820-89c7-444a-81bb-1c63124da75f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942910525 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3942910525
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3685052594
Short name T946
Test name
Test status
Simulation time 36152681 ps
CPU time 2.35 seconds
Started Feb 29 12:48:30 PM PST 24
Finished Feb 29 12:48:32 PM PST 24
Peak memory 202424 kb
Host smart-512bfc02-5238-417e-a887-6ae42065f8fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685052594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.3685052594
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1423555174
Short name T95
Test name
Test status
Simulation time 831423466 ps
CPU time 2.89 seconds
Started Feb 29 12:48:16 PM PST 24
Finished Feb 29 12:48:20 PM PST 24
Peak memory 202324 kb
Host smart-5fd4b5eb-612b-4fe1-998e-447e0802431f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423555174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1423555174
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3447934704
Short name T914
Test name
Test status
Simulation time 47342763 ps
CPU time 0.64 seconds
Started Feb 29 12:48:29 PM PST 24
Finished Feb 29 12:48:30 PM PST 24
Peak memory 202028 kb
Host smart-0b0d303b-dc54-46f3-93ce-693ef205cc90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447934704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.3447934704
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3707794638
Short name T951
Test name
Test status
Simulation time 2083497344 ps
CPU time 10.71 seconds
Started Feb 29 12:48:40 PM PST 24
Finished Feb 29 12:48:51 PM PST 24
Peak memory 202568 kb
Host smart-a6abd8a3-20ad-4d49-a2f0-af673a3a7e14
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707794638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3707794638
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2870261803
Short name T913
Test name
Test status
Simulation time 58952411 ps
CPU time 0.76 seconds
Started Feb 29 12:48:22 PM PST 24
Finished Feb 29 12:48:22 PM PST 24
Peak memory 202100 kb
Host smart-1ee129f3-a6be-495f-8cbe-d62a4ac403c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870261803 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2870261803
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3899749534
Short name T944
Test name
Test status
Simulation time 172191580 ps
CPU time 3.93 seconds
Started Feb 29 12:48:28 PM PST 24
Finished Feb 29 12:48:33 PM PST 24
Peak memory 202432 kb
Host smart-7785b738-1fd7-40ad-9438-22c7a036c7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899749534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.3899749534
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.430917645
Short name T902
Test name
Test status
Simulation time 253753637 ps
CPU time 1.28 seconds
Started Feb 29 12:48:33 PM PST 24
Finished Feb 29 12:48:35 PM PST 24
Peak memory 202300 kb
Host smart-61788b70-3192-49bb-8458-88369176b10f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430917645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.sram_ctrl_tl_intg_err.430917645
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3345346922
Short name T916
Test name
Test status
Simulation time 35261993 ps
CPU time 0.62 seconds
Started Feb 29 12:48:13 PM PST 24
Finished Feb 29 12:48:14 PM PST 24
Peak memory 202080 kb
Host smart-d22dd367-fbd3-4da9-a514-ec1e98f6b0b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345346922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3345346922
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3250361531
Short name T900
Test name
Test status
Simulation time 92972710 ps
CPU time 0.76 seconds
Started Feb 29 12:48:21 PM PST 24
Finished Feb 29 12:48:22 PM PST 24
Peak memory 202152 kb
Host smart-2631b56e-9e87-40a4-ade3-e6d38d3cf6d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250361531 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3250361531
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2384388985
Short name T44
Test name
Test status
Simulation time 140196510 ps
CPU time 4.42 seconds
Started Feb 29 12:48:43 PM PST 24
Finished Feb 29 12:48:48 PM PST 24
Peak memory 202520 kb
Host smart-73bd03e0-2125-4684-925b-8405ee6d3512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384388985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.2384388985
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2130416969
Short name T945
Test name
Test status
Simulation time 297519882 ps
CPU time 1.54 seconds
Started Feb 29 12:48:37 PM PST 24
Finished Feb 29 12:48:39 PM PST 24
Peak memory 202352 kb
Host smart-25fda6a4-84ce-4bb2-aef3-9758a5e806f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130416969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.2130416969
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1324447519
Short name T957
Test name
Test status
Simulation time 17642575 ps
CPU time 0.65 seconds
Started Feb 29 12:48:15 PM PST 24
Finished Feb 29 12:48:16 PM PST 24
Peak memory 202096 kb
Host smart-7277fd06-e3ce-497e-9193-7f1b665d70a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324447519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1324447519
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4114429545
Short name T909
Test name
Test status
Simulation time 1653253311 ps
CPU time 5.14 seconds
Started Feb 29 12:48:23 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 202432 kb
Host smart-98b5d4f4-372a-4887-815a-6ea55492eb0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114429545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.4114429545
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1758508169
Short name T59
Test name
Test status
Simulation time 21123295 ps
CPU time 0.73 seconds
Started Feb 29 12:48:39 PM PST 24
Finished Feb 29 12:48:40 PM PST 24
Peak memory 202124 kb
Host smart-ada59d1b-2c84-40b0-9b71-66cdac82a4a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758508169 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1758508169
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2310116319
Short name T938
Test name
Test status
Simulation time 137773394 ps
CPU time 4.09 seconds
Started Feb 29 12:48:43 PM PST 24
Finished Feb 29 12:48:47 PM PST 24
Peak memory 202316 kb
Host smart-0200417d-d6f0-41c1-9372-7f72895c2c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310116319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.2310116319
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3066851604
Short name T99
Test name
Test status
Simulation time 277861743 ps
CPU time 1.38 seconds
Started Feb 29 12:48:25 PM PST 24
Finished Feb 29 12:48:26 PM PST 24
Peak memory 202392 kb
Host smart-c7ff9806-fb5d-4a12-bed6-275117aefbba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066851604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3066851604
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1378699900
Short name T922
Test name
Test status
Simulation time 13257355 ps
CPU time 0.7 seconds
Started Feb 29 12:48:10 PM PST 24
Finished Feb 29 12:48:11 PM PST 24
Peak memory 202144 kb
Host smart-d7416727-19ba-4d39-b20f-f07eb3b6d278
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378699900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.1378699900
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3081376268
Short name T919
Test name
Test status
Simulation time 450238476 ps
CPU time 2.36 seconds
Started Feb 29 12:48:41 PM PST 24
Finished Feb 29 12:48:43 PM PST 24
Peak memory 202220 kb
Host smart-ded6eaaa-9904-4dbb-ada7-0657ea9211c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081376268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.3081376268
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1145145973
Short name T890
Test name
Test status
Simulation time 18698836 ps
CPU time 0.63 seconds
Started Feb 29 12:48:16 PM PST 24
Finished Feb 29 12:48:17 PM PST 24
Peak memory 201016 kb
Host smart-149768b9-fb5f-4fd4-9e94-4a8645c4255a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145145973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.1145145973
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2480916469
Short name T60
Test name
Test status
Simulation time 40468394 ps
CPU time 0.66 seconds
Started Feb 29 12:48:24 PM PST 24
Finished Feb 29 12:48:25 PM PST 24
Peak memory 202192 kb
Host smart-47330ed2-5d65-47e1-a80f-7f2c3adb3a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480916469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.2480916469
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.421146421
Short name T70
Test name
Test status
Simulation time 217033463 ps
CPU time 2.72 seconds
Started Feb 29 12:48:12 PM PST 24
Finished Feb 29 12:48:15 PM PST 24
Peak memory 202376 kb
Host smart-3727a0e1-67f9-4d8c-a41b-a73d38e64fdf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421146421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.421146421
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1254342331
Short name T61
Test name
Test status
Simulation time 35688041 ps
CPU time 0.71 seconds
Started Feb 29 12:48:17 PM PST 24
Finished Feb 29 12:48:19 PM PST 24
Peak memory 202060 kb
Host smart-4180b833-0f9c-4099-96f6-6b425faae97f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254342331 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1254342331
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.68590997
Short name T923
Test name
Test status
Simulation time 139128540 ps
CPU time 3.83 seconds
Started Feb 29 12:48:22 PM PST 24
Finished Feb 29 12:48:26 PM PST 24
Peak memory 202428 kb
Host smart-4a557b36-1032-4bb1-a1f8-df7ffe95ecc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68590997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_tl_errors.68590997
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2551742707
Short name T47
Test name
Test status
Simulation time 170980968 ps
CPU time 2.29 seconds
Started Feb 29 12:48:25 PM PST 24
Finished Feb 29 12:48:39 PM PST 24
Peak memory 202300 kb
Host smart-c03d4130-f58a-403d-a075-b3ef3e3a8cab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551742707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2551742707
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.545982406
Short name T930
Test name
Test status
Simulation time 50110614 ps
CPU time 0.68 seconds
Started Feb 29 12:48:15 PM PST 24
Finished Feb 29 12:48:16 PM PST 24
Peak memory 201104 kb
Host smart-b787699c-0e79-445c-b33a-54d5a9b681cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545982406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_aliasing.545982406
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3321543566
Short name T932
Test name
Test status
Simulation time 76122044 ps
CPU time 1.22 seconds
Started Feb 29 12:48:07 PM PST 24
Finished Feb 29 12:48:09 PM PST 24
Peak memory 202312 kb
Host smart-b6e95cdd-1a17-48fc-a72a-fd3428093420
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321543566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.3321543566
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1177991633
Short name T915
Test name
Test status
Simulation time 55907646 ps
CPU time 0.63 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 202148 kb
Host smart-0703b452-c841-48e2-8d19-b915be6d3109
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177991633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.1177991633
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.85814869
Short name T910
Test name
Test status
Simulation time 40879368 ps
CPU time 0.64 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 201932 kb
Host smart-eda9c428-e858-4feb-acaa-a3976ecc4110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85814869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.sram_ctrl_csr_rw.85814869
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.607327989
Short name T939
Test name
Test status
Simulation time 4307999482 ps
CPU time 5.03 seconds
Started Feb 29 12:48:22 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 202588 kb
Host smart-23082483-7edb-4459-b433-b2f4cf778422
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607327989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.607327989
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1227076043
Short name T927
Test name
Test status
Simulation time 88714499 ps
CPU time 0.75 seconds
Started Feb 29 12:48:26 PM PST 24
Finished Feb 29 12:48:27 PM PST 24
Peak memory 202132 kb
Host smart-07b218a9-ae23-4cda-9c90-d5607cb7dd8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227076043 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1227076043
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3120341224
Short name T937
Test name
Test status
Simulation time 40935186 ps
CPU time 2.97 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 202604 kb
Host smart-13f2d5c5-d85f-4f8e-8fd8-00ce9039e2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120341224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.3120341224
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3679458410
Short name T102
Test name
Test status
Simulation time 993119579 ps
CPU time 2.26 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 202316 kb
Host smart-c070635b-d321-4c92-9c26-1faf9575973d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679458410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.3679458410
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1392724148
Short name T54
Test name
Test status
Simulation time 18953719 ps
CPU time 0.72 seconds
Started Feb 29 12:48:47 PM PST 24
Finished Feb 29 12:48:54 PM PST 24
Peak memory 202008 kb
Host smart-7ec51cd0-1e98-4690-ac1d-581fe0c23a12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392724148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.1392724148
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1159183602
Short name T921
Test name
Test status
Simulation time 39080322 ps
CPU time 1.26 seconds
Started Feb 29 12:48:38 PM PST 24
Finished Feb 29 12:48:40 PM PST 24
Peak memory 202508 kb
Host smart-dd60bb92-59aa-4fb3-80e2-921c92050113
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159183602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.1159183602
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2050412855
Short name T943
Test name
Test status
Simulation time 25713787 ps
CPU time 0.65 seconds
Started Feb 29 12:48:30 PM PST 24
Finished Feb 29 12:48:30 PM PST 24
Peak memory 201316 kb
Host smart-412037d6-431b-45ac-bd3a-9ec154d31093
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050412855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.2050412855
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.295495173
Short name T956
Test name
Test status
Simulation time 23639108 ps
CPU time 0.63 seconds
Started Feb 29 12:48:12 PM PST 24
Finished Feb 29 12:48:12 PM PST 24
Peak memory 201084 kb
Host smart-9e025fca-f237-4dbc-9dc4-7041852943ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295495173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.sram_ctrl_csr_rw.295495173
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2201649774
Short name T83
Test name
Test status
Simulation time 260965907 ps
CPU time 6.51 seconds
Started Feb 29 12:48:29 PM PST 24
Finished Feb 29 12:48:36 PM PST 24
Peak memory 202508 kb
Host smart-55a02f91-6ae7-4f95-83ff-cb744c457fa4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201649774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2201649774
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2168408564
Short name T926
Test name
Test status
Simulation time 55105034 ps
CPU time 0.67 seconds
Started Feb 29 12:48:48 PM PST 24
Finished Feb 29 12:48:50 PM PST 24
Peak memory 202140 kb
Host smart-d513a150-4f51-4f3d-b758-98132aa11dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168408564 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2168408564
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4033620819
Short name T894
Test name
Test status
Simulation time 144639353 ps
CPU time 4.9 seconds
Started Feb 29 12:48:26 PM PST 24
Finished Feb 29 12:48:31 PM PST 24
Peak memory 202436 kb
Host smart-4d6d850a-8d02-4bec-b55e-694815f107b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033620819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.4033620819
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.257372213
Short name T29
Test name
Test status
Simulation time 89352500 ps
CPU time 1.57 seconds
Started Feb 29 12:48:36 PM PST 24
Finished Feb 29 12:48:39 PM PST 24
Peak memory 202572 kb
Host smart-ad673009-6058-4d3d-ba79-41be070e3153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257372213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.sram_ctrl_tl_intg_err.257372213
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3693506147
Short name T904
Test name
Test status
Simulation time 94394982 ps
CPU time 0.63 seconds
Started Feb 29 12:48:27 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 202128 kb
Host smart-0e2c2aec-b513-4de1-a2a3-bfcc5c56a61f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693506147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3693506147
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2578052264
Short name T77
Test name
Test status
Simulation time 676241044 ps
CPU time 9.76 seconds
Started Feb 29 12:48:05 PM PST 24
Finished Feb 29 12:48:16 PM PST 24
Peak memory 202480 kb
Host smart-1a64b283-07f2-4ce2-86dd-ce51f20c32e2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578052264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2578052264
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.583256265
Short name T908
Test name
Test status
Simulation time 29138333 ps
CPU time 0.73 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 202124 kb
Host smart-a05b9d68-d501-43f6-b0b0-6883bad1d904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583256265 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.583256265
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.25804773
Short name T948
Test name
Test status
Simulation time 330725009 ps
CPU time 2.92 seconds
Started Feb 29 12:48:46 PM PST 24
Finished Feb 29 12:48:51 PM PST 24
Peak memory 202464 kb
Host smart-785bd820-887f-4bf4-918a-f690959014a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25804773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_tl_errors.25804773
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3964038281
Short name T903
Test name
Test status
Simulation time 103761795 ps
CPU time 1.59 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 202336 kb
Host smart-2e65432c-568e-452e-a300-1bf4d421ac49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964038281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.3964038281
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.935778141
Short name T69
Test name
Test status
Simulation time 18836224 ps
CPU time 0.69 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:47:59 PM PST 24
Peak memory 201076 kb
Host smart-1feae62b-cac5-48ac-824f-82e661842815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935778141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.935778141
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1617264152
Short name T942
Test name
Test status
Simulation time 1321811680 ps
CPU time 5.16 seconds
Started Feb 29 12:48:23 PM PST 24
Finished Feb 29 12:48:29 PM PST 24
Peak memory 202448 kb
Host smart-6ab26652-185c-4aad-b157-1329da3efc7c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617264152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.1617264152
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.191849614
Short name T899
Test name
Test status
Simulation time 18688671 ps
CPU time 0.69 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 200924 kb
Host smart-9dca678b-b9b2-4cc0-8653-a4c83b4f0530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191849614 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.191849614
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3028196504
Short name T928
Test name
Test status
Simulation time 78300680 ps
CPU time 3.45 seconds
Started Feb 29 12:48:05 PM PST 24
Finished Feb 29 12:48:09 PM PST 24
Peak memory 202428 kb
Host smart-8db9b19b-1fa3-4de2-a5ec-4b24a1ec0544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028196504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.3028196504
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2975056271
Short name T933
Test name
Test status
Simulation time 30183686 ps
CPU time 0.63 seconds
Started Feb 29 12:48:47 PM PST 24
Finished Feb 29 12:48:49 PM PST 24
Peak memory 201992 kb
Host smart-9c3d73ee-2fd2-4a0e-aa17-3866e8f87d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975056271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.2975056271
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.371522593
Short name T905
Test name
Test status
Simulation time 855658317 ps
CPU time 3.03 seconds
Started Feb 29 12:48:24 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 202504 kb
Host smart-4facba09-e55f-4949-a8be-ca463426f308
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371522593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.371522593
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1416145457
Short name T896
Test name
Test status
Simulation time 21447985 ps
CPU time 0.77 seconds
Started Feb 29 12:48:08 PM PST 24
Finished Feb 29 12:48:09 PM PST 24
Peak memory 202076 kb
Host smart-e9a55a2d-00ad-4de4-8e72-e4d3eae3bad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416145457 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1416145457
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1509055082
Short name T45
Test name
Test status
Simulation time 40186772 ps
CPU time 4.07 seconds
Started Feb 29 12:48:18 PM PST 24
Finished Feb 29 12:48:23 PM PST 24
Peak memory 202400 kb
Host smart-d8fc1904-ebf7-42ee-a283-f28cc03664ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509055082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.1509055082
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2878071177
Short name T51
Test name
Test status
Simulation time 783446925 ps
CPU time 2.6 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 202384 kb
Host smart-f49cdc68-a30e-4579-b234-e85bc8dd4ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878071177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.2878071177
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3283591425
Short name T947
Test name
Test status
Simulation time 31096033 ps
CPU time 0.65 seconds
Started Feb 29 12:48:34 PM PST 24
Finished Feb 29 12:48:35 PM PST 24
Peak memory 202200 kb
Host smart-448f2e8c-9644-4e55-b05e-ea86923c1310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283591425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.3283591425
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.244232256
Short name T66
Test name
Test status
Simulation time 796309659 ps
CPU time 4.56 seconds
Started Feb 29 12:48:07 PM PST 24
Finished Feb 29 12:48:12 PM PST 24
Peak memory 202432 kb
Host smart-4abb87f5-49da-4abe-989a-996415931088
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244232256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.244232256
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1600332326
Short name T906
Test name
Test status
Simulation time 22103878 ps
CPU time 0.78 seconds
Started Feb 29 12:48:17 PM PST 24
Finished Feb 29 12:48:18 PM PST 24
Peak memory 202180 kb
Host smart-a48a2feb-b08f-4583-898c-f4821662af63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600332326 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1600332326
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1898149655
Short name T42
Test name
Test status
Simulation time 133393540 ps
CPU time 4.23 seconds
Started Feb 29 12:48:31 PM PST 24
Finished Feb 29 12:48:36 PM PST 24
Peak memory 210508 kb
Host smart-1f871e81-0e8f-43ae-b069-7db8f378ad6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898149655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.1898149655
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2113854660
Short name T941
Test name
Test status
Simulation time 567943414 ps
CPU time 2.38 seconds
Started Feb 29 12:48:33 PM PST 24
Finished Feb 29 12:48:36 PM PST 24
Peak memory 202580 kb
Host smart-5873cdde-5e83-4126-bb5f-688aacfe21cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113854660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.2113854660
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.836894339
Short name T940
Test name
Test status
Simulation time 17458775 ps
CPU time 0.64 seconds
Started Feb 29 12:48:20 PM PST 24
Finished Feb 29 12:48:21 PM PST 24
Peak memory 201040 kb
Host smart-fbc82e92-8c59-4393-937b-d181111d6c42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836894339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_csr_rw.836894339
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.967698491
Short name T53
Test name
Test status
Simulation time 1543467008 ps
CPU time 4.94 seconds
Started Feb 29 12:48:43 PM PST 24
Finished Feb 29 12:48:50 PM PST 24
Peak memory 202376 kb
Host smart-66edab92-f8a3-4a12-bc09-de8b06b2be05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967698491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.967698491
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3250223353
Short name T918
Test name
Test status
Simulation time 53036281 ps
CPU time 0.79 seconds
Started Feb 29 12:48:17 PM PST 24
Finished Feb 29 12:48:19 PM PST 24
Peak memory 202372 kb
Host smart-1c121d35-232c-4427-86da-e013a7efc021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250223353 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3250223353
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4003500330
Short name T46
Test name
Test status
Simulation time 33738306 ps
CPU time 2.5 seconds
Started Feb 29 12:48:31 PM PST 24
Finished Feb 29 12:48:35 PM PST 24
Peak memory 202416 kb
Host smart-3b9cacc2-8c44-487e-8d85-fa5c202de38f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003500330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.4003500330
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1105447231
Short name T96
Test name
Test status
Simulation time 197392206 ps
CPU time 2.33 seconds
Started Feb 29 12:48:22 PM PST 24
Finished Feb 29 12:48:24 PM PST 24
Peak memory 202364 kb
Host smart-8b13d5e1-4793-48b8-9f13-7c7089277ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105447231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.1105447231
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1035635740
Short name T173
Test name
Test status
Simulation time 3509221299 ps
CPU time 1637.23 seconds
Started Feb 29 02:20:58 PM PST 24
Finished Feb 29 02:48:15 PM PST 24
Peak memory 373536 kb
Host smart-1f921a26-fa59-41ba-b46d-324a6054909b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035635740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1035635740
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.4164854225
Short name T811
Test name
Test status
Simulation time 21424097 ps
CPU time 0.66 seconds
Started Feb 29 02:20:54 PM PST 24
Finished Feb 29 02:20:55 PM PST 24
Peak memory 202436 kb
Host smart-799732ee-a32e-4a59-b41a-1066a8d8dc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164854225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.4164854225
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.2854968425
Short name T2
Test name
Test status
Simulation time 9774444597 ps
CPU time 53.91 seconds
Started Feb 29 02:20:53 PM PST 24
Finished Feb 29 02:21:47 PM PST 24
Peak memory 202728 kb
Host smart-d55e55f4-a781-494b-92a3-4fa2abeacf69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854968425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
2854968425
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.2054251853
Short name T614
Test name
Test status
Simulation time 15706984681 ps
CPU time 1298.72 seconds
Started Feb 29 02:20:52 PM PST 24
Finished Feb 29 02:42:32 PM PST 24
Peak memory 374484 kb
Host smart-a7499b81-9d9c-44e2-a268-7c1b9a205724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054251853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.2054251853
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.473831611
Short name T562
Test name
Test status
Simulation time 621656072 ps
CPU time 7.62 seconds
Started Feb 29 02:20:57 PM PST 24
Finished Feb 29 02:21:05 PM PST 24
Peak memory 210876 kb
Host smart-bc34e42a-927e-47bc-bdb9-bd7d16113734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473831611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca
lation.473831611
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.1477716031
Short name T531
Test name
Test status
Simulation time 39489323 ps
CPU time 2.48 seconds
Started Feb 29 02:20:53 PM PST 24
Finished Feb 29 02:20:56 PM PST 24
Peak memory 210892 kb
Host smart-e6353ac7-453f-4fe3-8599-0c71624a5d17
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477716031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.1477716031
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3159244601
Short name T784
Test name
Test status
Simulation time 182339195 ps
CPU time 3.44 seconds
Started Feb 29 02:20:55 PM PST 24
Finished Feb 29 02:20:59 PM PST 24
Peak memory 210892 kb
Host smart-6306f568-6e49-4e81-81f8-5981a7ef1599
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159244601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.3159244601
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1945474351
Short name T299
Test name
Test status
Simulation time 241190351 ps
CPU time 5.19 seconds
Started Feb 29 02:20:53 PM PST 24
Finished Feb 29 02:20:59 PM PST 24
Peak memory 202628 kb
Host smart-3d91b187-83e6-43ff-8aa7-d30e6ca59a5f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945474351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1945474351
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.2271964616
Short name T532
Test name
Test status
Simulation time 2440833299 ps
CPU time 1047.61 seconds
Started Feb 29 02:20:56 PM PST 24
Finished Feb 29 02:38:24 PM PST 24
Peak memory 374472 kb
Host smart-0e03e5ce-1fd8-46e1-a2ce-074314c88229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271964616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.2271964616
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.795638982
Short name T438
Test name
Test status
Simulation time 9399239770 ps
CPU time 12.72 seconds
Started Feb 29 02:20:53 PM PST 24
Finished Feb 29 02:21:07 PM PST 24
Peak memory 202696 kb
Host smart-4171e2a4-b95a-4fc4-894b-7db4e1825630
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795638982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.795638982
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3934629392
Short name T638
Test name
Test status
Simulation time 2434851874 ps
CPU time 167.53 seconds
Started Feb 29 02:20:57 PM PST 24
Finished Feb 29 02:23:45 PM PST 24
Peak memory 202748 kb
Host smart-b12a2764-3cc2-4269-9483-cd530ed43925
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934629392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.3934629392
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.889393321
Short name T440
Test name
Test status
Simulation time 27472819 ps
CPU time 0.83 seconds
Started Feb 29 02:20:54 PM PST 24
Finished Feb 29 02:20:55 PM PST 24
Peak memory 202644 kb
Host smart-d74feec6-05c9-4c9a-a29d-a04d21cdbdf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889393321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.889393321
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.4291967426
Short name T25
Test name
Test status
Simulation time 5594802174 ps
CPU time 294.38 seconds
Started Feb 29 02:20:52 PM PST 24
Finished Feb 29 02:25:47 PM PST 24
Peak memory 349960 kb
Host smart-afa86913-b44d-4c16-b736-ece3e5e46cbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291967426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.4291967426
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.347418283
Short name T34
Test name
Test status
Simulation time 109440298 ps
CPU time 1.83 seconds
Started Feb 29 02:20:54 PM PST 24
Finished Feb 29 02:20:56 PM PST 24
Peak memory 220916 kb
Host smart-9b9abfc6-55b2-45f3-b089-0079db2a8bed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347418283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_sec_cm.347418283
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2955072205
Short name T714
Test name
Test status
Simulation time 1271269369 ps
CPU time 76.12 seconds
Started Feb 29 02:20:56 PM PST 24
Finished Feb 29 02:22:13 PM PST 24
Peak memory 328420 kb
Host smart-d598b410-45ac-445d-b414-2af249d67d48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955072205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2955072205
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.4006446159
Short name T618
Test name
Test status
Simulation time 55336446018 ps
CPU time 3714.06 seconds
Started Feb 29 02:20:55 PM PST 24
Finished Feb 29 03:22:50 PM PST 24
Peak memory 373504 kb
Host smart-39584005-2eeb-44d8-a9c6-3b5b5e9ddad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006446159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.4006446159
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3301960805
Short name T483
Test name
Test status
Simulation time 10933780226 ps
CPU time 261.09 seconds
Started Feb 29 02:20:53 PM PST 24
Finished Feb 29 02:25:15 PM PST 24
Peak memory 202756 kb
Host smart-d37b230e-cb34-4660-b3a7-3c7d927953c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301960805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.3301960805
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.963863243
Short name T626
Test name
Test status
Simulation time 92339422 ps
CPU time 24.59 seconds
Started Feb 29 02:20:53 PM PST 24
Finished Feb 29 02:21:18 PM PST 24
Peak memory 272148 kb
Host smart-b876dfab-1bc6-4354-961c-fcb17d8d4275
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963863243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.963863243
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1053555436
Short name T665
Test name
Test status
Simulation time 11965405433 ps
CPU time 1113.12 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:39:44 PM PST 24
Peak memory 372508 kb
Host smart-b4e2e3f0-2002-48e9-9c7c-70f37ba3535a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053555436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.1053555436
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.209039249
Short name T720
Test name
Test status
Simulation time 40323691 ps
CPU time 0.66 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:21:12 PM PST 24
Peak memory 201684 kb
Host smart-1c72597a-9843-49ae-9830-912b0edf50a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209039249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.209039249
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.1132803538
Short name T854
Test name
Test status
Simulation time 493198896 ps
CPU time 15.7 seconds
Started Feb 29 02:20:56 PM PST 24
Finished Feb 29 02:21:12 PM PST 24
Peak memory 202680 kb
Host smart-105f4354-ce0f-4a3f-aa62-679b7ccf7ef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132803538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
1132803538
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.1638067075
Short name T567
Test name
Test status
Simulation time 12737277075 ps
CPU time 539.71 seconds
Started Feb 29 02:21:13 PM PST 24
Finished Feb 29 02:30:13 PM PST 24
Peak memory 357312 kb
Host smart-7d96b52d-648b-46e8-984f-b00533ed09a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638067075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.1638067075
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.1047524522
Short name T138
Test name
Test status
Simulation time 395776108 ps
CPU time 5.34 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:21:16 PM PST 24
Peak memory 213272 kb
Host smart-a784fe2b-dd91-447b-90a7-0bbec57961f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047524522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.1047524522
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.3403621506
Short name T745
Test name
Test status
Simulation time 126638794 ps
CPU time 116.75 seconds
Started Feb 29 02:20:57 PM PST 24
Finished Feb 29 02:22:54 PM PST 24
Peak memory 350604 kb
Host smart-22f9087f-12ee-4df1-821b-538176e60b3f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403621506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.3403621506
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.522028195
Short name T536
Test name
Test status
Simulation time 51788590 ps
CPU time 2.92 seconds
Started Feb 29 02:21:12 PM PST 24
Finished Feb 29 02:21:15 PM PST 24
Peak memory 215272 kb
Host smart-f9344a68-b35c-45cc-b5c0-26e742288728
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522028195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_mem_partial_access.522028195
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.1190797432
Short name T114
Test name
Test status
Simulation time 2053529945 ps
CPU time 5.83 seconds
Started Feb 29 02:21:12 PM PST 24
Finished Feb 29 02:21:18 PM PST 24
Peak memory 202568 kb
Host smart-c4718dea-c01f-4593-885a-20b94c4b52c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190797432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.1190797432
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2924436565
Short name T387
Test name
Test status
Simulation time 2945255533 ps
CPU time 85.75 seconds
Started Feb 29 02:20:57 PM PST 24
Finished Feb 29 02:22:23 PM PST 24
Peak memory 266056 kb
Host smart-17f6daee-703d-4368-a7dd-010bf974558c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924436565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2924436565
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.1763584362
Short name T770
Test name
Test status
Simulation time 133738747 ps
CPU time 7.31 seconds
Started Feb 29 02:20:56 PM PST 24
Finished Feb 29 02:21:04 PM PST 24
Peak memory 202692 kb
Host smart-44bcbf48-75b5-486d-afa6-ac5dcfc5dc39
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763584362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.1763584362
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.526271632
Short name T85
Test name
Test status
Simulation time 202142359950 ps
CPU time 338.19 seconds
Started Feb 29 02:20:57 PM PST 24
Finished Feb 29 02:26:36 PM PST 24
Peak memory 202700 kb
Host smart-7d5669e9-48be-41e7-8d4d-a3e35540aeed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526271632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.sram_ctrl_partial_access_b2b.526271632
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1786923577
Short name T799
Test name
Test status
Simulation time 85126351 ps
CPU time 0.91 seconds
Started Feb 29 02:21:09 PM PST 24
Finished Feb 29 02:21:10 PM PST 24
Peak memory 202676 kb
Host smart-3a7b2d9c-9688-4877-9c2e-f5e3bde3c7e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786923577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1786923577
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.4086732622
Short name T247
Test name
Test status
Simulation time 9856676211 ps
CPU time 814.63 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:34:44 PM PST 24
Peak memory 368212 kb
Host smart-caa6b740-60c1-4911-b018-727be5e50d5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086732622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.4086732622
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.2823089552
Short name T457
Test name
Test status
Simulation time 120164737 ps
CPU time 120.16 seconds
Started Feb 29 02:20:53 PM PST 24
Finished Feb 29 02:22:54 PM PST 24
Peak memory 348696 kb
Host smart-f2519f39-c4ca-47a8-97cf-20cbaa19a6f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823089552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2823089552
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1629275961
Short name T447
Test name
Test status
Simulation time 14742443311 ps
CPU time 4246.16 seconds
Started Feb 29 02:21:13 PM PST 24
Finished Feb 29 03:32:00 PM PST 24
Peak memory 372960 kb
Host smart-884b7d26-e5eb-41bc-bccb-7a7a3e909045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629275961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1629275961
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.645264622
Short name T208
Test name
Test status
Simulation time 2316131070 ps
CPU time 219.45 seconds
Started Feb 29 02:20:56 PM PST 24
Finished Feb 29 02:24:36 PM PST 24
Peak memory 202760 kb
Host smart-5cdd4f30-8891-4882-9472-5c77abe68573
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645264622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_stress_pipeline.645264622
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3690566201
Short name T184
Test name
Test status
Simulation time 100421784 ps
CPU time 33.77 seconds
Started Feb 29 02:21:12 PM PST 24
Finished Feb 29 02:21:46 PM PST 24
Peak memory 284492 kb
Host smart-ddf20dba-9317-4b3e-9884-07228d949ef6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690566201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3690566201
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.3271281239
Short name T796
Test name
Test status
Simulation time 22512676 ps
CPU time 0.67 seconds
Started Feb 29 02:21:34 PM PST 24
Finished Feb 29 02:21:35 PM PST 24
Peak memory 201480 kb
Host smart-54ec1c1e-fdca-457d-803e-95756098f8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271281239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.3271281239
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.2645099674
Short name T768
Test name
Test status
Simulation time 3520723821 ps
CPU time 60.87 seconds
Started Feb 29 02:21:39 PM PST 24
Finished Feb 29 02:22:40 PM PST 24
Peak memory 202888 kb
Host smart-50081eea-a1b1-4e45-9ff7-fa6f3b30244b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645099674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.2645099674
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.635457669
Short name T623
Test name
Test status
Simulation time 1774748431 ps
CPU time 547.2 seconds
Started Feb 29 02:21:35 PM PST 24
Finished Feb 29 02:30:42 PM PST 24
Peak memory 372236 kb
Host smart-f3067a6a-122c-486e-bff7-f72d6d04b7f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635457669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl
e.635457669
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.929988097
Short name T650
Test name
Test status
Simulation time 551015841 ps
CPU time 6.77 seconds
Started Feb 29 02:21:43 PM PST 24
Finished Feb 29 02:21:50 PM PST 24
Peak memory 202716 kb
Host smart-f829a35d-3135-44c6-ac5d-94b2d616e7d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929988097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc
alation.929988097
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.452010643
Short name T678
Test name
Test status
Simulation time 275671014 ps
CPU time 155.72 seconds
Started Feb 29 02:21:37 PM PST 24
Finished Feb 29 02:24:13 PM PST 24
Peak memory 356152 kb
Host smart-93e7eb38-4691-4e88-818e-65f6ef3ef7e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452010643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.sram_ctrl_max_throughput.452010643
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4079829531
Short name T213
Test name
Test status
Simulation time 142316003 ps
CPU time 3.5 seconds
Started Feb 29 02:21:39 PM PST 24
Finished Feb 29 02:21:43 PM PST 24
Peak memory 210996 kb
Host smart-80ac573a-e7ce-4fc8-a3bc-c96052175c18
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079829531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.4079829531
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.1375969524
Short name T510
Test name
Test status
Simulation time 1867539129 ps
CPU time 5.31 seconds
Started Feb 29 02:21:35 PM PST 24
Finished Feb 29 02:21:40 PM PST 24
Peak memory 202648 kb
Host smart-56aae752-7879-433a-a0c8-f246b4f6fccc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375969524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.1375969524
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.2821797291
Short name T176
Test name
Test status
Simulation time 11940008070 ps
CPU time 681.19 seconds
Started Feb 29 02:21:37 PM PST 24
Finished Feb 29 02:32:59 PM PST 24
Peak memory 373460 kb
Host smart-f3a4653b-9a27-4092-8694-f2d12f0da402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821797291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.2821797291
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.3609847812
Short name T349
Test name
Test status
Simulation time 203647521 ps
CPU time 11.1 seconds
Started Feb 29 02:21:37 PM PST 24
Finished Feb 29 02:21:48 PM PST 24
Peak memory 202832 kb
Host smart-609645ec-d3c9-4f31-9cbc-3b2740c349db
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609847812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.3609847812
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2149174820
Short name T459
Test name
Test status
Simulation time 10238741856 ps
CPU time 376.39 seconds
Started Feb 29 02:21:40 PM PST 24
Finished Feb 29 02:27:56 PM PST 24
Peak memory 202892 kb
Host smart-f3ad4994-4c97-42b4-8bab-33535122c2ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149174820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2149174820
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.3258880798
Short name T230
Test name
Test status
Simulation time 5849035318 ps
CPU time 457.64 seconds
Started Feb 29 02:21:42 PM PST 24
Finished Feb 29 02:29:20 PM PST 24
Peak memory 361708 kb
Host smart-bc14f6f1-1013-4641-b798-cbc22f805232
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258880798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3258880798
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.2124632941
Short name T829
Test name
Test status
Simulation time 1257702505 ps
CPU time 123.73 seconds
Started Feb 29 02:21:40 PM PST 24
Finished Feb 29 02:23:44 PM PST 24
Peak memory 358792 kb
Host smart-d9e4f87a-9c40-44ec-bd62-7abb82fdf91a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124632941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2124632941
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.3682363351
Short name T597
Test name
Test status
Simulation time 19055817886 ps
CPU time 3314.06 seconds
Started Feb 29 02:21:43 PM PST 24
Finished Feb 29 03:16:57 PM PST 24
Peak memory 373792 kb
Host smart-0966f096-f14b-453b-bc13-da49edace24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682363351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.3682363351
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3820581438
Short name T463
Test name
Test status
Simulation time 14648109471 ps
CPU time 359.39 seconds
Started Feb 29 02:21:39 PM PST 24
Finished Feb 29 02:27:39 PM PST 24
Peak memory 202728 kb
Host smart-d5098e3a-8c5a-4e43-a7f9-26a3351c6cbc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820581438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.3820581438
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.990483355
Short name T537
Test name
Test status
Simulation time 551430442 ps
CPU time 101.08 seconds
Started Feb 29 02:21:36 PM PST 24
Finished Feb 29 02:23:17 PM PST 24
Peak memory 346136 kb
Host smart-3c26c745-32f4-4f4a-b20b-f715dc95bc93
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990483355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.990483355
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.293053290
Short name T632
Test name
Test status
Simulation time 24500176913 ps
CPU time 1710.62 seconds
Started Feb 29 02:21:36 PM PST 24
Finished Feb 29 02:50:07 PM PST 24
Peak memory 370428 kb
Host smart-e88d6084-5786-4b20-a093-d4c38646aa5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293053290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_access_during_key_req.293053290
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.1273183368
Short name T759
Test name
Test status
Simulation time 18831101 ps
CPU time 0.64 seconds
Started Feb 29 02:21:39 PM PST 24
Finished Feb 29 02:21:40 PM PST 24
Peak memory 202420 kb
Host smart-4bbec53e-b4e1-484e-87d6-38462a0dd3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273183368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.1273183368
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.1778017491
Short name T64
Test name
Test status
Simulation time 6759341088 ps
CPU time 54.28 seconds
Started Feb 29 02:21:35 PM PST 24
Finished Feb 29 02:22:30 PM PST 24
Peak memory 202724 kb
Host smart-c78b5edd-d3ba-422b-9bb5-424cc84c7d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778017491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.1778017491
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.1206734680
Short name T388
Test name
Test status
Simulation time 1997748859 ps
CPU time 68.02 seconds
Started Feb 29 02:21:36 PM PST 24
Finished Feb 29 02:22:44 PM PST 24
Peak memory 309800 kb
Host smart-201c4579-9752-44c7-875c-3f9cafdf3b38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206734680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.1206734680
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1581294167
Short name T825
Test name
Test status
Simulation time 107253473 ps
CPU time 21.19 seconds
Started Feb 29 02:21:37 PM PST 24
Finished Feb 29 02:21:59 PM PST 24
Peak memory 268120 kb
Host smart-f803b97c-45a1-4be1-9d14-2abfbc5af4c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581294167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1581294167
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2853547605
Short name T11
Test name
Test status
Simulation time 96867110 ps
CPU time 3.36 seconds
Started Feb 29 02:21:39 PM PST 24
Finished Feb 29 02:21:43 PM PST 24
Peak memory 210812 kb
Host smart-1cbba4f8-41f6-41e9-999a-7b1a4e0cbe2b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853547605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.2853547605
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.2077479521
Short name T415
Test name
Test status
Simulation time 276606044 ps
CPU time 4.62 seconds
Started Feb 29 02:21:35 PM PST 24
Finished Feb 29 02:21:40 PM PST 24
Peak memory 202540 kb
Host smart-b712096b-b51c-4f56-ad1e-c975f2271c81
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077479521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.2077479521
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.593259199
Short name T139
Test name
Test status
Simulation time 29764077741 ps
CPU time 496.29 seconds
Started Feb 29 02:21:58 PM PST 24
Finished Feb 29 02:30:15 PM PST 24
Peak memory 345880 kb
Host smart-888795c2-6069-4d70-842a-1e8cfe6ca0c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593259199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip
le_keys.593259199
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.152166446
Short name T731
Test name
Test status
Simulation time 2320275583 ps
CPU time 21.27 seconds
Started Feb 29 02:21:35 PM PST 24
Finished Feb 29 02:21:57 PM PST 24
Peak memory 202768 kb
Host smart-13e3d12e-f0e5-4978-89a3-1c4d6dbeaf0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152166446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s
ram_ctrl_partial_access.152166446
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4264865361
Short name T87
Test name
Test status
Simulation time 26639104178 ps
CPU time 567.47 seconds
Started Feb 29 02:21:38 PM PST 24
Finished Feb 29 02:31:06 PM PST 24
Peak memory 202704 kb
Host smart-d1187b0c-9013-41d6-bc26-424419f9a873
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264865361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.4264865361
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.3325174842
Short name T33
Test name
Test status
Simulation time 27575704 ps
CPU time 1.15 seconds
Started Feb 29 02:21:39 PM PST 24
Finished Feb 29 02:21:40 PM PST 24
Peak memory 203048 kb
Host smart-2b75037c-5ee4-4634-8881-53fe02bf0ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325174842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3325174842
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.1745240798
Short name T18
Test name
Test status
Simulation time 24426125636 ps
CPU time 1830.19 seconds
Started Feb 29 02:21:44 PM PST 24
Finished Feb 29 02:52:14 PM PST 24
Peak memory 374496 kb
Host smart-28540f0e-3a00-4a60-be37-329df5aead7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745240798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1745240798
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.1704649120
Short name T290
Test name
Test status
Simulation time 77297423 ps
CPU time 1.95 seconds
Started Feb 29 02:21:38 PM PST 24
Finished Feb 29 02:21:41 PM PST 24
Peak memory 202604 kb
Host smart-a3824581-fefe-4739-b518-7154cbf6bf61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704649120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1704649120
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.648821722
Short name T789
Test name
Test status
Simulation time 25227261345 ps
CPU time 356.05 seconds
Started Feb 29 02:21:42 PM PST 24
Finished Feb 29 02:27:38 PM PST 24
Peak memory 374500 kb
Host smart-c877e8fc-cb7f-407e-9cfc-f80590011cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648821722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_stress_all.648821722
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.721374698
Short name T707
Test name
Test status
Simulation time 2855640265 ps
CPU time 293.14 seconds
Started Feb 29 02:21:34 PM PST 24
Finished Feb 29 02:26:27 PM PST 24
Peak memory 202812 kb
Host smart-66104fe5-8b21-43e3-9630-597427d24106
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721374698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_stress_pipeline.721374698
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3121319638
Short name T273
Test name
Test status
Simulation time 576740159 ps
CPU time 150.31 seconds
Started Feb 29 02:21:36 PM PST 24
Finished Feb 29 02:24:06 PM PST 24
Peak memory 351788 kb
Host smart-c54d8edc-0218-439a-9b4e-45cfa5259bd0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121319638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3121319638
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3526030123
Short name T488
Test name
Test status
Simulation time 719405750 ps
CPU time 543.25 seconds
Started Feb 29 02:21:55 PM PST 24
Finished Feb 29 02:30:58 PM PST 24
Peak memory 372364 kb
Host smart-ab9183ce-77b1-47ea-9fb7-158e776f302f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526030123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.3526030123
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.2265450203
Short name T413
Test name
Test status
Simulation time 34294027 ps
CPU time 0.64 seconds
Started Feb 29 02:22:03 PM PST 24
Finished Feb 29 02:22:04 PM PST 24
Peak memory 202464 kb
Host smart-784ae7dc-4562-4fca-9b8a-952460a3091c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265450203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.2265450203
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.3148385553
Short name T863
Test name
Test status
Simulation time 1110481898 ps
CPU time 69.16 seconds
Started Feb 29 02:21:37 PM PST 24
Finished Feb 29 02:22:47 PM PST 24
Peak memory 202708 kb
Host smart-8ff3867b-43eb-462e-a16c-8d54e648ad5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148385553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.3148385553
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.3883541668
Short name T654
Test name
Test status
Simulation time 10952670185 ps
CPU time 63.66 seconds
Started Feb 29 02:21:48 PM PST 24
Finished Feb 29 02:22:52 PM PST 24
Peak memory 264084 kb
Host smart-5fcd2538-ce6e-44e1-8036-585d6b6ea242
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883541668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.3883541668
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.2179538818
Short name T431
Test name
Test status
Simulation time 233614497 ps
CPU time 12.01 seconds
Started Feb 29 02:21:37 PM PST 24
Finished Feb 29 02:21:49 PM PST 24
Peak memory 251484 kb
Host smart-10f761f9-f4d5-42c3-a1fe-33741fc1fabd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179538818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.2179538818
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1270527602
Short name T284
Test name
Test status
Simulation time 102536948 ps
CPU time 3 seconds
Started Feb 29 02:21:55 PM PST 24
Finished Feb 29 02:21:58 PM PST 24
Peak memory 210868 kb
Host smart-1897519d-5e5f-4b5f-86f7-73b83196b5ca
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270527602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.1270527602
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.12889229
Short name T277
Test name
Test status
Simulation time 665163319 ps
CPU time 9.84 seconds
Started Feb 29 02:21:59 PM PST 24
Finished Feb 29 02:22:10 PM PST 24
Peak memory 202652 kb
Host smart-2a4f4c63-c771-46f0-acb8-32ec1f7a65ea
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_
mem_walk.12889229
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.1804452741
Short name T360
Test name
Test status
Simulation time 30086840147 ps
CPU time 1494.19 seconds
Started Feb 29 02:21:42 PM PST 24
Finished Feb 29 02:46:36 PM PST 24
Peak memory 373496 kb
Host smart-e94cc1a8-3da4-4341-84b4-aa7c2b8a4abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804452741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.1804452741
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.4039280442
Short name T640
Test name
Test status
Simulation time 167436549 ps
CPU time 102.29 seconds
Started Feb 29 02:21:36 PM PST 24
Finished Feb 29 02:23:18 PM PST 24
Peak memory 329928 kb
Host smart-08f0142a-3e32-4a82-8267-3839d90b41f3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039280442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.4039280442
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.436853497
Short name T399
Test name
Test status
Simulation time 79742175824 ps
CPU time 312.6 seconds
Started Feb 29 02:21:35 PM PST 24
Finished Feb 29 02:26:48 PM PST 24
Peak memory 202656 kb
Host smart-2b0e05eb-ba07-4713-913f-34775ceb6b62
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436853497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_partial_access_b2b.436853497
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.1159672335
Short name T545
Test name
Test status
Simulation time 28434939 ps
CPU time 1.12 seconds
Started Feb 29 02:22:03 PM PST 24
Finished Feb 29 02:22:05 PM PST 24
Peak memory 202920 kb
Host smart-000125a6-a86d-4b49-bd80-df78a12408fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159672335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1159672335
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.2708579005
Short name T542
Test name
Test status
Simulation time 5531008918 ps
CPU time 1030.86 seconds
Started Feb 29 02:21:48 PM PST 24
Finished Feb 29 02:38:59 PM PST 24
Peak memory 374428 kb
Host smart-501ba38e-202b-44b0-9dbe-620a38d6e69c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708579005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2708579005
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3920307089
Short name T555
Test name
Test status
Simulation time 2557009681 ps
CPU time 13.84 seconds
Started Feb 29 02:21:44 PM PST 24
Finished Feb 29 02:21:58 PM PST 24
Peak memory 202712 kb
Host smart-cc70f0a6-da03-491b-8ff8-ec8fd52651e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920307089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3920307089
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.2640733298
Short name T239
Test name
Test status
Simulation time 557966151622 ps
CPU time 5583.89 seconds
Started Feb 29 02:21:52 PM PST 24
Finished Feb 29 03:54:57 PM PST 24
Peak memory 373516 kb
Host smart-7440875b-5c0a-4d54-b7d5-a409ec9189ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640733298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.2640733298
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2677166832
Short name T381
Test name
Test status
Simulation time 3694104228 ps
CPU time 350.94 seconds
Started Feb 29 02:21:44 PM PST 24
Finished Feb 29 02:27:35 PM PST 24
Peak memory 202580 kb
Host smart-8050f869-98ce-4b1f-a914-fd1d32aac630
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677166832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.2677166832
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1536102782
Short name T245
Test name
Test status
Simulation time 257607282 ps
CPU time 10.28 seconds
Started Feb 29 02:21:48 PM PST 24
Finished Feb 29 02:21:59 PM PST 24
Peak memory 238964 kb
Host smart-62aebe90-998f-470a-ace7-86960daf7082
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536102782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1536102782
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2428563883
Short name T740
Test name
Test status
Simulation time 26750710947 ps
CPU time 1415.19 seconds
Started Feb 29 02:21:56 PM PST 24
Finished Feb 29 02:45:32 PM PST 24
Peak memory 375524 kb
Host smart-5122663b-6b8e-440e-a3b0-8dec25bdc157
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428563883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.2428563883
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.204919872
Short name T557
Test name
Test status
Simulation time 13925997 ps
CPU time 0.66 seconds
Started Feb 29 02:21:46 PM PST 24
Finished Feb 29 02:21:46 PM PST 24
Peak memory 202440 kb
Host smart-84dda0ea-84aa-4541-856f-8e9f5abdbe04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204919872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.204919872
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.701694218
Short name T219
Test name
Test status
Simulation time 16379523938 ps
CPU time 58.72 seconds
Started Feb 29 02:21:49 PM PST 24
Finished Feb 29 02:22:48 PM PST 24
Peak memory 202684 kb
Host smart-6ab49cb8-57ab-489c-a890-0c9fdbd193a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701694218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.
701694218
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.3351151286
Short name T551
Test name
Test status
Simulation time 715862838 ps
CPU time 122.52 seconds
Started Feb 29 02:21:50 PM PST 24
Finished Feb 29 02:23:53 PM PST 24
Peak memory 322484 kb
Host smart-bd4e734c-189a-49ae-ae2b-b427584314d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351151286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.3351151286
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.354511363
Short name T4
Test name
Test status
Simulation time 1864625151 ps
CPU time 7.63 seconds
Started Feb 29 02:22:03 PM PST 24
Finished Feb 29 02:22:12 PM PST 24
Peak memory 202580 kb
Host smart-e39edeb3-3c40-490d-a212-005402ebb895
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354511363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc
alation.354511363
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.3946790248
Short name T220
Test name
Test status
Simulation time 210070481 ps
CPU time 40.62 seconds
Started Feb 29 02:21:49 PM PST 24
Finished Feb 29 02:22:30 PM PST 24
Peak memory 317788 kb
Host smart-f3d69b87-7154-44c6-b417-cc056000e01e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946790248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.3946790248
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2629962859
Short name T524
Test name
Test status
Simulation time 163827323 ps
CPU time 3.13 seconds
Started Feb 29 02:22:03 PM PST 24
Finished Feb 29 02:22:07 PM PST 24
Peak memory 218916 kb
Host smart-685b6e08-425c-457b-bf16-a7047dabf4ea
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629962859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.2629962859
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.3215203019
Short name T186
Test name
Test status
Simulation time 141526132 ps
CPU time 7.9 seconds
Started Feb 29 02:21:57 PM PST 24
Finished Feb 29 02:22:05 PM PST 24
Peak memory 202604 kb
Host smart-7f2b2fba-ee8c-4429-b05d-7a8a5de41413
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215203019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.3215203019
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.1254933895
Short name T594
Test name
Test status
Simulation time 51559741666 ps
CPU time 1515.26 seconds
Started Feb 29 02:21:58 PM PST 24
Finished Feb 29 02:47:14 PM PST 24
Peak memory 375508 kb
Host smart-2ab0ba54-6069-48a6-bbbb-813471f93907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254933895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.1254933895
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.626439864
Short name T232
Test name
Test status
Simulation time 853016398 ps
CPU time 12.71 seconds
Started Feb 29 02:21:54 PM PST 24
Finished Feb 29 02:22:08 PM PST 24
Peak memory 242888 kb
Host smart-1c77a29e-8f58-4974-8a5c-e33796a039fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626439864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.s
ram_ctrl_partial_access.626439864
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2128478798
Short name T448
Test name
Test status
Simulation time 29836655029 ps
CPU time 187.95 seconds
Started Feb 29 02:21:53 PM PST 24
Finished Feb 29 02:25:01 PM PST 24
Peak memory 202756 kb
Host smart-bfa99e30-fbce-4dd5-80a6-ed19d3f6855b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128478798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.2128478798
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.654762282
Short name T708
Test name
Test status
Simulation time 52739526 ps
CPU time 0.85 seconds
Started Feb 29 02:21:53 PM PST 24
Finished Feb 29 02:21:54 PM PST 24
Peak memory 202608 kb
Host smart-ab1a9391-a99a-44ab-a1ac-bef0e7cb05e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654762282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.654762282
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.2546613493
Short name T598
Test name
Test status
Simulation time 14671768794 ps
CPU time 1649.18 seconds
Started Feb 29 02:21:54 PM PST 24
Finished Feb 29 02:49:23 PM PST 24
Peak memory 368364 kb
Host smart-dab79032-6dba-4f7f-a80e-2ef86c582ef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546613493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2546613493
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.2258858198
Short name T143
Test name
Test status
Simulation time 6995030562 ps
CPU time 16.53 seconds
Started Feb 29 02:21:53 PM PST 24
Finished Feb 29 02:22:10 PM PST 24
Peak memory 202720 kb
Host smart-ab5f16ea-6ff5-4bef-8f44-f29c5149c581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258858198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2258858198
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.1080384697
Short name T652
Test name
Test status
Simulation time 109716804269 ps
CPU time 4143.56 seconds
Started Feb 29 02:21:58 PM PST 24
Finished Feb 29 03:31:03 PM PST 24
Peak memory 374552 kb
Host smart-6e254138-8088-48b8-b756-d63e5c214d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080384697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.1080384697
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2720017934
Short name T206
Test name
Test status
Simulation time 14024132674 ps
CPU time 349.67 seconds
Started Feb 29 02:21:49 PM PST 24
Finished Feb 29 02:27:40 PM PST 24
Peak memory 202752 kb
Host smart-17255c9b-9071-410c-a6e6-7ec93401e304
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720017934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.2720017934
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3615089417
Short name T624
Test name
Test status
Simulation time 285122196 ps
CPU time 2.26 seconds
Started Feb 29 02:21:52 PM PST 24
Finished Feb 29 02:21:54 PM PST 24
Peak memory 210904 kb
Host smart-5b32edc1-8037-4a17-9d7d-40d605053b9b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615089417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3615089417
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1109845067
Short name T622
Test name
Test status
Simulation time 7366681465 ps
CPU time 162.91 seconds
Started Feb 29 02:22:02 PM PST 24
Finished Feb 29 02:24:46 PM PST 24
Peak memory 318444 kb
Host smart-c7e14b93-3ea0-4224-91bd-cab199131669
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109845067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1109845067
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.1389053913
Short name T566
Test name
Test status
Simulation time 33319371 ps
CPU time 0.67 seconds
Started Feb 29 02:22:01 PM PST 24
Finished Feb 29 02:22:03 PM PST 24
Peak memory 202404 kb
Host smart-caecdca3-0c27-4047-a9c2-6a6145d73586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389053913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.1389053913
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.1602542309
Short name T193
Test name
Test status
Simulation time 2194733505 ps
CPU time 39.92 seconds
Started Feb 29 02:22:04 PM PST 24
Finished Feb 29 02:22:44 PM PST 24
Peak memory 202752 kb
Host smart-07f4e387-8579-468e-9bf0-26ebd8cf7ddd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602542309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.1602542309
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.2008804847
Short name T649
Test name
Test status
Simulation time 1892614276 ps
CPU time 44.53 seconds
Started Feb 29 02:22:01 PM PST 24
Finished Feb 29 02:22:47 PM PST 24
Peak memory 270416 kb
Host smart-74f4f10f-c66b-4e53-9699-6c2a61933f50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008804847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.2008804847
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.1874539456
Short name T189
Test name
Test status
Simulation time 169489234 ps
CPU time 2.43 seconds
Started Feb 29 02:22:00 PM PST 24
Finished Feb 29 02:22:03 PM PST 24
Peak memory 210956 kb
Host smart-50063e40-a226-4edb-a33c-af91026edc2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874539456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.1874539456
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.158950425
Short name T814
Test name
Test status
Simulation time 97177714 ps
CPU time 5.84 seconds
Started Feb 29 02:22:03 PM PST 24
Finished Feb 29 02:22:09 PM PST 24
Peak memory 225980 kb
Host smart-4480bc19-b1b1-4530-bf88-598acf116574
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158950425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.sram_ctrl_max_throughput.158950425
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1539215617
Short name T657
Test name
Test status
Simulation time 91473744 ps
CPU time 2.8 seconds
Started Feb 29 02:22:01 PM PST 24
Finished Feb 29 02:22:05 PM PST 24
Peak memory 215476 kb
Host smart-2b31eb29-3b20-4849-9082-11c02f7b7839
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539215617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.1539215617
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.2472785971
Short name T472
Test name
Test status
Simulation time 464616966 ps
CPU time 9.2 seconds
Started Feb 29 02:22:06 PM PST 24
Finished Feb 29 02:22:15 PM PST 24
Peak memory 202628 kb
Host smart-3548d3b0-38f5-4d7a-991b-27284bb6a295
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472785971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.2472785971
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.75248936
Short name T677
Test name
Test status
Simulation time 16004514694 ps
CPU time 459.33 seconds
Started Feb 29 02:21:46 PM PST 24
Finished Feb 29 02:29:26 PM PST 24
Peak memory 360132 kb
Host smart-b16166a5-72fd-4be1-bc6c-07b98e12e4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75248936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multipl
e_keys.75248936
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.3826223892
Short name T702
Test name
Test status
Simulation time 178439890 ps
CPU time 76.74 seconds
Started Feb 29 02:22:02 PM PST 24
Finished Feb 29 02:23:19 PM PST 24
Peak memory 326276 kb
Host smart-0e0750ef-cdec-4e5f-a89c-71d2a55672c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826223892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.3826223892
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.4034719444
Short name T437
Test name
Test status
Simulation time 14883121873 ps
CPU time 259.59 seconds
Started Feb 29 02:22:01 PM PST 24
Finished Feb 29 02:26:22 PM PST 24
Peak memory 202736 kb
Host smart-75c08939-2cd6-4cf6-98c6-b9b0cba25017
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034719444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.4034719444
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.4011112909
Short name T769
Test name
Test status
Simulation time 90981102 ps
CPU time 1.06 seconds
Started Feb 29 02:22:03 PM PST 24
Finished Feb 29 02:22:05 PM PST 24
Peak memory 202864 kb
Host smart-d155ffe0-493d-47a3-8172-680d63ea251f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011112909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.4011112909
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.1415095610
Short name T417
Test name
Test status
Simulation time 13228678369 ps
CPU time 1214.77 seconds
Started Feb 29 02:22:01 PM PST 24
Finished Feb 29 02:42:17 PM PST 24
Peak memory 374516 kb
Host smart-740cf0da-862f-4559-8e05-425a2e28542a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415095610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1415095610
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.1774837773
Short name T807
Test name
Test status
Simulation time 105607278 ps
CPU time 2.19 seconds
Started Feb 29 02:22:00 PM PST 24
Finished Feb 29 02:22:04 PM PST 24
Peak memory 202664 kb
Host smart-843ea5c8-bd9e-401f-9944-fbcacdf07bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774837773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1774837773
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.2243304112
Short name T639
Test name
Test status
Simulation time 54416096177 ps
CPU time 1079.5 seconds
Started Feb 29 02:22:01 PM PST 24
Finished Feb 29 02:40:02 PM PST 24
Peak memory 374472 kb
Host smart-e76606e4-18b0-4c78-b427-2e65e7664007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243304112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.2243304112
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1518735275
Short name T231
Test name
Test status
Simulation time 7536516600 ps
CPU time 365.1 seconds
Started Feb 29 02:22:01 PM PST 24
Finished Feb 29 02:28:07 PM PST 24
Peak memory 202776 kb
Host smart-c2d01114-feac-4d15-9cbe-589ad2d46ab7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518735275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.1518735275
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2627698740
Short name T860
Test name
Test status
Simulation time 648116310 ps
CPU time 149.78 seconds
Started Feb 29 02:22:02 PM PST 24
Finished Feb 29 02:24:32 PM PST 24
Peak memory 373080 kb
Host smart-5b53a6b8-bdc3-44d4-ae45-72a2d4e2b02c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627698740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.2627698740
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3331268963
Short name T606
Test name
Test status
Simulation time 4611237951 ps
CPU time 670.78 seconds
Started Feb 29 02:22:13 PM PST 24
Finished Feb 29 02:33:24 PM PST 24
Peak memory 375572 kb
Host smart-79a2adff-fe86-4cba-af13-4d7beef6d81a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331268963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3331268963
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.650716097
Short name T571
Test name
Test status
Simulation time 12986520196 ps
CPU time 54.58 seconds
Started Feb 29 02:22:02 PM PST 24
Finished Feb 29 02:22:57 PM PST 24
Peak memory 202660 kb
Host smart-bc88d85a-8f1b-4b73-955a-380ac91353d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650716097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.
650716097
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.373868386
Short name T416
Test name
Test status
Simulation time 6769129597 ps
CPU time 961.53 seconds
Started Feb 29 02:22:13 PM PST 24
Finished Feb 29 02:38:15 PM PST 24
Peak memory 372416 kb
Host smart-844f40b6-cfd6-4aff-9d24-36469f55c562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373868386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executabl
e.373868386
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.1836598658
Short name T476
Test name
Test status
Simulation time 7966343675 ps
CPU time 13.23 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:22:25 PM PST 24
Peak memory 202800 kb
Host smart-04b01c4b-00e0-4bae-9b9e-5f1d97da82e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836598658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.1836598658
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.2417366869
Short name T306
Test name
Test status
Simulation time 462086936 ps
CPU time 78.69 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:23:31 PM PST 24
Peak memory 309420 kb
Host smart-8532c2d1-ba7b-4365-adb9-133032d4e2c1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417366869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.2417366869
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3078593639
Short name T194
Test name
Test status
Simulation time 157954913 ps
CPU time 5.73 seconds
Started Feb 29 02:22:13 PM PST 24
Finished Feb 29 02:22:19 PM PST 24
Peak memory 210876 kb
Host smart-dcdaa27e-d84c-42df-8961-82ffa9a8b96e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078593639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3078593639
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.378946905
Short name T722
Test name
Test status
Simulation time 76235764 ps
CPU time 4.38 seconds
Started Feb 29 02:22:13 PM PST 24
Finished Feb 29 02:22:17 PM PST 24
Peak memory 202640 kb
Host smart-37aa24a5-903c-4811-a721-19474375000d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378946905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_mem_walk.378946905
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3587504222
Short name T141
Test name
Test status
Simulation time 59125308754 ps
CPU time 1056.7 seconds
Started Feb 29 02:22:02 PM PST 24
Finished Feb 29 02:39:40 PM PST 24
Peak memory 373388 kb
Host smart-d1f907d1-114e-458c-8155-b6c056beb6b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587504222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3587504222
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.3513094241
Short name T325
Test name
Test status
Simulation time 786871508 ps
CPU time 33.66 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:22:46 PM PST 24
Peak memory 291632 kb
Host smart-3bffd487-2166-4d9c-9027-c65d88a556f7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513094241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.3513094241
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3767125667
Short name T636
Test name
Test status
Simulation time 115971219176 ps
CPU time 372.3 seconds
Started Feb 29 02:22:16 PM PST 24
Finished Feb 29 02:28:28 PM PST 24
Peak memory 202748 kb
Host smart-13151a18-4b7c-4a21-bf05-e1b25c54db75
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767125667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.3767125667
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.450418513
Short name T32
Test name
Test status
Simulation time 28315248 ps
CPU time 0.88 seconds
Started Feb 29 02:22:11 PM PST 24
Finished Feb 29 02:22:12 PM PST 24
Peak memory 202692 kb
Host smart-43c37efc-3d7c-4938-b3d5-815f42e66dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450418513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.450418513
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.289930983
Short name T423
Test name
Test status
Simulation time 1490131906 ps
CPU time 600.32 seconds
Started Feb 29 02:22:13 PM PST 24
Finished Feb 29 02:32:13 PM PST 24
Peak memory 358768 kb
Host smart-7708844d-fb49-4b5f-b078-82a25b28ea17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289930983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.289930983
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.3407109262
Short name T238
Test name
Test status
Simulation time 235784629 ps
CPU time 4.73 seconds
Started Feb 29 02:22:02 PM PST 24
Finished Feb 29 02:22:07 PM PST 24
Peak memory 202624 kb
Host smart-f74070af-c8b3-41d1-bfdf-527624e5a034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407109262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3407109262
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.372724508
Short name T767
Test name
Test status
Simulation time 2484923429 ps
CPU time 236.89 seconds
Started Feb 29 02:22:04 PM PST 24
Finished Feb 29 02:26:01 PM PST 24
Peak memory 202756 kb
Host smart-7aca6ceb-1486-430c-92e6-0e45e7d705f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372724508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.372724508
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.173102547
Short name T355
Test name
Test status
Simulation time 2077047117 ps
CPU time 173.29 seconds
Started Feb 29 02:22:11 PM PST 24
Finished Feb 29 02:25:05 PM PST 24
Peak memory 367268 kb
Host smart-93a4f824-f7f0-480f-9b4d-e33b0e58575f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173102547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.173102547
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.4092197147
Short name T125
Test name
Test status
Simulation time 3806485681 ps
CPU time 314.08 seconds
Started Feb 29 02:22:14 PM PST 24
Finished Feb 29 02:27:28 PM PST 24
Peak memory 375068 kb
Host smart-bab7d781-412f-4eb7-b6a2-de52e11bbf2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092197147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.4092197147
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.1787657785
Short name T474
Test name
Test status
Simulation time 57119842 ps
CPU time 0.67 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:22:13 PM PST 24
Peak memory 202440 kb
Host smart-7e4b2cc0-da93-48b5-b4ae-f8687bafc968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787657785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.1787657785
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.2961892064
Short name T204
Test name
Test status
Simulation time 3736848604 ps
CPU time 83.8 seconds
Started Feb 29 02:22:11 PM PST 24
Finished Feb 29 02:23:35 PM PST 24
Peak memory 202688 kb
Host smart-6042c825-8ea4-458c-9dad-6101804f4905
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961892064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.2961892064
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.941697712
Short name T401
Test name
Test status
Simulation time 1392657719 ps
CPU time 7.38 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:22:20 PM PST 24
Peak memory 210888 kb
Host smart-39a50c7e-8e8e-4c95-974e-a9d04864b5ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941697712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc
alation.941697712
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.2349527393
Short name T822
Test name
Test status
Simulation time 216837656 ps
CPU time 75.41 seconds
Started Feb 29 02:22:11 PM PST 24
Finished Feb 29 02:23:26 PM PST 24
Peak memory 326124 kb
Host smart-7cb148f8-0fc2-4a97-a535-6ac5be557745
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349527393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.2349527393
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3673048624
Short name T200
Test name
Test status
Simulation time 376744246 ps
CPU time 5.85 seconds
Started Feb 29 02:22:14 PM PST 24
Finished Feb 29 02:22:20 PM PST 24
Peak memory 211848 kb
Host smart-ba4da99a-3e8c-4be0-a5e4-d9bbae299c54
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673048624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.3673048624
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.455237589
Short name T753
Test name
Test status
Simulation time 1341868744 ps
CPU time 9.94 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:22:23 PM PST 24
Peak memory 202620 kb
Host smart-9564f93b-19d9-48aa-8771-2bf3458bd53c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455237589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_mem_walk.455237589
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.3245062513
Short name T878
Test name
Test status
Simulation time 20183832803 ps
CPU time 514.51 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:30:47 PM PST 24
Peak memory 352192 kb
Host smart-fe58659a-3aa7-4f29-81f9-7f76f654112f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245062513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.3245062513
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.571742286
Short name T612
Test name
Test status
Simulation time 459555196 ps
CPU time 7.19 seconds
Started Feb 29 02:22:15 PM PST 24
Finished Feb 29 02:22:22 PM PST 24
Peak memory 202684 kb
Host smart-0a8874cf-2871-4aae-834e-ff540cbdeb89
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571742286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.571742286
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.366170809
Short name T421
Test name
Test status
Simulation time 108727427582 ps
CPU time 255.98 seconds
Started Feb 29 02:22:12 PM PST 24
Finished Feb 29 02:26:28 PM PST 24
Peak memory 202768 kb
Host smart-22472b23-16b6-4fe1-ab8f-96a6b25c1c7e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366170809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.sram_ctrl_partial_access_b2b.366170809
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3254037087
Short name T823
Test name
Test status
Simulation time 162275936 ps
CPU time 0.87 seconds
Started Feb 29 02:22:10 PM PST 24
Finished Feb 29 02:22:11 PM PST 24
Peak memory 202672 kb
Host smart-2ff4bceb-5525-458e-9751-0c6d1edb89d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254037087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3254037087
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.2251388945
Short name T788
Test name
Test status
Simulation time 55270544887 ps
CPU time 469.25 seconds
Started Feb 29 02:22:13 PM PST 24
Finished Feb 29 02:30:02 PM PST 24
Peak memory 374496 kb
Host smart-39299059-1ef4-4f3d-a3b5-9958ec1f13be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251388945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2251388945
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1155057163
Short name T498
Test name
Test status
Simulation time 126523976 ps
CPU time 17.66 seconds
Started Feb 29 02:22:14 PM PST 24
Finished Feb 29 02:22:32 PM PST 24
Peak memory 264308 kb
Host smart-d1d45521-0d7c-469d-821c-b389d1d21895
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155057163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1155057163
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.3644194097
Short name T519
Test name
Test status
Simulation time 184602806704 ps
CPU time 2387.44 seconds
Started Feb 29 02:22:18 PM PST 24
Finished Feb 29 03:02:06 PM PST 24
Peak memory 375524 kb
Host smart-7e164771-1688-4940-8dec-1c8c9640bd73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644194097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.3644194097
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1329391150
Short name T554
Test name
Test status
Simulation time 2013329789 ps
CPU time 209.47 seconds
Started Feb 29 02:22:11 PM PST 24
Finished Feb 29 02:25:40 PM PST 24
Peak memory 202720 kb
Host smart-e0bfb0dd-a939-4bf9-b8d2-2ed929fd0c7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329391150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.1329391150
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.62389076
Short name T757
Test name
Test status
Simulation time 155421970 ps
CPU time 137.28 seconds
Started Feb 29 02:22:13 PM PST 24
Finished Feb 29 02:24:31 PM PST 24
Peak memory 367652 kb
Host smart-f3f07498-e737-48f5-8358-0d4d6437b2a1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62389076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.sram_ctrl_throughput_w_partial_write.62389076
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3493283517
Short name T884
Test name
Test status
Simulation time 3043056940 ps
CPU time 750.8 seconds
Started Feb 29 02:22:26 PM PST 24
Finished Feb 29 02:34:57 PM PST 24
Peak memory 372780 kb
Host smart-b1301814-fdc6-425a-a180-95c4997b9e4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493283517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.3493283517
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.983764391
Short name T660
Test name
Test status
Simulation time 14104359 ps
CPU time 0.65 seconds
Started Feb 29 02:22:25 PM PST 24
Finished Feb 29 02:22:26 PM PST 24
Peak memory 202420 kb
Host smart-be4912ed-033b-4bd6-bc05-22a08a061883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983764391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.983764391
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.3938833071
Short name T680
Test name
Test status
Simulation time 1053147440 ps
CPU time 71.9 seconds
Started Feb 29 02:22:24 PM PST 24
Finished Feb 29 02:23:36 PM PST 24
Peak memory 202712 kb
Host smart-f4ab48a2-7689-4c08-9edf-d84414e6ec54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938833071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.3938833071
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.785678875
Short name T718
Test name
Test status
Simulation time 17829014172 ps
CPU time 459.12 seconds
Started Feb 29 02:22:22 PM PST 24
Finished Feb 29 02:30:02 PM PST 24
Peak memory 355116 kb
Host smart-da8fa887-7356-45de-999a-14858beef2b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785678875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl
e.785678875
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.362674545
Short name T234
Test name
Test status
Simulation time 1159520427 ps
CPU time 46.95 seconds
Started Feb 29 02:22:26 PM PST 24
Finished Feb 29 02:23:14 PM PST 24
Peak memory 284472 kb
Host smart-d424f852-65cb-4ce4-8932-64c225305afe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362674545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_max_throughput.362674545
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.829663398
Short name T275
Test name
Test status
Simulation time 93570542 ps
CPU time 3.31 seconds
Started Feb 29 02:22:23 PM PST 24
Finished Feb 29 02:22:27 PM PST 24
Peak memory 211040 kb
Host smart-c7bdf616-6069-44c4-b21c-dc145077dfa2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829663398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.829663398
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2934428785
Short name T579
Test name
Test status
Simulation time 584495706 ps
CPU time 5.73 seconds
Started Feb 29 02:22:24 PM PST 24
Finished Feb 29 02:22:30 PM PST 24
Peak memory 202608 kb
Host smart-4ab98efb-f619-4a8a-998c-1c03d7116195
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934428785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2934428785
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.3487466548
Short name T324
Test name
Test status
Simulation time 12745914015 ps
CPU time 1230.41 seconds
Started Feb 29 02:22:22 PM PST 24
Finished Feb 29 02:42:54 PM PST 24
Peak memory 374504 kb
Host smart-b00d8a45-c65b-4bba-9a01-2b37dcea2e4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487466548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.3487466548
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.3243259253
Short name T124
Test name
Test status
Simulation time 232742115 ps
CPU time 134.14 seconds
Started Feb 29 02:22:23 PM PST 24
Finished Feb 29 02:24:38 PM PST 24
Peak memory 362508 kb
Host smart-71fddd2b-0c4c-4c30-a58f-45595ad8838e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243259253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.3243259253
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.4162685434
Short name T375
Test name
Test status
Simulation time 105258069 ps
CPU time 0.84 seconds
Started Feb 29 02:22:22 PM PST 24
Finished Feb 29 02:22:24 PM PST 24
Peak memory 202664 kb
Host smart-3f342e9e-730e-491a-ae28-a5a6bff3cf3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162685434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.4162685434
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.2449792787
Short name T452
Test name
Test status
Simulation time 3826733838 ps
CPU time 278.63 seconds
Started Feb 29 02:22:23 PM PST 24
Finished Feb 29 02:27:02 PM PST 24
Peak memory 334364 kb
Host smart-f68fa9d8-ec41-4f5e-831e-322087f70287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449792787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2449792787
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.3322374727
Short name T580
Test name
Test status
Simulation time 6511110461 ps
CPU time 143.64 seconds
Started Feb 29 02:22:23 PM PST 24
Finished Feb 29 02:24:47 PM PST 24
Peak memory 358048 kb
Host smart-213eeb14-74e5-46e3-8be8-d7b39d0e1598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322374727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3322374727
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2287290803
Short name T471
Test name
Test status
Simulation time 1599832159 ps
CPU time 142.44 seconds
Started Feb 29 02:22:22 PM PST 24
Finished Feb 29 02:24:45 PM PST 24
Peak memory 202688 kb
Host smart-dc7ebee2-aed9-42e2-bef1-b8bd109d18fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287290803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.2287290803
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2669817553
Short name T487
Test name
Test status
Simulation time 140537500 ps
CPU time 99.32 seconds
Started Feb 29 02:22:22 PM PST 24
Finished Feb 29 02:24:02 PM PST 24
Peak memory 341656 kb
Host smart-ef21749c-7e8b-494d-af99-3e10902320de
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669817553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2669817553
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.4073679713
Short name T681
Test name
Test status
Simulation time 18340345699 ps
CPU time 782.18 seconds
Started Feb 29 02:22:26 PM PST 24
Finished Feb 29 02:35:29 PM PST 24
Peak memory 374228 kb
Host smart-12ccf645-07eb-485e-a08b-9d665b9bf3a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073679713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.4073679713
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.3898295804
Short name T843
Test name
Test status
Simulation time 15371947 ps
CPU time 0.68 seconds
Started Feb 29 02:22:37 PM PST 24
Finished Feb 29 02:22:38 PM PST 24
Peak memory 201536 kb
Host smart-48fec3c3-c968-4c18-b610-7ba88a1122d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898295804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.3898295804
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.3135309364
Short name T41
Test name
Test status
Simulation time 11559723130 ps
CPU time 64.31 seconds
Started Feb 29 02:22:25 PM PST 24
Finished Feb 29 02:23:30 PM PST 24
Peak memory 202664 kb
Host smart-7e2b7233-c5f6-41b3-a5a2-eb8f30fdf4b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135309364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.3135309364
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.709133538
Short name T301
Test name
Test status
Simulation time 1565547490 ps
CPU time 311.9 seconds
Started Feb 29 02:22:24 PM PST 24
Finished Feb 29 02:27:36 PM PST 24
Peak memory 317420 kb
Host smart-2d3a9188-8861-4f7e-a413-7435db04e6d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709133538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executabl
e.709133538
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.545370961
Short name T685
Test name
Test status
Simulation time 1015331604 ps
CPU time 13.58 seconds
Started Feb 29 02:22:24 PM PST 24
Finished Feb 29 02:22:38 PM PST 24
Peak memory 210892 kb
Host smart-b561ede7-3427-4ac4-914b-417ea0bf661a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545370961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.545370961
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.2819461328
Short name T568
Test name
Test status
Simulation time 52764383 ps
CPU time 3.97 seconds
Started Feb 29 02:22:25 PM PST 24
Finished Feb 29 02:22:30 PM PST 24
Peak memory 219028 kb
Host smart-96fc882e-06eb-450f-9111-ce9134dbb5e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819461328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.2819461328
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.477840262
Short name T601
Test name
Test status
Simulation time 175155322 ps
CPU time 6 seconds
Started Feb 29 02:22:36 PM PST 24
Finished Feb 29 02:22:42 PM PST 24
Peak memory 210808 kb
Host smart-16c09820-b7a9-41b8-9c5c-526ef0eb44fd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477840262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.sram_ctrl_mem_partial_access.477840262
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.2406041839
Short name T271
Test name
Test status
Simulation time 738269083 ps
CPU time 9.71 seconds
Started Feb 29 02:22:35 PM PST 24
Finished Feb 29 02:22:45 PM PST 24
Peak memory 202620 kb
Host smart-e406b326-06ce-4d6c-9934-dacf5c600f85
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406041839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.2406041839
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.416301871
Short name T426
Test name
Test status
Simulation time 17884419816 ps
CPU time 106.6 seconds
Started Feb 29 02:22:23 PM PST 24
Finished Feb 29 02:24:11 PM PST 24
Peak memory 308944 kb
Host smart-51f05868-6166-4a0f-ad75-83000b7f45a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416301871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.416301871
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.470992212
Short name T737
Test name
Test status
Simulation time 3667311855 ps
CPU time 20.14 seconds
Started Feb 29 02:22:26 PM PST 24
Finished Feb 29 02:22:46 PM PST 24
Peak memory 202720 kb
Host smart-12304f76-df37-4f09-b598-b728affc77ae
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470992212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s
ram_ctrl_partial_access.470992212
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1644336580
Short name T846
Test name
Test status
Simulation time 55682840239 ps
CPU time 278.17 seconds
Started Feb 29 02:22:26 PM PST 24
Finished Feb 29 02:27:05 PM PST 24
Peak memory 202888 kb
Host smart-4d0aa6e5-a79e-4cad-aa1b-afc7068056d4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644336580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.1644336580
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.1491747353
Short name T563
Test name
Test status
Simulation time 72968278 ps
CPU time 1.05 seconds
Started Feb 29 02:22:36 PM PST 24
Finished Feb 29 02:22:38 PM PST 24
Peak memory 202888 kb
Host smart-f49e2ff9-55e1-4cff-82e0-69abb37053ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491747353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1491747353
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.4213530170
Short name T322
Test name
Test status
Simulation time 6975540412 ps
CPU time 218.64 seconds
Started Feb 29 02:22:25 PM PST 24
Finished Feb 29 02:26:04 PM PST 24
Peak memory 346916 kb
Host smart-7e563f79-6d46-406e-a86d-fab76893a965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213530170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.4213530170
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.4192069369
Short name T874
Test name
Test status
Simulation time 2536498142 ps
CPU time 36.21 seconds
Started Feb 29 02:22:24 PM PST 24
Finished Feb 29 02:23:01 PM PST 24
Peak memory 283476 kb
Host smart-bc3bf0e2-8f5b-4a8c-86de-214f5fd42659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192069369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4192069369
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.1719875015
Short name T404
Test name
Test status
Simulation time 172500711439 ps
CPU time 2443.27 seconds
Started Feb 29 02:22:37 PM PST 24
Finished Feb 29 03:03:21 PM PST 24
Peak memory 373504 kb
Host smart-4fe5483f-1481-48b4-9d67-eae8c02b1752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719875015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.1719875015
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.4088362544
Short name T412
Test name
Test status
Simulation time 14777847190 ps
CPU time 359.22 seconds
Started Feb 29 02:22:25 PM PST 24
Finished Feb 29 02:28:25 PM PST 24
Peak memory 202776 kb
Host smart-777f6347-c1ad-43e8-be36-98d1bcb55c60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088362544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.4088362544
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1221165182
Short name T820
Test name
Test status
Simulation time 940702222 ps
CPU time 6.04 seconds
Started Feb 29 02:22:23 PM PST 24
Finished Feb 29 02:22:29 PM PST 24
Peak memory 224372 kb
Host smart-11300a8c-1173-40ea-82fa-2046a18932d7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221165182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1221165182
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3149770687
Short name T703
Test name
Test status
Simulation time 34134855159 ps
CPU time 1394.69 seconds
Started Feb 29 02:22:39 PM PST 24
Finished Feb 29 02:45:54 PM PST 24
Peak memory 373496 kb
Host smart-fb68df13-ff2f-4d1b-93c2-7d186331820d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149770687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3149770687
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2184727511
Short name T525
Test name
Test status
Simulation time 34257984 ps
CPU time 0.64 seconds
Started Feb 29 02:22:51 PM PST 24
Finished Feb 29 02:22:52 PM PST 24
Peak memory 202336 kb
Host smart-19985f8a-54de-4d37-9f99-0f3f56cd64f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184727511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2184727511
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.1160999791
Short name T653
Test name
Test status
Simulation time 1796008875 ps
CPU time 31.87 seconds
Started Feb 29 02:22:37 PM PST 24
Finished Feb 29 02:23:08 PM PST 24
Peak memory 202668 kb
Host smart-7f6c6426-2165-4865-b7fe-b576826ddebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160999791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.1160999791
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.2179064705
Short name T330
Test name
Test status
Simulation time 60747123727 ps
CPU time 971.16 seconds
Started Feb 29 02:22:37 PM PST 24
Finished Feb 29 02:38:49 PM PST 24
Peak memory 373516 kb
Host smart-4d36790c-7d77-4bc6-b5ed-44aec13986af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179064705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.2179064705
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.1746930630
Short name T309
Test name
Test status
Simulation time 3576180987 ps
CPU time 13.59 seconds
Started Feb 29 02:22:35 PM PST 24
Finished Feb 29 02:22:49 PM PST 24
Peak memory 210920 kb
Host smart-355063c0-0a08-41aa-a2c7-972937b08e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746930630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.1746930630
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.1928952884
Short name T698
Test name
Test status
Simulation time 138208224 ps
CPU time 15.58 seconds
Started Feb 29 02:22:39 PM PST 24
Finished Feb 29 02:22:55 PM PST 24
Peak memory 254060 kb
Host smart-f55e33f1-cbe3-4ef9-955d-02351b717a75
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928952884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.1928952884
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1997225943
Short name T509
Test name
Test status
Simulation time 91497430 ps
CPU time 3.21 seconds
Started Feb 29 02:22:38 PM PST 24
Finished Feb 29 02:22:41 PM PST 24
Peak memory 210908 kb
Host smart-c74a52b1-62f2-4100-a103-8a405da12f1a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997225943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.1997225943
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2522085004
Short name T593
Test name
Test status
Simulation time 1078341845 ps
CPU time 4.97 seconds
Started Feb 29 02:22:39 PM PST 24
Finished Feb 29 02:22:44 PM PST 24
Peak memory 202588 kb
Host smart-cf707e2b-8891-4f16-af2d-e577739c91c7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522085004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2522085004
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.2653413948
Short name T1
Test name
Test status
Simulation time 5497814979 ps
CPU time 944.74 seconds
Started Feb 29 02:22:38 PM PST 24
Finished Feb 29 02:38:23 PM PST 24
Peak memory 371444 kb
Host smart-faf0b17f-e47e-437b-808e-6ee209b1e682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653413948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.2653413948
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.829131835
Short name T617
Test name
Test status
Simulation time 646453549 ps
CPU time 28.78 seconds
Started Feb 29 02:22:38 PM PST 24
Finished Feb 29 02:23:07 PM PST 24
Peak memory 266004 kb
Host smart-b1860d4e-353d-477f-91ca-c8a4cfe5ceab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829131835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_partial_access.829131835
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2734157941
Short name T489
Test name
Test status
Simulation time 18619820247 ps
CPU time 410.86 seconds
Started Feb 29 02:22:37 PM PST 24
Finished Feb 29 02:29:28 PM PST 24
Peak memory 202756 kb
Host smart-7bf38987-7e56-4f56-9517-a6436f954b2f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734157941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.2734157941
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.1183014124
Short name T655
Test name
Test status
Simulation time 217087060 ps
CPU time 0.84 seconds
Started Feb 29 02:22:36 PM PST 24
Finished Feb 29 02:22:36 PM PST 24
Peak memory 202588 kb
Host smart-d12ce557-ab0c-4131-bbb5-52d8d386ed86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183014124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1183014124
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2115301489
Short name T478
Test name
Test status
Simulation time 13540936724 ps
CPU time 1007.37 seconds
Started Feb 29 02:22:38 PM PST 24
Finished Feb 29 02:39:25 PM PST 24
Peak memory 367516 kb
Host smart-a5bb9559-e5d1-482e-ab37-94d03875cb54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115301489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2115301489
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.662868672
Short name T119
Test name
Test status
Simulation time 813110117 ps
CPU time 18.02 seconds
Started Feb 29 02:22:37 PM PST 24
Finished Feb 29 02:22:55 PM PST 24
Peak memory 202692 kb
Host smart-cfb260b8-c2bf-4d7d-8ca4-8bd4b3063024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662868672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.662868672
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.1114460911
Short name T544
Test name
Test status
Simulation time 104334293286 ps
CPU time 4395.63 seconds
Started Feb 29 02:22:38 PM PST 24
Finished Feb 29 03:35:55 PM PST 24
Peak memory 382732 kb
Host smart-78ba3cff-524a-4b24-955f-7b936b9c4461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114460911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.1114460911
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1185792153
Short name T556
Test name
Test status
Simulation time 3386295056 ps
CPU time 318.57 seconds
Started Feb 29 02:22:40 PM PST 24
Finished Feb 29 02:27:58 PM PST 24
Peak memory 202716 kb
Host smart-1d8a5a18-fa73-4556-bd1e-5faeb8ee089d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185792153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.1185792153
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1639889891
Short name T278
Test name
Test status
Simulation time 75390116 ps
CPU time 2.74 seconds
Started Feb 29 02:22:39 PM PST 24
Finished Feb 29 02:22:42 PM PST 24
Peak memory 210884 kb
Host smart-cca8e4fa-46dc-42e6-b9e0-57ea8209eded
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639889891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1639889891
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3595598874
Short name T169
Test name
Test status
Simulation time 4068346196 ps
CPU time 1292.15 seconds
Started Feb 29 02:21:12 PM PST 24
Finished Feb 29 02:42:44 PM PST 24
Peak memory 375508 kb
Host smart-a21cedba-9295-4b10-81e5-72ce70d4dcef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595598874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.3595598874
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.4220659200
Short name T798
Test name
Test status
Simulation time 32651672 ps
CPU time 0.69 seconds
Started Feb 29 02:21:12 PM PST 24
Finished Feb 29 02:21:12 PM PST 24
Peak memory 201548 kb
Host smart-f77f95e5-7212-48ff-9d26-7ae330a297d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220659200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.4220659200
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.3548108377
Short name T742
Test name
Test status
Simulation time 353400927 ps
CPU time 24.58 seconds
Started Feb 29 02:21:09 PM PST 24
Finished Feb 29 02:21:34 PM PST 24
Peak memory 202684 kb
Host smart-d535a9c5-bec2-452e-8a4f-97666960e92c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548108377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
3548108377
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.1529637412
Short name T709
Test name
Test status
Simulation time 23975219493 ps
CPU time 932.33 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:36:43 PM PST 24
Peak memory 371360 kb
Host smart-b950b6b6-e4b5-43b2-bfae-9c0f68738696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529637412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.1529637412
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2676533163
Short name T276
Test name
Test status
Simulation time 1384978021 ps
CPU time 12.41 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:21:22 PM PST 24
Peak memory 210908 kb
Host smart-48378978-0728-46fa-acf6-2a863c3d91d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676533163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2676533163
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.171765065
Short name T747
Test name
Test status
Simulation time 670524135 ps
CPU time 65.76 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:22:16 PM PST 24
Peak memory 310668 kb
Host smart-2aef3d5b-4c2f-4aea-be9d-f5e861b94204
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171765065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.sram_ctrl_max_throughput.171765065
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2312529571
Short name T658
Test name
Test status
Simulation time 204962936 ps
CPU time 5.52 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:21:16 PM PST 24
Peak memory 215816 kb
Host smart-f9f1de59-c673-4d8a-9eac-31cfe495fd99
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312529571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.2312529571
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.868713798
Short name T700
Test name
Test status
Simulation time 550565515 ps
CPU time 8.42 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:21:19 PM PST 24
Peak memory 202656 kb
Host smart-de9c47bd-f4bf-4e13-b79a-0d1365fd676a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868713798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
mem_walk.868713798
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.905346687
Short name T442
Test name
Test status
Simulation time 190602172382 ps
CPU time 967.56 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:37:18 PM PST 24
Peak memory 374028 kb
Host smart-4169a05a-6365-48b7-8fca-f3db8dc60513
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905346687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multipl
e_keys.905346687
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.3212813917
Short name T771
Test name
Test status
Simulation time 696190643 ps
CPU time 4.15 seconds
Started Feb 29 02:21:09 PM PST 24
Finished Feb 29 02:21:14 PM PST 24
Peak memory 202620 kb
Host smart-a78ce697-b5ca-40f3-8871-deb8688d3d28
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212813917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.3212813917
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1917940087
Short name T518
Test name
Test status
Simulation time 54219107588 ps
CPU time 232.94 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:25:04 PM PST 24
Peak memory 202812 kb
Host smart-d182d47e-c56c-4d16-a697-e5e0dd5937f0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917940087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.1917940087
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.2264644463
Short name T876
Test name
Test status
Simulation time 83767219 ps
CPU time 0.86 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:21:12 PM PST 24
Peak memory 202624 kb
Host smart-1fd06276-ad6d-42e8-a84b-c12b84dc48b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264644463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2264644463
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.3782416384
Short name T674
Test name
Test status
Simulation time 7166433742 ps
CPU time 973.73 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:37:25 PM PST 24
Peak memory 372364 kb
Host smart-2f5cc8e7-10ee-4980-a9ca-38fde70a4328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782416384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3782416384
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.2096877831
Short name T35
Test name
Test status
Simulation time 203145654 ps
CPU time 1.82 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:21:12 PM PST 24
Peak memory 220816 kb
Host smart-604cd951-4cc4-4851-a95c-f18ac0bc9f2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096877831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.2096877831
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.951977663
Short name T502
Test name
Test status
Simulation time 3003285367 ps
CPU time 188.06 seconds
Started Feb 29 02:21:09 PM PST 24
Finished Feb 29 02:24:17 PM PST 24
Peak memory 370096 kb
Host smart-8cbf131a-60e1-40ca-b129-c220fdc6b154
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951977663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.951977663
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.1238144487
Short name T390
Test name
Test status
Simulation time 20526978889 ps
CPU time 3122.41 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 03:13:13 PM PST 24
Peak memory 382252 kb
Host smart-11f116aa-bf02-4bf3-8268-d80bd82a3d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238144487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.1238144487
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3731816498
Short name T828
Test name
Test status
Simulation time 1670855243 ps
CPU time 171.13 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:24:02 PM PST 24
Peak memory 202692 kb
Host smart-859010e7-c763-4d04-a44e-30e7655565b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731816498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.3731816498
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2018030410
Short name T530
Test name
Test status
Simulation time 242253549 ps
CPU time 63.98 seconds
Started Feb 29 02:21:13 PM PST 24
Finished Feb 29 02:22:17 PM PST 24
Peak memory 320156 kb
Host smart-3dee37a2-2584-4ff8-9505-a57931a0e592
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018030410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.2018030410
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2188114810
Short name T808
Test name
Test status
Simulation time 4531164619 ps
CPU time 1413.54 seconds
Started Feb 29 02:22:51 PM PST 24
Finished Feb 29 02:46:25 PM PST 24
Peak memory 373444 kb
Host smart-f56f67f6-4089-4dbc-8fef-3d6c917d5260
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188114810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2188114810
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1485239681
Short name T363
Test name
Test status
Simulation time 12190279 ps
CPU time 0.64 seconds
Started Feb 29 02:22:49 PM PST 24
Finished Feb 29 02:22:51 PM PST 24
Peak memory 202440 kb
Host smart-5d532567-fd10-4134-92c9-efed60eceb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485239681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1485239681
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.2056372046
Short name T386
Test name
Test status
Simulation time 1159034730 ps
CPU time 38.37 seconds
Started Feb 29 02:22:50 PM PST 24
Finished Feb 29 02:23:29 PM PST 24
Peak memory 202664 kb
Host smart-c784cea9-d94e-4b0f-ad4b-73039fe339b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056372046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.2056372046
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.1953444132
Short name T688
Test name
Test status
Simulation time 4814579729 ps
CPU time 1205.41 seconds
Started Feb 29 02:22:48 PM PST 24
Finished Feb 29 02:42:54 PM PST 24
Peak memory 374564 kb
Host smart-5f78ac95-ff6c-416f-879f-8d87f5e88673
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953444132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.1953444132
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.1709419968
Short name T695
Test name
Test status
Simulation time 430008022 ps
CPU time 6.31 seconds
Started Feb 29 02:22:48 PM PST 24
Finished Feb 29 02:22:56 PM PST 24
Peak memory 213184 kb
Host smart-5172fe25-5e4d-493d-969a-075010db92e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709419968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.1709419968
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.4252685534
Short name T592
Test name
Test status
Simulation time 1560761367 ps
CPU time 50.96 seconds
Started Feb 29 02:22:51 PM PST 24
Finished Feb 29 02:23:42 PM PST 24
Peak memory 304920 kb
Host smart-90179383-3121-4622-a78e-427d75f96557
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252685534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.4252685534
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3914238213
Short name T495
Test name
Test status
Simulation time 187792240 ps
CPU time 3.22 seconds
Started Feb 29 02:22:49 PM PST 24
Finished Feb 29 02:22:53 PM PST 24
Peak memory 211868 kb
Host smart-a1a472dc-18ca-4210-9ccc-e5f7496b7c6f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914238213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.3914238213
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.658557479
Short name T313
Test name
Test status
Simulation time 291857025 ps
CPU time 5.51 seconds
Started Feb 29 02:22:50 PM PST 24
Finished Feb 29 02:22:56 PM PST 24
Peak memory 202568 kb
Host smart-4d0c3562-3665-45c5-ba0a-f220680f5701
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658557479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_mem_walk.658557479
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.89947023
Short name T512
Test name
Test status
Simulation time 1548156336 ps
CPU time 255.07 seconds
Started Feb 29 02:22:48 PM PST 24
Finished Feb 29 02:27:03 PM PST 24
Peak memory 368200 kb
Host smart-7b11bc2a-8669-4103-9a4d-2171b3e44bba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89947023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multipl
e_keys.89947023
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1006152970
Short name T202
Test name
Test status
Simulation time 497348684 ps
CPU time 2.77 seconds
Started Feb 29 02:22:50 PM PST 24
Finished Feb 29 02:22:54 PM PST 24
Peak memory 202648 kb
Host smart-ee2a10d6-4a9f-4d69-9cce-a8b10f64a4dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006152970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1006152970
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1808645024
Short name T146
Test name
Test status
Simulation time 4715195549 ps
CPU time 317.54 seconds
Started Feb 29 02:22:49 PM PST 24
Finished Feb 29 02:28:07 PM PST 24
Peak memory 202756 kb
Host smart-086681bd-007e-406d-9de2-6b77e76e746e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808645024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.1808645024
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.1327958153
Short name T337
Test name
Test status
Simulation time 40717485 ps
CPU time 1.01 seconds
Started Feb 29 02:22:49 PM PST 24
Finished Feb 29 02:22:51 PM PST 24
Peak memory 202844 kb
Host smart-423de769-f380-4bd4-a9d0-e59f4483c4ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327958153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1327958153
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.4135681200
Short name T106
Test name
Test status
Simulation time 10297651015 ps
CPU time 1102.06 seconds
Started Feb 29 02:22:51 PM PST 24
Finished Feb 29 02:41:14 PM PST 24
Peak memory 374672 kb
Host smart-2cf868ec-4fb5-4b23-93f7-738fd6049c07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135681200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.4135681200
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.4094460815
Short name T115
Test name
Test status
Simulation time 2067864052 ps
CPU time 12.82 seconds
Started Feb 29 02:22:51 PM PST 24
Finished Feb 29 02:23:04 PM PST 24
Peak memory 202640 kb
Host smart-003d1dc7-3748-4d47-a377-54de0011a8f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094460815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4094460815
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.639473393
Short name T484
Test name
Test status
Simulation time 33091833887 ps
CPU time 3001.5 seconds
Started Feb 29 02:22:48 PM PST 24
Finished Feb 29 03:12:51 PM PST 24
Peak memory 374872 kb
Host smart-7f4a3220-13ad-4693-b4d1-5c4be057989b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639473393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_stress_all.639473393
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2311745705
Short name T265
Test name
Test status
Simulation time 1538539588 ps
CPU time 159.25 seconds
Started Feb 29 02:22:49 PM PST 24
Finished Feb 29 02:25:29 PM PST 24
Peak memory 202728 kb
Host smart-d45955cc-3e60-41d0-9acc-1b98cdcfc66c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311745705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.2311745705
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3166109331
Short name T596
Test name
Test status
Simulation time 521438848 ps
CPU time 122.33 seconds
Started Feb 29 02:22:53 PM PST 24
Finished Feb 29 02:24:56 PM PST 24
Peak memory 352652 kb
Host smart-c159d8f1-ae2e-4cf6-ac04-f64f4eb0cbe4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166109331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3166109331
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2097124162
Short name T699
Test name
Test status
Simulation time 5522518659 ps
CPU time 818.7 seconds
Started Feb 29 02:23:00 PM PST 24
Finished Feb 29 02:36:39 PM PST 24
Peak memory 373588 kb
Host smart-b32afca1-ac1a-4ee5-8705-089ffd9095f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097124162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.2097124162
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.546370117
Short name T475
Test name
Test status
Simulation time 32467080 ps
CPU time 0.62 seconds
Started Feb 29 02:23:07 PM PST 24
Finished Feb 29 02:23:08 PM PST 24
Peak memory 201732 kb
Host smart-fd9360c8-b3d0-4a56-81ce-08d2b75bd33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546370117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.546370117
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1502436949
Short name T565
Test name
Test status
Simulation time 3364088035 ps
CPU time 36.02 seconds
Started Feb 29 02:22:53 PM PST 24
Finished Feb 29 02:23:29 PM PST 24
Peak memory 202676 kb
Host smart-cbd3eed1-f6d1-4976-a268-452c077a1796
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502436949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1502436949
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.4099824450
Short name T561
Test name
Test status
Simulation time 4695442255 ps
CPU time 131.9 seconds
Started Feb 29 02:23:02 PM PST 24
Finished Feb 29 02:25:14 PM PST 24
Peak memory 293076 kb
Host smart-daf75def-b193-48b4-beeb-b32702d3b3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099824450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.4099824450
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.552216331
Short name T166
Test name
Test status
Simulation time 566234190 ps
CPU time 2.38 seconds
Started Feb 29 02:22:49 PM PST 24
Finished Feb 29 02:22:52 PM PST 24
Peak memory 210800 kb
Host smart-571922d3-3e42-4254-9152-45c05f14adf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552216331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc
alation.552216331
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.283683448
Short name T450
Test name
Test status
Simulation time 101174570 ps
CPU time 16.44 seconds
Started Feb 29 02:22:53 PM PST 24
Finished Feb 29 02:23:10 PM PST 24
Peak memory 251768 kb
Host smart-93b2088e-a93e-499e-97ce-4c2beb6eb54a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283683448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.283683448
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2630116729
Short name T296
Test name
Test status
Simulation time 67055723 ps
CPU time 5.45 seconds
Started Feb 29 02:23:03 PM PST 24
Finished Feb 29 02:23:09 PM PST 24
Peak memory 212096 kb
Host smart-81164039-9f7b-4413-888c-a233ad8783d7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630116729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.2630116729
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.2733400670
Short name T192
Test name
Test status
Simulation time 1001255002 ps
CPU time 4.74 seconds
Started Feb 29 02:23:02 PM PST 24
Finished Feb 29 02:23:07 PM PST 24
Peak memory 202600 kb
Host smart-725343f3-9ef7-46c6-bcf8-2599a162dc99
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733400670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.2733400670
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.1876071426
Short name T877
Test name
Test status
Simulation time 9123681004 ps
CPU time 1063.86 seconds
Started Feb 29 02:22:50 PM PST 24
Finished Feb 29 02:40:35 PM PST 24
Peak memory 371452 kb
Host smart-0fbc17fc-d207-4a9c-a385-91e7b4866f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876071426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.1876071426
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.3596027433
Short name T378
Test name
Test status
Simulation time 271406521 ps
CPU time 55.09 seconds
Started Feb 29 02:22:51 PM PST 24
Finished Feb 29 02:23:47 PM PST 24
Peak memory 303700 kb
Host smart-170ba351-1766-4e49-92ef-369dbe2ada81
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596027433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.3596027433
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3565819698
Short name T178
Test name
Test status
Simulation time 23512294883 ps
CPU time 264.17 seconds
Started Feb 29 02:22:49 PM PST 24
Finished Feb 29 02:27:14 PM PST 24
Peak memory 202740 kb
Host smart-0206b471-d9a5-4c05-9b1c-80c2f1a7f456
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565819698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.3565819698
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.2296672389
Short name T777
Test name
Test status
Simulation time 88221803 ps
CPU time 0.82 seconds
Started Feb 29 02:23:03 PM PST 24
Finished Feb 29 02:23:04 PM PST 24
Peak memory 202632 kb
Host smart-d7eddb7e-e6fa-4dc4-a973-284426191ac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296672389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2296672389
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.3961896760
Short name T853
Test name
Test status
Simulation time 1571980820 ps
CPU time 1007.62 seconds
Started Feb 29 02:23:05 PM PST 24
Finished Feb 29 02:39:53 PM PST 24
Peak memory 373296 kb
Host smart-6ff856d5-db2a-4c4a-b519-4f12f74587a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961896760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3961896760
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.2396279651
Short name T793
Test name
Test status
Simulation time 836411260 ps
CPU time 5.24 seconds
Started Feb 29 02:22:52 PM PST 24
Finished Feb 29 02:22:57 PM PST 24
Peak memory 202636 kb
Host smart-38bf4d08-db12-4851-b2f1-130d4f1560aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396279651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2396279651
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.4248679811
Short name T279
Test name
Test status
Simulation time 6503860091 ps
CPU time 2749.68 seconds
Started Feb 29 02:23:02 PM PST 24
Finished Feb 29 03:08:52 PM PST 24
Peak memory 373552 kb
Host smart-532953cd-e67f-4a61-a238-a2dfb5fcc257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248679811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.4248679811
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1150282751
Short name T216
Test name
Test status
Simulation time 12692506800 ps
CPU time 301 seconds
Started Feb 29 02:22:48 PM PST 24
Finished Feb 29 02:27:50 PM PST 24
Peak memory 202704 kb
Host smart-4a45ad4f-7a7f-451e-9b79-472fb2bc69ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150282751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.1150282751
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2064354645
Short name T398
Test name
Test status
Simulation time 211321728 ps
CPU time 104.56 seconds
Started Feb 29 02:22:51 PM PST 24
Finished Feb 29 02:24:36 PM PST 24
Peak memory 336344 kb
Host smart-5d8e67b6-3c2e-4c8c-8083-c7ad2a88005b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064354645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2064354645
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1232029760
Short name T888
Test name
Test status
Simulation time 15762204133 ps
CPU time 1127.19 seconds
Started Feb 29 02:23:01 PM PST 24
Finished Feb 29 02:41:48 PM PST 24
Peak memory 332972 kb
Host smart-3d77e64c-823e-4b9a-a0c5-9612e842b508
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232029760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.1232029760
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.2654719165
Short name T286
Test name
Test status
Simulation time 25987982 ps
CPU time 0.72 seconds
Started Feb 29 02:23:03 PM PST 24
Finished Feb 29 02:23:04 PM PST 24
Peak memory 201540 kb
Host smart-f81d1c62-e826-4658-b6f9-180d90652b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654719165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.2654719165
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.1577131750
Short name T201
Test name
Test status
Simulation time 1197183258 ps
CPU time 26.48 seconds
Started Feb 29 02:23:05 PM PST 24
Finished Feb 29 02:23:31 PM PST 24
Peak memory 202604 kb
Host smart-597fa61c-9524-4771-8d3d-461bda50521d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577131750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.1577131750
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.1580054818
Short name T706
Test name
Test status
Simulation time 39807086554 ps
CPU time 850.37 seconds
Started Feb 29 02:23:03 PM PST 24
Finished Feb 29 02:37:13 PM PST 24
Peak memory 372328 kb
Host smart-91b546c5-fd52-4c3d-a368-7808313332ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580054818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab
le.1580054818
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.2302169437
Short name T599
Test name
Test status
Simulation time 202944772 ps
CPU time 4.77 seconds
Started Feb 29 02:23:01 PM PST 24
Finished Feb 29 02:23:07 PM PST 24
Peak memory 202680 kb
Host smart-3ff4a253-2608-4e2f-a37f-2802a843a5b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302169437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.2302169437
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.3271891232
Short name T818
Test name
Test status
Simulation time 141057116 ps
CPU time 133.5 seconds
Started Feb 29 02:23:09 PM PST 24
Finished Feb 29 02:25:23 PM PST 24
Peak memory 369840 kb
Host smart-17ef88f2-0e06-49d0-ad44-53261aff2e49
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271891232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.3271891232
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2978729299
Short name T249
Test name
Test status
Simulation time 674522537 ps
CPU time 3.39 seconds
Started Feb 29 02:23:01 PM PST 24
Finished Feb 29 02:23:06 PM PST 24
Peak memory 210888 kb
Host smart-891f1110-c05d-4ba7-ba5f-10b26bf438eb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978729299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.2978729299
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3096096117
Short name T558
Test name
Test status
Simulation time 283270507 ps
CPU time 4.97 seconds
Started Feb 29 02:23:04 PM PST 24
Finished Feb 29 02:23:09 PM PST 24
Peak memory 202636 kb
Host smart-e48f24cf-54d6-499d-855e-d02ec24b9cee
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096096117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3096096117
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.428464811
Short name T629
Test name
Test status
Simulation time 7485461674 ps
CPU time 1351.65 seconds
Started Feb 29 02:23:02 PM PST 24
Finished Feb 29 02:45:34 PM PST 24
Peak memory 370488 kb
Host smart-968b031f-8b86-422e-af06-b7af06074091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428464811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip
le_keys.428464811
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.2944347230
Short name T373
Test name
Test status
Simulation time 347328474 ps
CPU time 13.69 seconds
Started Feb 29 02:23:02 PM PST 24
Finished Feb 29 02:23:16 PM PST 24
Peak memory 248416 kb
Host smart-928ce244-6c8d-4759-924c-4e8bc9bec0ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944347230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.2944347230
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.102769954
Short name T774
Test name
Test status
Simulation time 34763684891 ps
CPU time 216.66 seconds
Started Feb 29 02:23:08 PM PST 24
Finished Feb 29 02:26:45 PM PST 24
Peak memory 202796 kb
Host smart-7046cab9-2535-415c-85cd-f74774fe3f7d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102769954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.sram_ctrl_partial_access_b2b.102769954
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.1992040344
Short name T792
Test name
Test status
Simulation time 49019472 ps
CPU time 0.88 seconds
Started Feb 29 02:23:03 PM PST 24
Finished Feb 29 02:23:04 PM PST 24
Peak memory 202624 kb
Host smart-73978231-3947-41c4-8b0d-dee0dfe6aeed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992040344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1992040344
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.2484300871
Short name T122
Test name
Test status
Simulation time 657252155 ps
CPU time 1.58 seconds
Started Feb 29 02:23:03 PM PST 24
Finished Feb 29 02:23:05 PM PST 24
Peak memory 202648 kb
Host smart-c124a732-f828-4965-998f-1f60aea90679
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484300871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2484300871
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.2361399492
Short name T254
Test name
Test status
Simulation time 166305537135 ps
CPU time 2194.19 seconds
Started Feb 29 02:23:07 PM PST 24
Finished Feb 29 02:59:42 PM PST 24
Peak memory 370528 kb
Host smart-0db6e890-61cd-4085-b3c7-ae78971ab12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361399492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.2361399492
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2391384706
Short name T185
Test name
Test status
Simulation time 10377042854 ps
CPU time 238.07 seconds
Started Feb 29 02:23:01 PM PST 24
Finished Feb 29 02:27:00 PM PST 24
Peak memory 202752 kb
Host smart-78110895-b154-4614-a25e-a0089ec39991
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391384706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.2391384706
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.4023866033
Short name T533
Test name
Test status
Simulation time 287616196 ps
CPU time 4.97 seconds
Started Feb 29 02:23:02 PM PST 24
Finished Feb 29 02:23:07 PM PST 24
Peak memory 219032 kb
Host smart-5c0130c7-825c-42f5-8bf9-1180970748e5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023866033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.4023866033
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3920992510
Short name T505
Test name
Test status
Simulation time 3518757571 ps
CPU time 1226.49 seconds
Started Feb 29 02:23:21 PM PST 24
Finished Feb 29 02:43:49 PM PST 24
Peak memory 372468 kb
Host smart-565f9654-6721-4286-b146-2a080b16b5a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920992510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.3920992510
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.2914180729
Short name T783
Test name
Test status
Simulation time 21218405 ps
CPU time 0.65 seconds
Started Feb 29 02:23:34 PM PST 24
Finished Feb 29 02:23:34 PM PST 24
Peak memory 201720 kb
Host smart-b5e1507b-fa65-4d28-9f81-40694e73ac5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914180729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.2914180729
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.2027416959
Short name T866
Test name
Test status
Simulation time 7550973566 ps
CPU time 56.89 seconds
Started Feb 29 02:23:20 PM PST 24
Finished Feb 29 02:24:18 PM PST 24
Peak memory 202816 kb
Host smart-0ec25b6b-fd7a-42ed-959b-62e0ced5ff4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027416959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.2027416959
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.2118933938
Short name T454
Test name
Test status
Simulation time 7139466169 ps
CPU time 2391.71 seconds
Started Feb 29 02:23:22 PM PST 24
Finished Feb 29 03:03:15 PM PST 24
Peak memory 373496 kb
Host smart-2fe424c6-4580-4007-a2a5-0f35e3edf0c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118933938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.2118933938
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.2189467885
Short name T578
Test name
Test status
Simulation time 7548059181 ps
CPU time 9.76 seconds
Started Feb 29 02:23:20 PM PST 24
Finished Feb 29 02:23:31 PM PST 24
Peak memory 210896 kb
Host smart-463ba023-d07f-4772-a548-e238f1ccea94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189467885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.2189467885
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1283115229
Short name T358
Test name
Test status
Simulation time 161778913 ps
CPU time 147.5 seconds
Started Feb 29 02:23:21 PM PST 24
Finished Feb 29 02:25:50 PM PST 24
Peak memory 371960 kb
Host smart-cb72cf0d-26fc-4f82-833b-2407167d25de
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283115229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1283115229
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3214484312
Short name T74
Test name
Test status
Simulation time 68098154 ps
CPU time 4.82 seconds
Started Feb 29 02:23:22 PM PST 24
Finished Feb 29 02:23:28 PM PST 24
Peak memory 216004 kb
Host smart-8e0b1b67-d595-4ef8-ae1c-fce5c0606a82
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214484312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.3214484312
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.4044552996
Short name T751
Test name
Test status
Simulation time 1075392403 ps
CPU time 10.35 seconds
Started Feb 29 02:23:21 PM PST 24
Finished Feb 29 02:23:32 PM PST 24
Peak memory 202644 kb
Host smart-784ab5aa-4a90-4a3d-be5d-74ce732a0100
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044552996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.4044552996
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.441630135
Short name T522
Test name
Test status
Simulation time 881279697 ps
CPU time 470.54 seconds
Started Feb 29 02:23:21 PM PST 24
Finished Feb 29 02:31:13 PM PST 24
Peak memory 370216 kb
Host smart-44f50887-1f5a-49d6-8767-58b6a4a690b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441630135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip
le_keys.441630135
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.3915288465
Short name T409
Test name
Test status
Simulation time 2033211260 ps
CPU time 104.6 seconds
Started Feb 29 02:23:21 PM PST 24
Finished Feb 29 02:25:07 PM PST 24
Peak memory 357788 kb
Host smart-6e3b5243-4627-48ce-bd17-db334a1dc00a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915288465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.3915288465
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2752496652
Short name T162
Test name
Test status
Simulation time 15149459137 ps
CPU time 337.16 seconds
Started Feb 29 02:23:22 PM PST 24
Finished Feb 29 02:29:00 PM PST 24
Peak memory 202736 kb
Host smart-11d8179e-8f89-41a1-80b8-05791723e20d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752496652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.2752496652
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2678614337
Short name T460
Test name
Test status
Simulation time 27989780 ps
CPU time 1.14 seconds
Started Feb 29 02:23:22 PM PST 24
Finished Feb 29 02:23:24 PM PST 24
Peak memory 202848 kb
Host smart-fe10027a-1cd0-4145-a110-b6c81735cc4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678614337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2678614337
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.528084553
Short name T351
Test name
Test status
Simulation time 150444981403 ps
CPU time 1083.92 seconds
Started Feb 29 02:23:22 PM PST 24
Finished Feb 29 02:41:27 PM PST 24
Peak memory 372576 kb
Host smart-1df5343d-7691-44f4-9f10-5eb1ba546f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528084553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.528084553
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.386050403
Short name T255
Test name
Test status
Simulation time 1524732438 ps
CPU time 14.73 seconds
Started Feb 29 02:23:21 PM PST 24
Finished Feb 29 02:23:37 PM PST 24
Peak memory 202692 kb
Host smart-8b577d06-5b70-4376-98d1-f97bdbacaa51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386050403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.386050403
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.109803114
Short name T724
Test name
Test status
Simulation time 131940060242 ps
CPU time 2597.75 seconds
Started Feb 29 02:23:21 PM PST 24
Finished Feb 29 03:06:40 PM PST 24
Peak memory 383460 kb
Host smart-2a727d81-2347-4461-9117-0d6b6de9715f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109803114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_stress_all.109803114
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3450415114
Short name T673
Test name
Test status
Simulation time 2196825759 ps
CPU time 224.48 seconds
Started Feb 29 02:23:20 PM PST 24
Finished Feb 29 02:27:05 PM PST 24
Peak memory 202740 kb
Host smart-885adda1-9307-4ee4-91a0-1d90180e7166
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450415114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.3450415114
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1279407654
Short name T293
Test name
Test status
Simulation time 152596058 ps
CPU time 15.93 seconds
Started Feb 29 02:23:22 PM PST 24
Finished Feb 29 02:23:39 PM PST 24
Peak memory 259992 kb
Host smart-adc39437-978a-4ca3-9ca0-2090a210df28
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279407654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1279407654
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2688001044
Short name T591
Test name
Test status
Simulation time 11980686047 ps
CPU time 707.84 seconds
Started Feb 29 02:23:34 PM PST 24
Finished Feb 29 02:35:22 PM PST 24
Peak memory 375552 kb
Host smart-8c2128da-03ee-4887-b9e2-1f311f7e007f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688001044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.2688001044
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.1563862926
Short name T574
Test name
Test status
Simulation time 25006602 ps
CPU time 0.65 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:23:37 PM PST 24
Peak memory 201552 kb
Host smart-441f80a4-8dde-4f23-985d-f141007798dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563862926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.1563862926
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3791532685
Short name T37
Test name
Test status
Simulation time 14427623463 ps
CPU time 55.48 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:24:32 PM PST 24
Peak memory 202724 kb
Host smart-5f6aa7f1-b6bd-4f61-8463-c037092dd740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791532685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3791532685
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.1932469315
Short name T318
Test name
Test status
Simulation time 1987803093 ps
CPU time 568.98 seconds
Started Feb 29 02:23:34 PM PST 24
Finished Feb 29 02:33:03 PM PST 24
Peak memory 366792 kb
Host smart-950281c7-ac89-4b27-8b4a-1b30ee1cfc8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932469315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.1932469315
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.755094892
Short name T887
Test name
Test status
Simulation time 198093689 ps
CPU time 6.33 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:23:43 PM PST 24
Peak memory 211972 kb
Host smart-be0aaa94-50c9-4c97-8ee0-65e6c8eb83cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755094892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc
alation.755094892
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2509042519
Short name T316
Test name
Test status
Simulation time 139737338 ps
CPU time 1.78 seconds
Started Feb 29 02:23:37 PM PST 24
Finished Feb 29 02:23:39 PM PST 24
Peak memory 210912 kb
Host smart-a4ba9684-3cf2-4f40-b34f-c6ba0cec3699
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509042519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2509042519
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2619092950
Short name T62
Test name
Test status
Simulation time 911794395 ps
CPU time 5.29 seconds
Started Feb 29 02:23:33 PM PST 24
Finished Feb 29 02:23:39 PM PST 24
Peak memory 211892 kb
Host smart-22994edc-c289-4d3f-9017-3daccb6fcca0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619092950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.2619092950
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.503218168
Short name T809
Test name
Test status
Simulation time 228210008 ps
CPU time 4.92 seconds
Started Feb 29 02:23:37 PM PST 24
Finished Feb 29 02:23:42 PM PST 24
Peak memory 202680 kb
Host smart-77d6fe23-74c1-40e4-a1b8-5a5a9f09490b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503218168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.503218168
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.1553314211
Short name T871
Test name
Test status
Simulation time 13029210288 ps
CPU time 1058.19 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:41:13 PM PST 24
Peak memory 374568 kb
Host smart-9a3eb3ef-1664-4e5d-ba09-70a0cb8e9d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553314211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.1553314211
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3729778698
Short name T668
Test name
Test status
Simulation time 49528326 ps
CPU time 0.98 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:23:37 PM PST 24
Peak memory 202456 kb
Host smart-f4e4ec4a-dbd9-4674-8c85-9eb8a65454a1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729778698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3729778698
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.54913594
Short name T832
Test name
Test status
Simulation time 88244263740 ps
CPU time 510.22 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:32:05 PM PST 24
Peak memory 202776 kb
Host smart-c56f1ece-e24c-49cf-aa17-d98039d3729a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54913594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_partial_access_b2b.54913594
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.3392916099
Short name T408
Test name
Test status
Simulation time 45145671 ps
CPU time 0.93 seconds
Started Feb 29 02:23:34 PM PST 24
Finished Feb 29 02:23:35 PM PST 24
Peak memory 202644 kb
Host smart-23d94c73-28e8-48ea-a08c-7ff251e323df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392916099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3392916099
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.3693697582
Short name T110
Test name
Test status
Simulation time 3600300856 ps
CPU time 1426.46 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:47:22 PM PST 24
Peak memory 374520 kb
Host smart-b9f8d0c2-1b14-4123-b439-5a88a039842f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693697582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3693697582
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.2353142942
Short name T377
Test name
Test status
Simulation time 227033208 ps
CPU time 5.3 seconds
Started Feb 29 02:23:38 PM PST 24
Finished Feb 29 02:23:43 PM PST 24
Peak memory 202600 kb
Host smart-545e4571-fb2d-4eee-9df5-a8bbc050ddd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353142942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2353142942
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2825918080
Short name T716
Test name
Test status
Simulation time 8248749622 ps
CPU time 188.51 seconds
Started Feb 29 02:23:34 PM PST 24
Finished Feb 29 02:26:43 PM PST 24
Peak memory 202752 kb
Host smart-a72ec7c4-b917-47fd-ad31-ad280d389d2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825918080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.2825918080
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3356563202
Short name T405
Test name
Test status
Simulation time 132165049 ps
CPU time 12.8 seconds
Started Feb 29 02:23:33 PM PST 24
Finished Feb 29 02:23:46 PM PST 24
Peak memory 240080 kb
Host smart-f7fb6594-dea7-4d5a-9231-51a2c3c2e717
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356563202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3356563202
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3793623884
Short name T191
Test name
Test status
Simulation time 7182436404 ps
CPU time 609.79 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:33:44 PM PST 24
Peak memory 368364 kb
Host smart-0572425f-ddac-473d-a49f-53299f2bda5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793623884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.3793623884
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.3246503991
Short name T283
Test name
Test status
Simulation time 52038236 ps
CPU time 0.63 seconds
Started Feb 29 02:23:37 PM PST 24
Finished Feb 29 02:23:38 PM PST 24
Peak memory 201708 kb
Host smart-4e5f5ba6-5eea-4958-8089-c5d00ab361e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246503991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.3246503991
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.28697127
Short name T368
Test name
Test status
Simulation time 2408915554 ps
CPU time 40.3 seconds
Started Feb 29 02:23:34 PM PST 24
Finished Feb 29 02:24:15 PM PST 24
Peak memory 202712 kb
Host smart-7ff43aa1-b5d8-4ea0-b5eb-94b127876862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28697127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.28697127
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.4173995402
Short name T503
Test name
Test status
Simulation time 1088763267 ps
CPU time 109.11 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:25:24 PM PST 24
Peak memory 334832 kb
Host smart-b289bf3b-113d-4635-9c7d-05e792317110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173995402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.4173995402
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3213236228
Short name T634
Test name
Test status
Simulation time 928478268 ps
CPU time 12.79 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:23:48 PM PST 24
Peak memory 202536 kb
Host smart-ba9375d2-b8e4-4867-8271-ae75e58021eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213236228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3213236228
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.977205892
Short name T383
Test name
Test status
Simulation time 546512101 ps
CPU time 80.39 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:24:57 PM PST 24
Peak memory 311916 kb
Host smart-bb2cb1f9-ea2c-417c-a351-28229a0fdaba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977205892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sram_ctrl_max_throughput.977205892
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2190894392
Short name T785
Test name
Test status
Simulation time 54876586 ps
CPU time 3.55 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:23:39 PM PST 24
Peak memory 215888 kb
Host smart-620da3b7-2d8c-4132-ba39-1814cfd3e5d9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190894392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2190894392
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3958981975
Short name T419
Test name
Test status
Simulation time 1144144140 ps
CPU time 10.1 seconds
Started Feb 29 02:23:37 PM PST 24
Finished Feb 29 02:23:47 PM PST 24
Peak memory 202600 kb
Host smart-197b4c52-b6a8-4251-ab2f-5bc2577d471b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958981975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.3958981975
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3627171649
Short name T692
Test name
Test status
Simulation time 38148281417 ps
CPU time 745.74 seconds
Started Feb 29 02:23:37 PM PST 24
Finished Feb 29 02:36:03 PM PST 24
Peak memory 366320 kb
Host smart-87329e2b-e733-4539-a788-418eb5a2221e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627171649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3627171649
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.86839954
Short name T137
Test name
Test status
Simulation time 534329031 ps
CPU time 32.76 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:24:08 PM PST 24
Peak memory 281300 kb
Host smart-d7a7daaf-bf12-4a04-b2f6-e2d056f42be3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86839954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sr
am_ctrl_partial_access.86839954
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3678486539
Short name T458
Test name
Test status
Simulation time 23438455852 ps
CPU time 428.33 seconds
Started Feb 29 02:23:32 PM PST 24
Finished Feb 29 02:30:41 PM PST 24
Peak memory 202756 kb
Host smart-0ea9373a-58c7-4794-b156-20aaaeee3784
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678486539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3678486539
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.162588968
Short name T328
Test name
Test status
Simulation time 78190842 ps
CPU time 0.85 seconds
Started Feb 29 02:23:35 PM PST 24
Finished Feb 29 02:23:36 PM PST 24
Peak memory 202648 kb
Host smart-582f6d52-3a29-4167-8459-6bc62bb8c641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162588968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.162588968
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.2209532963
Short name T534
Test name
Test status
Simulation time 3675702792 ps
CPU time 1227.05 seconds
Started Feb 29 02:23:33 PM PST 24
Finished Feb 29 02:44:01 PM PST 24
Peak memory 363352 kb
Host smart-15153ded-8603-41d4-85e4-438d638919e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209532963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2209532963
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1249475222
Short name T298
Test name
Test status
Simulation time 43801569 ps
CPU time 2.28 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:23:38 PM PST 24
Peak memory 202692 kb
Host smart-ff118fd1-1313-45c7-9067-c3e1dbb5591f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249475222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1249475222
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.4110353282
Short name T86
Test name
Test status
Simulation time 2860359289 ps
CPU time 277.93 seconds
Started Feb 29 02:23:32 PM PST 24
Finished Feb 29 02:28:11 PM PST 24
Peak memory 202744 kb
Host smart-2b694d75-69e5-4547-b360-1c5482755f63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110353282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.4110353282
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1607973692
Short name T835
Test name
Test status
Simulation time 101941882 ps
CPU time 26.78 seconds
Started Feb 29 02:23:36 PM PST 24
Finished Feb 29 02:24:03 PM PST 24
Peak memory 284256 kb
Host smart-2d80903a-7a85-4cb8-b99e-fa23a8a5e7f5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607973692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1607973692
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1385671961
Short name T310
Test name
Test status
Simulation time 30434682508 ps
CPU time 475.47 seconds
Started Feb 29 02:23:58 PM PST 24
Finished Feb 29 02:31:54 PM PST 24
Peak memory 362820 kb
Host smart-46be96d7-8725-43f8-861b-f054ac3aae01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385671961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.1385671961
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.365715486
Short name T847
Test name
Test status
Simulation time 13979786 ps
CPU time 0.64 seconds
Started Feb 29 02:23:50 PM PST 24
Finished Feb 29 02:23:51 PM PST 24
Peak memory 202436 kb
Host smart-d7ba358b-ad0f-4e84-b0d8-dad6108ef6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365715486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.365715486
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.4291130391
Short name T595
Test name
Test status
Simulation time 4190838034 ps
CPU time 67.17 seconds
Started Feb 29 02:23:38 PM PST 24
Finished Feb 29 02:24:45 PM PST 24
Peak memory 202708 kb
Host smart-7894dfb1-739a-4c37-827d-071fca0b3f9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291130391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.4291130391
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.2160005543
Short name T130
Test name
Test status
Simulation time 3509996277 ps
CPU time 18.1 seconds
Started Feb 29 02:23:50 PM PST 24
Finished Feb 29 02:24:09 PM PST 24
Peak memory 202748 kb
Host smart-ebec8635-bbc8-41f8-89f0-3ddebb847b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160005543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.2160005543
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3694288400
Short name T367
Test name
Test status
Simulation time 1563435888 ps
CPU time 10.68 seconds
Started Feb 29 02:23:58 PM PST 24
Finished Feb 29 02:24:08 PM PST 24
Peak memory 210912 kb
Host smart-7d14ab93-5002-4254-92c6-f59619548f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694288400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3694288400
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3733812540
Short name T391
Test name
Test status
Simulation time 238350101 ps
CPU time 114.85 seconds
Started Feb 29 02:23:50 PM PST 24
Finished Feb 29 02:25:45 PM PST 24
Peak memory 342760 kb
Host smart-57e09a1b-3de2-4bff-9ca0-d2b8142ce056
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733812540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3733812540
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3277204500
Short name T262
Test name
Test status
Simulation time 337008866 ps
CPU time 5.48 seconds
Started Feb 29 02:23:50 PM PST 24
Finished Feb 29 02:23:55 PM PST 24
Peak memory 210784 kb
Host smart-b26bbcb1-705c-48c3-9e33-ae7de8a282f9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277204500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.3277204500
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2963862122
Short name T174
Test name
Test status
Simulation time 137579336 ps
CPU time 8.43 seconds
Started Feb 29 02:23:58 PM PST 24
Finished Feb 29 02:24:06 PM PST 24
Peak memory 202660 kb
Host smart-b889cf37-c18c-4ac7-954f-e13680b0843f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963862122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2963862122
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.3655077701
Short name T167
Test name
Test status
Simulation time 59506663974 ps
CPU time 1975.14 seconds
Started Feb 29 02:23:37 PM PST 24
Finished Feb 29 02:56:32 PM PST 24
Peak memory 375056 kb
Host smart-10c53696-883d-4fa9-9aec-10f797e14be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655077701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.3655077701
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.151599064
Short name T211
Test name
Test status
Simulation time 5055067424 ps
CPU time 20.48 seconds
Started Feb 29 02:23:51 PM PST 24
Finished Feb 29 02:24:11 PM PST 24
Peak memory 202652 kb
Host smart-2d792867-e5ec-4727-81c3-2dca7f49acf3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151599064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s
ram_ctrl_partial_access.151599064
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.4228767855
Short name T645
Test name
Test status
Simulation time 3746680192 ps
CPU time 234.31 seconds
Started Feb 29 02:23:51 PM PST 24
Finished Feb 29 02:27:45 PM PST 24
Peak memory 202776 kb
Host smart-502ee314-86de-4bab-9216-86e7cabfd5f9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228767855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.4228767855
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2284592331
Short name T407
Test name
Test status
Simulation time 30147582 ps
CPU time 0.87 seconds
Started Feb 29 02:23:52 PM PST 24
Finished Feb 29 02:23:53 PM PST 24
Peak memory 202636 kb
Host smart-0ad4823f-2d6e-4207-872e-9f2a49e1cd79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284592331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2284592331
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.1613008160
Short name T543
Test name
Test status
Simulation time 747565061 ps
CPU time 16.71 seconds
Started Feb 29 02:23:38 PM PST 24
Finished Feb 29 02:23:55 PM PST 24
Peak memory 202596 kb
Host smart-afbf0eb8-cbe4-4254-b619-a0ee0a1359c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613008160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1613008160
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.4099828948
Short name T321
Test name
Test status
Simulation time 6250619072 ps
CPU time 300.21 seconds
Started Feb 29 02:23:49 PM PST 24
Finished Feb 29 02:28:50 PM PST 24
Peak memory 202740 kb
Host smart-5debeda9-0c22-4620-a3c5-65e0091039c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099828948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.4099828948
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3673898006
Short name T610
Test name
Test status
Simulation time 106553215 ps
CPU time 41.91 seconds
Started Feb 29 02:23:50 PM PST 24
Finished Feb 29 02:24:32 PM PST 24
Peak memory 290596 kb
Host smart-086f3b95-a67c-4ad9-b449-5e50b1349014
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673898006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3673898006
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3351916933
Short name T424
Test name
Test status
Simulation time 10551870814 ps
CPU time 1597.9 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:50:42 PM PST 24
Peak memory 374516 kb
Host smart-5101c538-db77-4a55-acb6-b9ca0d81d638
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351916933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.3351916933
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.1713438797
Short name T628
Test name
Test status
Simulation time 40432194 ps
CPU time 0.65 seconds
Started Feb 29 02:24:02 PM PST 24
Finished Feb 29 02:24:03 PM PST 24
Peak memory 201680 kb
Host smart-b71b4bd3-f96e-4981-8aaf-31b0aa9a7044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713438797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.1713438797
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.3053472595
Short name T564
Test name
Test status
Simulation time 6994227047 ps
CPU time 55.41 seconds
Started Feb 29 02:23:53 PM PST 24
Finished Feb 29 02:24:48 PM PST 24
Peak memory 202720 kb
Host smart-57db93ab-6b4c-4c88-a6a6-0b0b96e20108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053472595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.3053472595
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.4201310281
Short name T609
Test name
Test status
Simulation time 918412931 ps
CPU time 11.23 seconds
Started Feb 29 02:24:03 PM PST 24
Finished Feb 29 02:24:14 PM PST 24
Peak memory 202628 kb
Host smart-f9944218-7717-4c7d-9537-2509a72ae8a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201310281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.4201310281
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.3345409432
Short name T797
Test name
Test status
Simulation time 1579570909 ps
CPU time 146.73 seconds
Started Feb 29 02:24:03 PM PST 24
Finished Feb 29 02:26:30 PM PST 24
Peak memory 367120 kb
Host smart-02b41565-341c-4084-92db-e81cf8810488
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345409432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.3345409432
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3020844711
Short name T36
Test name
Test status
Simulation time 87726045 ps
CPU time 3.12 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:24:07 PM PST 24
Peak memory 210896 kb
Host smart-c0694d50-f901-47b3-84c5-0059d18635d7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020844711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.3020844711
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.301709729
Short name T268
Test name
Test status
Simulation time 910605768 ps
CPU time 9.22 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:24:14 PM PST 24
Peak memory 202644 kb
Host smart-ab0daceb-82ed-41b5-b2ad-5ce01ee0ec74
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301709729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl
_mem_walk.301709729
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.3846495035
Short name T701
Test name
Test status
Simulation time 2976755831 ps
CPU time 706.03 seconds
Started Feb 29 02:23:52 PM PST 24
Finished Feb 29 02:35:38 PM PST 24
Peak memory 371520 kb
Host smart-9509adda-c741-48f4-8885-c9173e81fb6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846495035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.3846495035
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1801095691
Short name T713
Test name
Test status
Simulation time 1145215541 ps
CPU time 10.5 seconds
Started Feb 29 02:24:05 PM PST 24
Finished Feb 29 02:24:15 PM PST 24
Peak memory 202700 kb
Host smart-688690a8-2dbe-4a1a-9f3a-85289785b4e7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801095691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1801095691
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3925820447
Short name T148
Test name
Test status
Simulation time 8682398889 ps
CPU time 329.79 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:29:34 PM PST 24
Peak memory 202720 kb
Host smart-7486598b-6f41-4257-8560-d7deffc4a45e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925820447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.3925820447
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.1223597168
Short name T787
Test name
Test status
Simulation time 39551526 ps
CPU time 0.86 seconds
Started Feb 29 02:24:02 PM PST 24
Finished Feb 29 02:24:03 PM PST 24
Peak memory 202720 kb
Host smart-1048b9e9-8f1c-4133-ada1-28aed3f31306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223597168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1223597168
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.1855258129
Short name T221
Test name
Test status
Simulation time 20043904077 ps
CPU time 1049.36 seconds
Started Feb 29 02:24:03 PM PST 24
Finished Feb 29 02:41:33 PM PST 24
Peak memory 373856 kb
Host smart-f60f26e7-35e0-4f8b-af5a-79b481c795c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855258129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1855258129
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.2527202214
Short name T569
Test name
Test status
Simulation time 473055658 ps
CPU time 8.19 seconds
Started Feb 29 02:23:50 PM PST 24
Finished Feb 29 02:23:59 PM PST 24
Peak memory 202636 kb
Host smart-eeb80b1d-ff02-4612-8a62-6da2f2529d07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527202214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2527202214
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2613229925
Short name T682
Test name
Test status
Simulation time 3178077362 ps
CPU time 328.71 seconds
Started Feb 29 02:24:03 PM PST 24
Finished Feb 29 02:29:32 PM PST 24
Peak memory 202712 kb
Host smart-ef02b07b-7e0b-41d6-8e6f-5cfe0a4ddde8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613229925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.2613229925
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2354446006
Short name T120
Test name
Test status
Simulation time 77242491 ps
CPU time 14.26 seconds
Started Feb 29 02:24:02 PM PST 24
Finished Feb 29 02:24:16 PM PST 24
Peak memory 252808 kb
Host smart-e163662d-0459-4ad6-8d19-ae9cab6c00d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354446006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2354446006
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.552873882
Short name T334
Test name
Test status
Simulation time 13318551527 ps
CPU time 1722.06 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:53:01 PM PST 24
Peak memory 374504 kb
Host smart-05ae0b86-622a-4742-a4c1-18b14fb3eeb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552873882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.sram_ctrl_access_during_key_req.552873882
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.4055383011
Short name T394
Test name
Test status
Simulation time 15135509 ps
CPU time 0.68 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:24:18 PM PST 24
Peak memory 201740 kb
Host smart-0fde371b-45bc-4ac9-ab50-8ec9629ee35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055383011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.4055383011
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.495315840
Short name T285
Test name
Test status
Simulation time 1362469628 ps
CPU time 42.51 seconds
Started Feb 29 02:24:03 PM PST 24
Finished Feb 29 02:24:46 PM PST 24
Peak memory 202680 kb
Host smart-e0c6b8dc-3a83-4a24-a4ca-7065d4c4bc87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495315840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
495315840
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.3280962067
Short name T859
Test name
Test status
Simulation time 4298595264 ps
CPU time 360.78 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:30:19 PM PST 24
Peak memory 373468 kb
Host smart-7906df73-e4d4-417f-864b-4ebc0c1a99a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280962067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.3280962067
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.3162297748
Short name T711
Test name
Test status
Simulation time 1186175684 ps
CPU time 8.02 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:24:27 PM PST 24
Peak memory 213336 kb
Host smart-a7e16af9-54d2-426b-b3ae-8cb00ef763c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162297748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.3162297748
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.2248281576
Short name T312
Test name
Test status
Simulation time 1811065289 ps
CPU time 131.54 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:26:16 PM PST 24
Peak memory 362896 kb
Host smart-65216f3c-9394-4095-b400-c6b72c6e9ffd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248281576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.2248281576
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1973593397
Short name T575
Test name
Test status
Simulation time 179447764 ps
CPU time 3.36 seconds
Started Feb 29 02:24:20 PM PST 24
Finished Feb 29 02:24:23 PM PST 24
Peak memory 218956 kb
Host smart-76846512-9214-42bc-8069-37c7c3b5be12
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973593397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.1973593397
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.800036404
Short name T879
Test name
Test status
Simulation time 5004356173 ps
CPU time 11.21 seconds
Started Feb 29 02:24:19 PM PST 24
Finished Feb 29 02:24:30 PM PST 24
Peak memory 202728 kb
Host smart-29a0385b-5f1d-4ef3-b8b7-c4c9bb01bed9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800036404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_mem_walk.800036404
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.3232224547
Short name T226
Test name
Test status
Simulation time 88783066319 ps
CPU time 495.08 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:32:19 PM PST 24
Peak memory 370876 kb
Host smart-ae76c0c6-312f-4a86-8ca7-c8ae32f47298
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232224547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.3232224547
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.4108910373
Short name T756
Test name
Test status
Simulation time 3275302781 ps
CPU time 17.69 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:24:22 PM PST 24
Peak memory 202664 kb
Host smart-2acde941-ee02-4a78-a618-397301406abe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108910373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.4108910373
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1504816589
Short name T848
Test name
Test status
Simulation time 16628637449 ps
CPU time 435.8 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:31:20 PM PST 24
Peak memory 202740 kb
Host smart-ad05c796-9f04-409b-8494-818575b5e461
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504816589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1504816589
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.1231722362
Short name T205
Test name
Test status
Simulation time 26940018 ps
CPU time 0.86 seconds
Started Feb 29 02:24:19 PM PST 24
Finished Feb 29 02:24:20 PM PST 24
Peak memory 202728 kb
Host smart-88a9f506-e474-4971-893f-15712754b85a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231722362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1231722362
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.2172063618
Short name T766
Test name
Test status
Simulation time 17527067694 ps
CPU time 1425.8 seconds
Started Feb 29 02:24:20 PM PST 24
Finished Feb 29 02:48:06 PM PST 24
Peak memory 374472 kb
Host smart-51279a31-cafa-4884-96bc-95fd763f9e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172063618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2172063618
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.1549897432
Short name T242
Test name
Test status
Simulation time 515768939 ps
CPU time 8.15 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:24:12 PM PST 24
Peak memory 202692 kb
Host smart-939c0a92-92ad-4ee8-90c7-a049c11d66b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549897432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1549897432
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.3092561977
Short name T480
Test name
Test status
Simulation time 567366034725 ps
CPU time 6646.25 seconds
Started Feb 29 02:24:22 PM PST 24
Finished Feb 29 04:15:09 PM PST 24
Peak memory 382600 kb
Host smart-afac81ba-adb8-46bb-93fe-b92718558949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092561977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.3092561977
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3835980360
Short name T523
Test name
Test status
Simulation time 7460259515 ps
CPU time 358.11 seconds
Started Feb 29 02:24:04 PM PST 24
Finished Feb 29 02:30:03 PM PST 24
Peak memory 202708 kb
Host smart-b8544896-0d70-4d59-904f-6ef09ccf3a70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835980360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3835980360
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3360702392
Short name T712
Test name
Test status
Simulation time 59863167 ps
CPU time 5.31 seconds
Started Feb 29 02:24:03 PM PST 24
Finished Feb 29 02:24:09 PM PST 24
Peak memory 222764 kb
Host smart-b184b2ca-3465-4fe9-8fcd-12af2a35adbc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360702392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3360702392
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.57047458
Short name T14
Test name
Test status
Simulation time 605813844 ps
CPU time 329.15 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:29:48 PM PST 24
Peak memory 371356 kb
Host smart-e5199f90-6808-4941-b308-78e0f2946809
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57047458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.sram_ctrl_access_during_key_req.57047458
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.2908882054
Short name T218
Test name
Test status
Simulation time 15501941 ps
CPU time 0.64 seconds
Started Feb 29 02:24:34 PM PST 24
Finished Feb 29 02:24:35 PM PST 24
Peak memory 202364 kb
Host smart-83f6e52c-fd8c-4459-a085-0f2784a2ada2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908882054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.2908882054
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.1752001005
Short name T479
Test name
Test status
Simulation time 9043821362 ps
CPU time 38.98 seconds
Started Feb 29 02:24:17 PM PST 24
Finished Feb 29 02:24:57 PM PST 24
Peak memory 202704 kb
Host smart-0f830cc0-c931-49c8-bb0e-516b1eec2534
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752001005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.1752001005
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1838622544
Short name T881
Test name
Test status
Simulation time 7489874210 ps
CPU time 699.5 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:35:58 PM PST 24
Peak memory 372404 kb
Host smart-6b584c16-f95b-4e76-9787-be76dd2c4064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838622544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1838622544
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.3790159712
Short name T414
Test name
Test status
Simulation time 49864150 ps
CPU time 1.73 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:24:20 PM PST 24
Peak memory 210896 kb
Host smart-1acc937d-8cb0-4bf4-bfbc-af81acc0d31b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790159712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.3790159712
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.4100801392
Short name T693
Test name
Test status
Simulation time 67941741 ps
CPU time 13.67 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:24:31 PM PST 24
Peak memory 251132 kb
Host smart-e813fe78-5fee-4845-8635-1496d5dca77a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100801392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.4100801392
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1383557939
Short name T529
Test name
Test status
Simulation time 299518225 ps
CPU time 5.48 seconds
Started Feb 29 02:24:35 PM PST 24
Finished Feb 29 02:24:42 PM PST 24
Peak memory 210832 kb
Host smart-3b7f31e2-6bc7-48ce-9b99-aff21be55838
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383557939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.1383557939
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.3989515779
Short name T508
Test name
Test status
Simulation time 233161579 ps
CPU time 5.16 seconds
Started Feb 29 02:24:33 PM PST 24
Finished Feb 29 02:24:39 PM PST 24
Peak memory 202596 kb
Host smart-670f5356-30b8-4d73-a760-a31a6f4d1cfa
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989515779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.3989515779
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.1228739710
Short name T687
Test name
Test status
Simulation time 5453474496 ps
CPU time 1118.58 seconds
Started Feb 29 02:24:17 PM PST 24
Finished Feb 29 02:42:56 PM PST 24
Peak memory 366364 kb
Host smart-2c292ba5-aafc-4324-88e3-e70255dbdb2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228739710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.1228739710
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.2584166656
Short name T380
Test name
Test status
Simulation time 358415231 ps
CPU time 3.43 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:24:22 PM PST 24
Peak memory 207360 kb
Host smart-9925db44-8bd0-40a5-9599-99d997c55ff4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584166656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.2584166656
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1644980105
Short name T865
Test name
Test status
Simulation time 4367825530 ps
CPU time 317.35 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:29:36 PM PST 24
Peak memory 202748 kb
Host smart-21d88784-0f49-4320-b160-3941609c8594
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644980105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.1644980105
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.2239755830
Short name T516
Test name
Test status
Simulation time 47442556 ps
CPU time 1.11 seconds
Started Feb 29 02:24:32 PM PST 24
Finished Feb 29 02:24:33 PM PST 24
Peak memory 202948 kb
Host smart-60dd100b-d1b5-48f1-ad17-f6810c2cd57b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239755830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2239755830
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.1265829594
Short name T664
Test name
Test status
Simulation time 8330582128 ps
CPU time 421.78 seconds
Started Feb 29 02:24:19 PM PST 24
Finished Feb 29 02:31:21 PM PST 24
Peak memory 321340 kb
Host smart-ee08d593-62ef-4416-8a57-cb7a75d7fd58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265829594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1265829594
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.1271347969
Short name T335
Test name
Test status
Simulation time 297678115 ps
CPU time 4.4 seconds
Started Feb 29 02:24:17 PM PST 24
Finished Feb 29 02:24:22 PM PST 24
Peak memory 202684 kb
Host smart-67dd99e3-651b-4b50-b415-9327475ee258
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271347969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1271347969
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.1009389548
Short name T112
Test name
Test status
Simulation time 25940963442 ps
CPU time 1468.66 seconds
Started Feb 29 02:24:32 PM PST 24
Finished Feb 29 02:49:01 PM PST 24
Peak memory 374552 kb
Host smart-35c77876-8dca-4b8b-93ed-9180c8fbf38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009389548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.1009389548
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2157004931
Short name T145
Test name
Test status
Simulation time 1288026320 ps
CPU time 125.47 seconds
Started Feb 29 02:24:18 PM PST 24
Finished Feb 29 02:26:24 PM PST 24
Peak memory 202704 kb
Host smart-947eaeeb-4732-48b1-8221-100f70b62794
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157004931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.2157004931
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3682235543
Short name T175
Test name
Test status
Simulation time 142200478 ps
CPU time 115.06 seconds
Started Feb 29 02:24:22 PM PST 24
Finished Feb 29 02:26:17 PM PST 24
Peak memory 342696 kb
Host smart-25f644e8-6c48-48ae-acb5-71b5a7bdc834
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682235543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3682235543
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2334940162
Short name T168
Test name
Test status
Simulation time 4403068191 ps
CPU time 874.69 seconds
Started Feb 29 02:21:13 PM PST 24
Finished Feb 29 02:35:47 PM PST 24
Peak memory 368988 kb
Host smart-fb5dea36-09d1-41dd-acce-fe3375b8c9ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334940162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.2334940162
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.2318341454
Short name T364
Test name
Test status
Simulation time 23741875 ps
CPU time 0.65 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:21:25 PM PST 24
Peak memory 201712 kb
Host smart-2b0031d5-d645-4c8a-ba88-7782bfbed4b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318341454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.2318341454
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.921831679
Short name T333
Test name
Test status
Simulation time 1137636586 ps
CPU time 31.84 seconds
Started Feb 29 02:21:14 PM PST 24
Finished Feb 29 02:21:46 PM PST 24
Peak memory 202692 kb
Host smart-3f0a683a-c587-42d1-a554-8901f4d8d0bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921831679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.921831679
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.73867448
Short name T630
Test name
Test status
Simulation time 6545972208 ps
CPU time 468.88 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:29:12 PM PST 24
Peak memory 365256 kb
Host smart-7c9a4a54-103e-44f6-b824-005d58aa7259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73867448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.73867448
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.2829994036
Short name T403
Test name
Test status
Simulation time 53469923 ps
CPU time 1.81 seconds
Started Feb 29 02:21:08 PM PST 24
Finished Feb 29 02:21:10 PM PST 24
Peak memory 212220 kb
Host smart-1c5335ac-444f-41ec-b3d9-b86cbd6fd53b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829994036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.2829994036
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.1168659015
Short name T397
Test name
Test status
Simulation time 128170825 ps
CPU time 104.77 seconds
Started Feb 29 02:21:13 PM PST 24
Finished Feb 29 02:22:57 PM PST 24
Peak memory 348376 kb
Host smart-2622b98a-9c47-4b7a-ad48-6f1c1cc53f92
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168659015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.1168659015
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3301610713
Short name T127
Test name
Test status
Simulation time 184647987 ps
CPU time 5.5 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:21:27 PM PST 24
Peak memory 210852 kb
Host smart-b9d8a257-80f9-4054-939e-baada76cc6fc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301610713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.3301610713
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.3880418134
Short name T229
Test name
Test status
Simulation time 1754488898 ps
CPU time 5.8 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:21:30 PM PST 24
Peak memory 202620 kb
Host smart-b34f9b78-5b75-4989-9a18-f6c7281c98cd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880418134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.3880418134
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.857163112
Short name T671
Test name
Test status
Simulation time 3322936571 ps
CPU time 180.07 seconds
Started Feb 29 02:21:12 PM PST 24
Finished Feb 29 02:24:12 PM PST 24
Peak memory 339964 kb
Host smart-f68cf41b-fd05-4d09-aa97-0fb14abc75fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857163112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl
e_keys.857163112
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3087730769
Short name T435
Test name
Test status
Simulation time 1251849830 ps
CPU time 19.09 seconds
Started Feb 29 02:21:10 PM PST 24
Finished Feb 29 02:21:29 PM PST 24
Peak memory 202692 kb
Host smart-6d543247-55ec-4f50-8769-75c1e90340e0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087730769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3087730769
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1920334898
Short name T433
Test name
Test status
Simulation time 16711017459 ps
CPU time 423.53 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:28:15 PM PST 24
Peak memory 202732 kb
Host smart-75558369-ed82-43d8-83aa-ef7d7d9ab95b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920334898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.1920334898
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.1476649871
Short name T372
Test name
Test status
Simulation time 159113044 ps
CPU time 0.9 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:21:25 PM PST 24
Peak memory 202636 kb
Host smart-7b961902-04b7-40a0-a13c-0be4b3f64abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476649871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1476649871
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1031532647
Short name T684
Test name
Test status
Simulation time 39500266810 ps
CPU time 839.56 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:35:25 PM PST 24
Peak memory 373656 kb
Host smart-c9f8b4f8-bd60-422b-89f3-508839bdd71e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031532647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1031532647
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.3832244349
Short name T17
Test name
Test status
Simulation time 86689655 ps
CPU time 1.65 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:21:23 PM PST 24
Peak memory 220952 kb
Host smart-df8eea26-e9ff-48a8-98bb-7551415603a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832244349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.3832244349
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2781475184
Short name T470
Test name
Test status
Simulation time 893596736 ps
CPU time 67.11 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:22:19 PM PST 24
Peak memory 305248 kb
Host smart-a7b6eed0-4593-4ed6-beed-777f7766fb89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781475184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2781475184
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.784429049
Short name T704
Test name
Test status
Simulation time 49418872175 ps
CPU time 1708.22 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:49:55 PM PST 24
Peak memory 382824 kb
Host smart-2c48cc95-4c2d-4d43-a246-a03e8d6f0864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784429049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_stress_all.784429049
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.772412886
Short name T320
Test name
Test status
Simulation time 59891277423 ps
CPU time 334.13 seconds
Started Feb 29 02:21:11 PM PST 24
Finished Feb 29 02:26:45 PM PST 24
Peak memory 202896 kb
Host smart-2bb7a34d-5847-4185-981e-909ecf34f623
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772412886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
sram_ctrl_stress_pipeline.772412886
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.968611271
Short name T155
Test name
Test status
Simulation time 382402168 ps
CPU time 17.21 seconds
Started Feb 29 02:21:13 PM PST 24
Finished Feb 29 02:21:30 PM PST 24
Peak memory 261148 kb
Host smart-19d04427-d93f-4d9a-8f67-f4438e29b5ca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968611271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.968611271
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2134078912
Short name T506
Test name
Test status
Simulation time 15458373540 ps
CPU time 1409.37 seconds
Started Feb 29 02:24:33 PM PST 24
Finished Feb 29 02:48:04 PM PST 24
Peak memory 373464 kb
Host smart-d5a4f3ff-d666-4df0-b7ce-e072b6f5064d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134078912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.2134078912
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.994127993
Short name T838
Test name
Test status
Simulation time 30763299 ps
CPU time 0.64 seconds
Started Feb 29 02:24:34 PM PST 24
Finished Feb 29 02:24:36 PM PST 24
Peak memory 202436 kb
Host smart-1ac45020-3536-43b6-b0bb-fa93e8638991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994127993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.994127993
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.841611805
Short name T118
Test name
Test status
Simulation time 1190856140 ps
CPU time 28.25 seconds
Started Feb 29 02:24:34 PM PST 24
Finished Feb 29 02:25:04 PM PST 24
Peak memory 202652 kb
Host smart-d1368b74-4bb5-4fe1-a25c-cc9897b6263c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841611805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.
841611805
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.1117518401
Short name T323
Test name
Test status
Simulation time 15959627212 ps
CPU time 1449.97 seconds
Started Feb 29 02:24:35 PM PST 24
Finished Feb 29 02:48:46 PM PST 24
Peak memory 374524 kb
Host smart-1f734add-e6ec-440d-8624-b133755e4614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117518401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.1117518401
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.2160929213
Short name T683
Test name
Test status
Simulation time 1386061145 ps
CPU time 4.51 seconds
Started Feb 29 02:24:38 PM PST 24
Finished Feb 29 02:24:43 PM PST 24
Peak memory 202592 kb
Host smart-952fc224-2d48-40fb-8b89-bb1b208810f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160929213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.2160929213
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.3784870462
Short name T269
Test name
Test status
Simulation time 519380579 ps
CPU time 132.34 seconds
Started Feb 29 02:24:34 PM PST 24
Finished Feb 29 02:26:47 PM PST 24
Peak memory 353964 kb
Host smart-769910dd-6b58-4039-a1fe-e7d9ba807308
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784870462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.3784870462
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.923825055
Short name T527
Test name
Test status
Simulation time 668202798 ps
CPU time 5.77 seconds
Started Feb 29 02:24:36 PM PST 24
Finished Feb 29 02:24:43 PM PST 24
Peak memory 210904 kb
Host smart-f672da2e-a57b-4384-8337-d3fa07d13823
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923825055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.sram_ctrl_mem_partial_access.923825055
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.2690304213
Short name T177
Test name
Test status
Simulation time 1202484878 ps
CPU time 5.35 seconds
Started Feb 29 02:24:32 PM PST 24
Finished Feb 29 02:24:38 PM PST 24
Peak memory 202588 kb
Host smart-2839dfae-de65-414b-965a-e2716f903c50
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690304213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.2690304213
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.2439822793
Short name T156
Test name
Test status
Simulation time 11907097773 ps
CPU time 799.28 seconds
Started Feb 29 02:24:34 PM PST 24
Finished Feb 29 02:37:55 PM PST 24
Peak memory 368348 kb
Host smart-ac601455-d81c-4df6-bc3c-c7ebb451642d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439822793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.2439822793
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.4013629665
Short name T663
Test name
Test status
Simulation time 932051705 ps
CPU time 18.25 seconds
Started Feb 29 02:24:36 PM PST 24
Finished Feb 29 02:24:55 PM PST 24
Peak memory 202688 kb
Host smart-61f8a561-2df1-4498-9744-b36a68c5cf4e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013629665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.4013629665
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2352130010
Short name T744
Test name
Test status
Simulation time 5784916198 ps
CPU time 201.76 seconds
Started Feb 29 02:24:35 PM PST 24
Finished Feb 29 02:27:57 PM PST 24
Peak memory 202748 kb
Host smart-8ed1ec5d-d569-4204-aa78-09c11a2d1284
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352130010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.2352130010
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.4110332494
Short name T889
Test name
Test status
Simulation time 49834541 ps
CPU time 0.81 seconds
Started Feb 29 02:24:35 PM PST 24
Finished Feb 29 02:24:36 PM PST 24
Peak memory 202672 kb
Host smart-4518460a-5e69-4f53-b65d-1e8a49d9719d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110332494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.4110332494
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.4136562636
Short name T490
Test name
Test status
Simulation time 4398050506 ps
CPU time 569.42 seconds
Started Feb 29 02:24:35 PM PST 24
Finished Feb 29 02:34:05 PM PST 24
Peak memory 370132 kb
Host smart-93c54487-b5f0-41f7-9e53-9a84db2bc2fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136562636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4136562636
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.526857208
Short name T165
Test name
Test status
Simulation time 2268602807 ps
CPU time 18.36 seconds
Started Feb 29 02:24:37 PM PST 24
Finished Feb 29 02:24:56 PM PST 24
Peak memory 202724 kb
Host smart-7647d331-ff45-4735-82c1-6e3d7953eed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526857208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.526857208
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.641916170
Short name T26
Test name
Test status
Simulation time 62478266020 ps
CPU time 4075.79 seconds
Started Feb 29 02:24:35 PM PST 24
Finished Feb 29 03:32:32 PM PST 24
Peak memory 382724 kb
Host smart-3e5b2db8-18ce-4db4-875f-fd8096596db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641916170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_stress_all.641916170
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.908754350
Short name T331
Test name
Test status
Simulation time 3475101415 ps
CPU time 339.85 seconds
Started Feb 29 02:24:33 PM PST 24
Finished Feb 29 02:30:13 PM PST 24
Peak memory 202676 kb
Host smart-c1776d95-b381-45e2-8817-8f176f95c7a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908754350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.sram_ctrl_stress_pipeline.908754350
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.151111892
Short name T772
Test name
Test status
Simulation time 486676108 ps
CPU time 98.79 seconds
Started Feb 29 02:24:33 PM PST 24
Finished Feb 29 02:26:12 PM PST 24
Peak memory 334384 kb
Host smart-d9a18db8-4b78-4c59-96ba-5678591c7843
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151111892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.151111892
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1192676369
Short name T13
Test name
Test status
Simulation time 20479704707 ps
CPU time 444.64 seconds
Started Feb 29 02:24:47 PM PST 24
Finished Feb 29 02:32:13 PM PST 24
Peak memory 370376 kb
Host smart-9d19f7cb-1652-4223-974f-3c72c0421b5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192676369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.1192676369
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.3720806855
Short name T288
Test name
Test status
Simulation time 51944426 ps
CPU time 0.64 seconds
Started Feb 29 02:24:45 PM PST 24
Finished Feb 29 02:24:47 PM PST 24
Peak memory 201552 kb
Host smart-db4e5e32-794d-4120-a7d5-c2b55e27f280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720806855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.3720806855
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2261531481
Short name T513
Test name
Test status
Simulation time 13051560530 ps
CPU time 75.31 seconds
Started Feb 29 02:24:37 PM PST 24
Finished Feb 29 02:25:53 PM PST 24
Peak memory 202728 kb
Host smart-27ed2b75-5655-4447-8bbe-74052dab9e1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261531481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2261531481
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.795456268
Short name T105
Test name
Test status
Simulation time 1775931962 ps
CPU time 1012.02 seconds
Started Feb 29 02:24:47 PM PST 24
Finished Feb 29 02:41:40 PM PST 24
Peak memory 369404 kb
Host smart-2fa88d93-6fdc-4d22-9237-4ca256076283
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795456268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executabl
e.795456268
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.3465445433
Short name T691
Test name
Test status
Simulation time 4821154115 ps
CPU time 6.04 seconds
Started Feb 29 02:24:45 PM PST 24
Finished Feb 29 02:24:51 PM PST 24
Peak memory 202696 kb
Host smart-19e55d4b-22e5-4753-8c37-f07f4ca41726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465445433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.3465445433
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.2211921732
Short name T444
Test name
Test status
Simulation time 531302521 ps
CPU time 147.03 seconds
Started Feb 29 02:24:45 PM PST 24
Finished Feb 29 02:27:13 PM PST 24
Peak memory 366712 kb
Host smart-444b7295-0826-4122-96de-d6e5e3758842
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211921732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.2211921732
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.527139123
Short name T214
Test name
Test status
Simulation time 128261251 ps
CPU time 5.22 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 02:24:52 PM PST 24
Peak memory 210840 kb
Host smart-5e63efce-ec74-4aa0-ba0d-5fff89a5c19f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527139123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.sram_ctrl_mem_partial_access.527139123
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.1352391226
Short name T715
Test name
Test status
Simulation time 1353203398 ps
CPU time 10.31 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 02:24:58 PM PST 24
Peak memory 202700 kb
Host smart-fec3ab32-8023-4888-aac1-1fa6093ff6d5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352391226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.1352391226
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.1528211621
Short name T133
Test name
Test status
Simulation time 9903408177 ps
CPU time 1127.31 seconds
Started Feb 29 02:24:35 PM PST 24
Finished Feb 29 02:43:24 PM PST 24
Peak memory 369368 kb
Host smart-04d3156a-d3e6-4ae8-9e47-61ce69e26296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528211621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.1528211621
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.2113717903
Short name T824
Test name
Test status
Simulation time 227626178 ps
CPU time 125.37 seconds
Started Feb 29 02:24:33 PM PST 24
Finished Feb 29 02:26:39 PM PST 24
Peak memory 373284 kb
Host smart-2ceae6ee-3528-498b-8470-b5d3b70a8be2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113717903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.2113717903
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3660243203
Short name T272
Test name
Test status
Simulation time 5846398354 ps
CPU time 403 seconds
Started Feb 29 02:24:44 PM PST 24
Finished Feb 29 02:31:27 PM PST 24
Peak memory 202732 kb
Host smart-2827a47b-c00c-492f-89a6-1819146e0f84
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660243203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.3660243203
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.1555324532
Short name T607
Test name
Test status
Simulation time 32261971 ps
CPU time 1.09 seconds
Started Feb 29 02:24:45 PM PST 24
Finished Feb 29 02:24:46 PM PST 24
Peak memory 202932 kb
Host smart-9205735b-c37b-497a-881a-303a11aa723d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555324532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1555324532
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.4224229241
Short name T469
Test name
Test status
Simulation time 93084829032 ps
CPU time 866.48 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 02:39:14 PM PST 24
Peak memory 340712 kb
Host smart-a4f7fda3-81cf-4c4b-905a-1f62c83ab5de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224229241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.4224229241
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.557537907
Short name T164
Test name
Test status
Simulation time 1905108595 ps
CPU time 19.07 seconds
Started Feb 29 02:24:33 PM PST 24
Finished Feb 29 02:24:54 PM PST 24
Peak memory 202624 kb
Host smart-0aaf9c66-3c69-421e-83fb-0ceb27ef5f5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557537907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.557537907
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.3857912584
Short name T732
Test name
Test status
Simulation time 37196701972 ps
CPU time 2941.29 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 03:13:49 PM PST 24
Peak memory 375532 kb
Host smart-680c572f-c26d-4790-a6c7-099cae7f8156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857912584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.3857912584
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2647925843
Short name T497
Test name
Test status
Simulation time 9186304210 ps
CPU time 220.63 seconds
Started Feb 29 02:24:33 PM PST 24
Finished Feb 29 02:28:13 PM PST 24
Peak memory 202756 kb
Host smart-8c443e1b-7825-479c-913b-2cd1c5aedbf0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647925843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2647925843
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1313367635
Short name T761
Test name
Test status
Simulation time 147798519 ps
CPU time 52.31 seconds
Started Feb 29 02:24:45 PM PST 24
Finished Feb 29 02:25:37 PM PST 24
Peak memory 329468 kb
Host smart-59bdad33-f039-4915-a3db-293e52d6e31d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313367635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1313367635
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.275346962
Short name T755
Test name
Test status
Simulation time 2547368378 ps
CPU time 674.8 seconds
Started Feb 29 02:24:57 PM PST 24
Finished Feb 29 02:36:13 PM PST 24
Peak memory 373500 kb
Host smart-26e77c01-073a-4c52-ac2d-458972675c97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275346962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.sram_ctrl_access_during_key_req.275346962
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.4011960567
Short name T319
Test name
Test status
Simulation time 47351642 ps
CPU time 0.66 seconds
Started Feb 29 02:24:58 PM PST 24
Finished Feb 29 02:24:59 PM PST 24
Peak memory 201556 kb
Host smart-6b414258-b9b4-444d-a40a-59c82e043d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011960567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.4011960567
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.2113094824
Short name T875
Test name
Test status
Simulation time 5579273107 ps
CPU time 50.79 seconds
Started Feb 29 02:24:47 PM PST 24
Finished Feb 29 02:25:38 PM PST 24
Peak memory 202668 kb
Host smart-446f7267-0a0b-4b54-b889-64cca041bc83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113094824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.2113094824
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.1718302751
Short name T393
Test name
Test status
Simulation time 2331759963 ps
CPU time 535.42 seconds
Started Feb 29 02:24:56 PM PST 24
Finished Feb 29 02:33:51 PM PST 24
Peak memory 363336 kb
Host smart-c5058929-4570-43c3-b578-e353b87d3dd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718302751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.1718302751
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.3706093766
Short name T128
Test name
Test status
Simulation time 110873289 ps
CPU time 98.28 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 02:26:26 PM PST 24
Peak memory 335104 kb
Host smart-794c9cba-01bc-4e6e-9785-85cb8b29c356
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706093766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.3706093766
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3487631284
Short name T172
Test name
Test status
Simulation time 76017097 ps
CPU time 2.98 seconds
Started Feb 29 02:24:57 PM PST 24
Finished Feb 29 02:25:00 PM PST 24
Peak memory 212076 kb
Host smart-148b202f-1ee6-49be-aeb7-56af3eaec44e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487631284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3487631284
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.1283711848
Short name T582
Test name
Test status
Simulation time 8124228437 ps
CPU time 10.62 seconds
Started Feb 29 02:24:58 PM PST 24
Finished Feb 29 02:25:09 PM PST 24
Peak memory 202672 kb
Host smart-e5882911-717d-4ef1-adeb-3f608a64bf45
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283711848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.1283711848
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.745878363
Short name T819
Test name
Test status
Simulation time 6340608655 ps
CPU time 191.85 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 02:27:59 PM PST 24
Peak memory 370444 kb
Host smart-06492d1e-a2b9-4cf0-8bb8-b1b7fd8d5238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745878363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip
le_keys.745878363
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.961448771
Short name T588
Test name
Test status
Simulation time 176445143 ps
CPU time 9.38 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 02:24:57 PM PST 24
Peak memory 202664 kb
Host smart-8fe64585-901b-4e4a-baa0-9007a8c874f5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961448771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s
ram_ctrl_partial_access.961448771
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3687029385
Short name T366
Test name
Test status
Simulation time 59670112903 ps
CPU time 367.21 seconds
Started Feb 29 02:24:46 PM PST 24
Finished Feb 29 02:30:54 PM PST 24
Peak memory 202752 kb
Host smart-fbf83966-61c4-4cd1-9c44-d840b15d94a1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687029385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.3687029385
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.3738791751
Short name T196
Test name
Test status
Simulation time 121351487 ps
CPU time 1.06 seconds
Started Feb 29 02:24:57 PM PST 24
Finished Feb 29 02:24:59 PM PST 24
Peak memory 202920 kb
Host smart-80fcc89d-56cb-4e09-9031-58f61876b987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738791751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3738791751
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.3081878371
Short name T666
Test name
Test status
Simulation time 15515775351 ps
CPU time 1229.75 seconds
Started Feb 29 02:24:58 PM PST 24
Finished Feb 29 02:45:28 PM PST 24
Peak memory 368344 kb
Host smart-fc15d277-9ace-4ab6-b400-9ae91a00f27c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081878371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3081878371
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.547127694
Short name T385
Test name
Test status
Simulation time 130641825 ps
CPU time 1.15 seconds
Started Feb 29 02:24:44 PM PST 24
Finished Feb 29 02:24:45 PM PST 24
Peak memory 202424 kb
Host smart-c6f7f973-9729-4e3e-879e-6a68c937606a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547127694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.547127694
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.167862791
Short name T786
Test name
Test status
Simulation time 15791283106 ps
CPU time 5347.38 seconds
Started Feb 29 02:24:57 PM PST 24
Finished Feb 29 03:54:06 PM PST 24
Peak memory 375516 kb
Host smart-6865f973-a6d3-43f0-80e0-7f1b0d0bb3dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167862791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_stress_all.167862791
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.104974219
Short name T430
Test name
Test status
Simulation time 15375621886 ps
CPU time 301.45 seconds
Started Feb 29 02:24:48 PM PST 24
Finished Feb 29 02:29:50 PM PST 24
Peak memory 202756 kb
Host smart-87e7b873-110c-4378-8010-de48a9fe327d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104974219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_stress_pipeline.104974219
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.4034613088
Short name T648
Test name
Test status
Simulation time 306967384 ps
CPU time 138.48 seconds
Started Feb 29 02:24:57 PM PST 24
Finished Feb 29 02:27:15 PM PST 24
Peak memory 364728 kb
Host smart-75ac57d2-470e-498a-ad33-9d50858def13
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034613088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.4034613088
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3143631691
Short name T486
Test name
Test status
Simulation time 29469335607 ps
CPU time 511.97 seconds
Started Feb 29 02:25:16 PM PST 24
Finished Feb 29 02:33:48 PM PST 24
Peak memory 346952 kb
Host smart-ed899344-f660-4e08-843f-d5509d690309
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143631691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.3143631691
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.334043806
Short name T752
Test name
Test status
Simulation time 34993012 ps
CPU time 0.67 seconds
Started Feb 29 02:25:16 PM PST 24
Finished Feb 29 02:25:17 PM PST 24
Peak memory 201528 kb
Host smart-144ceab9-0626-42a7-b210-584b1ae0840c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334043806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.334043806
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.946469850
Short name T250
Test name
Test status
Simulation time 10440511923 ps
CPU time 43.02 seconds
Started Feb 29 02:24:58 PM PST 24
Finished Feb 29 02:25:41 PM PST 24
Peak memory 202704 kb
Host smart-4155fd68-1851-4c59-b6c5-35848ec1741e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946469850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
946469850
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.2834604818
Short name T581
Test name
Test status
Simulation time 15513420993 ps
CPU time 1962.74 seconds
Started Feb 29 02:25:16 PM PST 24
Finished Feb 29 02:57:59 PM PST 24
Peak memory 374512 kb
Host smart-8bd6dcf5-df49-4a52-8ca6-d10e39d8285d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834604818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.2834604818
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.3748606571
Short name T656
Test name
Test status
Simulation time 953812339 ps
CPU time 12.59 seconds
Started Feb 29 02:25:17 PM PST 24
Finished Feb 29 02:25:30 PM PST 24
Peak memory 210868 kb
Host smart-bf4dfac1-ab89-49aa-84f1-f9c38dd322af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748606571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.3748606571
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.1141979665
Short name T410
Test name
Test status
Simulation time 115228788 ps
CPU time 86.08 seconds
Started Feb 29 02:24:57 PM PST 24
Finished Feb 29 02:26:23 PM PST 24
Peak memory 321248 kb
Host smart-27c43912-b72a-4e17-b25f-bff73e302172
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141979665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.1141979665
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3079164628
Short name T521
Test name
Test status
Simulation time 594841665 ps
CPU time 5.14 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:25:20 PM PST 24
Peak memory 210852 kb
Host smart-5edfd457-9e3a-4b7d-8a0d-37239f1932cc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079164628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.3079164628
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.3568128941
Short name T719
Test name
Test status
Simulation time 1377501450 ps
CPU time 5.38 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:25:21 PM PST 24
Peak memory 202596 kb
Host smart-e7976c4e-81ac-44c3-8266-d91af90010c4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568128941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.3568128941
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1951909294
Short name T812
Test name
Test status
Simulation time 1488608942 ps
CPU time 21.92 seconds
Started Feb 29 02:24:58 PM PST 24
Finished Feb 29 02:25:20 PM PST 24
Peak memory 240732 kb
Host smart-8d16d577-062c-452d-b00b-ea0160425ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951909294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1951909294
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.1276535517
Short name T500
Test name
Test status
Simulation time 4169663035 ps
CPU time 17.91 seconds
Started Feb 29 02:24:56 PM PST 24
Finished Feb 29 02:25:14 PM PST 24
Peak memory 202696 kb
Host smart-99dde548-fa7c-428c-8470-0153223e3e02
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276535517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.1276535517
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1670632478
Short name T152
Test name
Test status
Simulation time 29008004324 ps
CPU time 714.6 seconds
Started Feb 29 02:24:56 PM PST 24
Finished Feb 29 02:36:51 PM PST 24
Peak memory 202776 kb
Host smart-f2a19d14-4d22-4063-97fc-2103a8f0bbc7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670632478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.1670632478
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.2436692966
Short name T317
Test name
Test status
Simulation time 41231988 ps
CPU time 1.12 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:25:16 PM PST 24
Peak memory 202928 kb
Host smart-022fb772-7555-4d09-9342-1afeb41ae785
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436692966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2436692966
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.1476723608
Short name T710
Test name
Test status
Simulation time 12058920670 ps
CPU time 593.29 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:35:08 PM PST 24
Peak memory 359808 kb
Host smart-4b5c3932-4dea-42dd-926a-33d918643ce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476723608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1476723608
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.2714287644
Short name T243
Test name
Test status
Simulation time 6074927452 ps
CPU time 19.95 seconds
Started Feb 29 02:24:57 PM PST 24
Finished Feb 29 02:25:17 PM PST 24
Peak memory 202768 kb
Host smart-60e90bd7-8029-4b56-af41-3b2eb4bbbe6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714287644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2714287644
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1925388162
Short name T548
Test name
Test status
Simulation time 2135016770 ps
CPU time 198.35 seconds
Started Feb 29 02:24:59 PM PST 24
Finished Feb 29 02:28:17 PM PST 24
Peak memory 202696 kb
Host smart-b306821e-c3b5-4c43-8bbc-c8b24cb0aa8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925388162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.1925388162
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1902706942
Short name T676
Test name
Test status
Simulation time 99788859 ps
CPU time 41.5 seconds
Started Feb 29 02:24:56 PM PST 24
Finished Feb 29 02:25:37 PM PST 24
Peak memory 283688 kb
Host smart-d24b04c5-f1f7-43b5-9e7c-55fc61928603
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902706942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1902706942
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.163791818
Short name T782
Test name
Test status
Simulation time 4265598057 ps
CPU time 504.25 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:33:54 PM PST 24
Peak memory 371904 kb
Host smart-7ad05df5-2ed8-41c2-8ace-67d15eab37d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163791818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.sram_ctrl_access_during_key_req.163791818
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.3352108446
Short name T370
Test name
Test status
Simulation time 85136906 ps
CPU time 0.67 seconds
Started Feb 29 02:25:27 PM PST 24
Finished Feb 29 02:25:28 PM PST 24
Peak memory 201544 kb
Host smart-7615ab8d-73a7-42b8-a44d-16626863019f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352108446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.3352108446
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.3866338986
Short name T821
Test name
Test status
Simulation time 1929163797 ps
CPU time 60.31 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:26:15 PM PST 24
Peak memory 202688 kb
Host smart-1c825d9b-6643-436d-a759-3ae585369d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866338986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.3866338986
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.3554672764
Short name T641
Test name
Test status
Simulation time 35660065744 ps
CPU time 911.75 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:40:40 PM PST 24
Peak memory 373316 kb
Host smart-1fcb31a8-0a51-4b5f-8c49-b09cc58aa53e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554672764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.3554672764
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.291011891
Short name T93
Test name
Test status
Simulation time 1414329351 ps
CPU time 3.39 seconds
Started Feb 29 02:25:31 PM PST 24
Finished Feb 29 02:25:34 PM PST 24
Peak memory 202664 kb
Host smart-1c4db0d9-b3be-419b-af9b-b7020d47b729
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291011891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc
alation.291011891
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.106484224
Short name T8
Test name
Test status
Simulation time 86172405 ps
CPU time 6.3 seconds
Started Feb 29 02:25:32 PM PST 24
Finished Feb 29 02:25:39 PM PST 24
Peak memory 224456 kb
Host smart-d263619c-e619-41a9-945f-c58889ed1b8b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106484224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.sram_ctrl_max_throughput.106484224
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1546207352
Short name T882
Test name
Test status
Simulation time 1150610737 ps
CPU time 6.05 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:25:35 PM PST 24
Peak memory 210876 kb
Host smart-341ea724-cb53-46ff-8239-a1dfd63bd121
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546207352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.1546207352
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2261738637
Short name T584
Test name
Test status
Simulation time 1309372269 ps
CPU time 10.64 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:25:39 PM PST 24
Peak memory 202620 kb
Host smart-7b77d60d-e564-4051-81b7-92aa4082dc50
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261738637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2261738637
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.1117390564
Short name T662
Test name
Test status
Simulation time 6900856305 ps
CPU time 624.12 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:35:39 PM PST 24
Peak memory 369356 kb
Host smart-10b73f39-e29e-41ac-a347-89306f86d00f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117390564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.1117390564
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2679348026
Short name T642
Test name
Test status
Simulation time 1810473990 ps
CPU time 19.14 seconds
Started Feb 29 02:25:16 PM PST 24
Finished Feb 29 02:25:35 PM PST 24
Peak memory 202620 kb
Host smart-be07a99d-02ba-46da-bdca-0c4476a04fa1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679348026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2679348026
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2791703488
Short name T697
Test name
Test status
Simulation time 22481651921 ps
CPU time 290.75 seconds
Started Feb 29 02:25:17 PM PST 24
Finished Feb 29 02:30:07 PM PST 24
Peak memory 202720 kb
Host smart-7d515a91-e49f-4091-9a02-80d3f870bfe3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791703488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.2791703488
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3564077161
Short name T817
Test name
Test status
Simulation time 27629958 ps
CPU time 0.86 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:25:31 PM PST 24
Peak memory 202628 kb
Host smart-5db97b88-70d4-462a-9412-cac136111b77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564077161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3564077161
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.2408460982
Short name T9
Test name
Test status
Simulation time 16903872957 ps
CPU time 1001.07 seconds
Started Feb 29 02:25:27 PM PST 24
Finished Feb 29 02:42:09 PM PST 24
Peak memory 374532 kb
Host smart-0b63ac9d-638a-4ea1-829c-21cc49117894
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408460982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2408460982
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.2844245895
Short name T635
Test name
Test status
Simulation time 55805160 ps
CPU time 3.39 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:25:19 PM PST 24
Peak memory 202684 kb
Host smart-3911c562-dcc9-466a-a85c-f181bd612ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844245895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2844245895
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.3386612271
Short name T302
Test name
Test status
Simulation time 13154373272 ps
CPU time 1609.01 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:52:17 PM PST 24
Peak memory 373480 kb
Host smart-854ed847-ed6c-4431-a281-d4e35a42a39d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386612271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.3386612271
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.833747864
Short name T849
Test name
Test status
Simulation time 16761895705 ps
CPU time 422.03 seconds
Started Feb 29 02:25:15 PM PST 24
Finished Feb 29 02:32:17 PM PST 24
Peak memory 202752 kb
Host smart-271071ca-cb34-424c-a955-92657e8e5af6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833747864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_stress_pipeline.833747864
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3989967860
Short name T837
Test name
Test status
Simulation time 48520222 ps
CPU time 2.72 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:25:33 PM PST 24
Peak memory 210880 kb
Host smart-7bbace26-d16b-45bf-ba86-08814f59ff81
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989967860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3989967860
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3830193782
Short name T781
Test name
Test status
Simulation time 8076552770 ps
CPU time 1139.2 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:44:29 PM PST 24
Peak memory 375588 kb
Host smart-a15c002a-28f3-48e7-8d4f-17e97c7ea6a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830193782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.3830193782
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2149262741
Short name T467
Test name
Test status
Simulation time 26857914 ps
CPU time 0.65 seconds
Started Feb 29 02:25:38 PM PST 24
Finished Feb 29 02:25:38 PM PST 24
Peak memory 201684 kb
Host smart-b5c85875-09b4-4355-9eb5-f99c89a892d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149262741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2149262741
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.404710887
Short name T608
Test name
Test status
Simulation time 1116779500 ps
CPU time 36.26 seconds
Started Feb 29 02:25:30 PM PST 24
Finished Feb 29 02:26:07 PM PST 24
Peak memory 202696 kb
Host smart-469aed0b-6c45-4fff-9d58-96edfb0d0a51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404710887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.
404710887
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.1960635001
Short name T434
Test name
Test status
Simulation time 10883983524 ps
CPU time 420.36 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:32:30 PM PST 24
Peak memory 373380 kb
Host smart-698bbf1f-707b-4418-bd7a-599a94169ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960635001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.1960635001
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.2676742762
Short name T428
Test name
Test status
Simulation time 359672800 ps
CPU time 7.13 seconds
Started Feb 29 02:25:30 PM PST 24
Finished Feb 29 02:25:37 PM PST 24
Peak memory 210944 kb
Host smart-e612b001-a6f1-4f8f-8c30-4d664a14ff49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676742762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.2676742762
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.2213812262
Short name T603
Test name
Test status
Simulation time 139112201 ps
CPU time 136.97 seconds
Started Feb 29 02:25:30 PM PST 24
Finished Feb 29 02:27:47 PM PST 24
Peak memory 350108 kb
Host smart-0acb5622-04db-49f9-ae13-25fe7b92d8e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213812262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.2213812262
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.221446594
Short name T507
Test name
Test status
Simulation time 49716365 ps
CPU time 3.1 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:25:33 PM PST 24
Peak memory 211132 kb
Host smart-e25c1203-2331-42d4-afd9-8733f6f6b3d9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221446594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.221446594
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.3616239024
Short name T297
Test name
Test status
Simulation time 878214995 ps
CPU time 10.45 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:25:40 PM PST 24
Peak memory 202672 kb
Host smart-5aa65d82-d3eb-4e63-9eef-37aea603e4ad
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616239024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.3616239024
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.1096019405
Short name T570
Test name
Test status
Simulation time 9158218773 ps
CPU time 1547.6 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:51:16 PM PST 24
Peak memory 375392 kb
Host smart-fdd146b5-4cdf-489f-9660-4a608441774f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096019405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.1096019405
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.490609364
Short name T348
Test name
Test status
Simulation time 251009715 ps
CPU time 14.74 seconds
Started Feb 29 02:25:32 PM PST 24
Finished Feb 29 02:25:47 PM PST 24
Peak memory 247600 kb
Host smart-7f66e435-c667-4ec2-a345-effcdcf45559
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490609364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s
ram_ctrl_partial_access.490609364
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2294478922
Short name T734
Test name
Test status
Simulation time 2323319375 ps
CPU time 163.99 seconds
Started Feb 29 02:25:29 PM PST 24
Finished Feb 29 02:28:13 PM PST 24
Peak memory 202808 kb
Host smart-c04bdefc-bb9f-49e4-8060-e9645f9ad993
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294478922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.2294478922
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.1646632569
Short name T329
Test name
Test status
Simulation time 328822542 ps
CPU time 1.05 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:25:29 PM PST 24
Peak memory 202860 kb
Host smart-a42f729b-95f4-4263-8d21-95c762a7212a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646632569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1646632569
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.4107129656
Short name T779
Test name
Test status
Simulation time 50285906832 ps
CPU time 1184.54 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:45:13 PM PST 24
Peak memory 373836 kb
Host smart-26411f0c-9e88-4c12-9df3-0d7cf5b97cd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107129656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.4107129656
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.2342383405
Short name T258
Test name
Test status
Simulation time 861993305 ps
CPU time 13.36 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:25:42 PM PST 24
Peak memory 202680 kb
Host smart-38968e95-5e2e-4c4d-8a31-a85e2906d053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342383405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2342383405
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3698233270
Short name T462
Test name
Test status
Simulation time 3324268332 ps
CPU time 310.02 seconds
Started Feb 29 02:25:31 PM PST 24
Finished Feb 29 02:30:41 PM PST 24
Peak memory 202772 kb
Host smart-e2b15457-25ca-4bb7-b226-ed1a56663284
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698233270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.3698233270
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3239379291
Short name T764
Test name
Test status
Simulation time 468703640 ps
CPU time 58.99 seconds
Started Feb 29 02:25:28 PM PST 24
Finished Feb 29 02:26:27 PM PST 24
Peak memory 305932 kb
Host smart-26916c68-4339-47c4-b12f-fd4d5bdd0402
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239379291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3239379291
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2829318236
Short name T72
Test name
Test status
Simulation time 7912566835 ps
CPU time 269.35 seconds
Started Feb 29 02:25:35 PM PST 24
Finished Feb 29 02:30:05 PM PST 24
Peak memory 371092 kb
Host smart-ff326d5c-eed3-48c1-99bb-ca20b96e8104
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829318236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.2829318236
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.3855603938
Short name T795
Test name
Test status
Simulation time 26828079 ps
CPU time 0.61 seconds
Started Feb 29 02:25:38 PM PST 24
Finished Feb 29 02:25:39 PM PST 24
Peak memory 202416 kb
Host smart-94294b46-9c3f-4cc6-a35e-038735c4e4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855603938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.3855603938
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.1194940668
Short name T182
Test name
Test status
Simulation time 788707525 ps
CPU time 50.03 seconds
Started Feb 29 02:25:37 PM PST 24
Finished Feb 29 02:26:28 PM PST 24
Peak memory 202700 kb
Host smart-7f97667f-9b2a-4154-8b84-cd2cd35c2f74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194940668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.1194940668
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.4133328140
Short name T282
Test name
Test status
Simulation time 11949576610 ps
CPU time 1468.28 seconds
Started Feb 29 02:25:39 PM PST 24
Finished Feb 29 02:50:08 PM PST 24
Peak memory 373584 kb
Host smart-c3d06050-88f3-4bc9-b021-89923b06a900
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133328140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.4133328140
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.428080786
Short name T382
Test name
Test status
Simulation time 1593576287 ps
CPU time 5.91 seconds
Started Feb 29 02:25:42 PM PST 24
Finished Feb 29 02:25:48 PM PST 24
Peak memory 210856 kb
Host smart-64e88157-1524-4551-92c6-1ec169eb1018
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428080786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esc
alation.428080786
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.2991757322
Short name T549
Test name
Test status
Simulation time 45581901 ps
CPU time 3.52 seconds
Started Feb 29 02:25:38 PM PST 24
Finished Feb 29 02:25:41 PM PST 24
Peak memory 219036 kb
Host smart-cb7e3f7b-0c2f-49f5-9cbd-5449cfb5c58d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991757322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.2991757322
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1774860485
Short name T224
Test name
Test status
Simulation time 75696023 ps
CPU time 5.23 seconds
Started Feb 29 02:25:42 PM PST 24
Finished Feb 29 02:25:47 PM PST 24
Peak memory 211848 kb
Host smart-02a6ebbe-3b91-4bc8-8a51-936efd7a7013
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774860485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.1774860485
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.134035347
Short name T477
Test name
Test status
Simulation time 560419675 ps
CPU time 9.45 seconds
Started Feb 29 02:25:37 PM PST 24
Finished Feb 29 02:25:46 PM PST 24
Peak memory 202616 kb
Host smart-53cf15d5-6bcd-465f-9423-b933c9277174
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134035347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl
_mem_walk.134035347
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.2424450610
Short name T491
Test name
Test status
Simulation time 7811555939 ps
CPU time 432.66 seconds
Started Feb 29 02:25:39 PM PST 24
Finished Feb 29 02:32:52 PM PST 24
Peak memory 365184 kb
Host smart-29a4025f-a17b-474e-bc8b-68dbfb0a200b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424450610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.2424450610
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.2862066068
Short name T540
Test name
Test status
Simulation time 363258149 ps
CPU time 4.97 seconds
Started Feb 29 02:25:39 PM PST 24
Finished Feb 29 02:25:44 PM PST 24
Peak memory 202668 kb
Host smart-011364bd-449d-47be-8f04-fad0ee2abd07
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862066068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.2862066068
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1513796605
Short name T872
Test name
Test status
Simulation time 16845144349 ps
CPU time 353.94 seconds
Started Feb 29 02:25:37 PM PST 24
Finished Feb 29 02:31:31 PM PST 24
Peak memory 202760 kb
Host smart-6b5d77f1-d22c-4540-92f0-3d4f804e1078
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513796605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.1513796605
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.2445975867
Short name T199
Test name
Test status
Simulation time 27004329 ps
CPU time 0.84 seconds
Started Feb 29 02:25:37 PM PST 24
Finished Feb 29 02:25:38 PM PST 24
Peak memory 202720 kb
Host smart-e7a347dd-2c93-45c1-bb39-c6ecb05a6c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445975867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2445975867
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.3153243854
Short name T689
Test name
Test status
Simulation time 7192600919 ps
CPU time 346.06 seconds
Started Feb 29 02:25:38 PM PST 24
Finished Feb 29 02:31:24 PM PST 24
Peak memory 356092 kb
Host smart-233e1793-bce4-4c29-92db-6c6b1b37c758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153243854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3153243854
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.1548981019
Short name T856
Test name
Test status
Simulation time 598154687 ps
CPU time 14.73 seconds
Started Feb 29 02:25:42 PM PST 24
Finished Feb 29 02:25:57 PM PST 24
Peak memory 202564 kb
Host smart-e18b7ac6-af8b-47f1-a902-8b5d33be8cbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548981019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1548981019
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.2135127288
Short name T395
Test name
Test status
Simulation time 110927775838 ps
CPU time 3299.79 seconds
Started Feb 29 02:25:38 PM PST 24
Finished Feb 29 03:20:39 PM PST 24
Peak memory 382700 kb
Host smart-27096ec3-68c9-46f1-8236-7940f6f2c81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135127288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.2135127288
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1661512159
Short name T559
Test name
Test status
Simulation time 2861301215 ps
CPU time 252.23 seconds
Started Feb 29 02:25:37 PM PST 24
Finished Feb 29 02:29:50 PM PST 24
Peak memory 202764 kb
Host smart-602f8b99-2f24-477e-8d53-0c3bacb10a26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661512159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.1661512159
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.652414076
Short name T728
Test name
Test status
Simulation time 954559031 ps
CPU time 49.25 seconds
Started Feb 29 02:25:37 PM PST 24
Finished Feb 29 02:26:27 PM PST 24
Peak memory 292820 kb
Host smart-bd367745-a69f-43ea-a4f2-353c4fc861eb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652414076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.652414076
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3952736313
Short name T180
Test name
Test status
Simulation time 3248252941 ps
CPU time 913.97 seconds
Started Feb 29 02:25:49 PM PST 24
Finished Feb 29 02:41:03 PM PST 24
Peak memory 373472 kb
Host smart-6b0e6640-c08d-4f9e-b63a-da8d9ca6b0b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952736313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.3952736313
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.4197294924
Short name T292
Test name
Test status
Simulation time 53843447 ps
CPU time 0.66 seconds
Started Feb 29 02:25:59 PM PST 24
Finished Feb 29 02:26:00 PM PST 24
Peak memory 202384 kb
Host smart-28010d6b-cc6f-4704-aa04-0623644de104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197294924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.4197294924
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.4050966687
Short name T604
Test name
Test status
Simulation time 1403448139 ps
CPU time 45.82 seconds
Started Feb 29 02:25:49 PM PST 24
Finished Feb 29 02:26:35 PM PST 24
Peak memory 202700 kb
Host smart-35c0d57e-b580-4e3f-bb30-2706c98655e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050966687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.4050966687
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.2112214609
Short name T844
Test name
Test status
Simulation time 6758716253 ps
CPU time 1283.53 seconds
Started Feb 29 02:25:48 PM PST 24
Finished Feb 29 02:47:13 PM PST 24
Peak memory 373540 kb
Host smart-7e56f6d8-066b-4442-a953-51de3dedc275
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112214609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.2112214609
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.2121411663
Short name T350
Test name
Test status
Simulation time 3824346302 ps
CPU time 7.16 seconds
Started Feb 29 02:25:49 PM PST 24
Finished Feb 29 02:25:57 PM PST 24
Peak memory 213760 kb
Host smart-cb0c176b-eeeb-44a4-aca2-c894b1ed77a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121411663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.2121411663
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.2879453671
Short name T841
Test name
Test status
Simulation time 90102360 ps
CPU time 29.75 seconds
Started Feb 29 02:25:48 PM PST 24
Finished Feb 29 02:26:18 PM PST 24
Peak memory 284248 kb
Host smart-0f65da6b-74ea-45b0-b02a-9fc6baf686e2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879453671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.2879453671
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2440819426
Short name T775
Test name
Test status
Simulation time 340857314 ps
CPU time 3.09 seconds
Started Feb 29 02:26:00 PM PST 24
Finished Feb 29 02:26:03 PM PST 24
Peak memory 210904 kb
Host smart-6ee2e989-cfa1-4591-83b5-0b3bb49b4b75
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440819426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.2440819426
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.485821962
Short name T252
Test name
Test status
Simulation time 443897990 ps
CPU time 9.58 seconds
Started Feb 29 02:25:58 PM PST 24
Finished Feb 29 02:26:08 PM PST 24
Peak memory 202608 kb
Host smart-54b87de8-7d48-4fa3-bb42-768278e75341
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485821962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl
_mem_walk.485821962
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.412350578
Short name T868
Test name
Test status
Simulation time 1169895990 ps
CPU time 73.6 seconds
Started Feb 29 02:25:48 PM PST 24
Finished Feb 29 02:27:03 PM PST 24
Peak memory 308056 kb
Host smart-0fcec4f6-293c-4163-b909-ff9882472299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412350578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip
le_keys.412350578
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.114192701
Short name T637
Test name
Test status
Simulation time 129612007 ps
CPU time 2.82 seconds
Started Feb 29 02:25:48 PM PST 24
Finished Feb 29 02:25:51 PM PST 24
Peak memory 202688 kb
Host smart-e6286f0a-2be6-4b2b-8921-433d7cfb465f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114192701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s
ram_ctrl_partial_access.114192701
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.275993930
Short name T577
Test name
Test status
Simulation time 55741697081 ps
CPU time 344.65 seconds
Started Feb 29 02:25:53 PM PST 24
Finished Feb 29 02:31:38 PM PST 24
Peak memory 202700 kb
Host smart-cd9d5d54-1b3b-47c0-a5f8-58a701be985a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275993930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.sram_ctrl_partial_access_b2b.275993930
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.2355922323
Short name T801
Test name
Test status
Simulation time 30440603 ps
CPU time 1.21 seconds
Started Feb 29 02:26:01 PM PST 24
Finished Feb 29 02:26:03 PM PST 24
Peak memory 202912 kb
Host smart-7c2abef9-99c1-4dc4-b57c-d81f629c28fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355922323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2355922323
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.2996591657
Short name T494
Test name
Test status
Simulation time 7684737828 ps
CPU time 717.1 seconds
Started Feb 29 02:25:59 PM PST 24
Finished Feb 29 02:37:56 PM PST 24
Peak memory 373136 kb
Host smart-a3f343f8-7b75-49cc-bcd4-9e395c010590
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996591657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2996591657
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.2489538383
Short name T142
Test name
Test status
Simulation time 2215013816 ps
CPU time 12.26 seconds
Started Feb 29 02:25:51 PM PST 24
Finished Feb 29 02:26:04 PM PST 24
Peak memory 202864 kb
Host smart-1412305a-731d-4cdf-ab87-14d57eb2ce7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489538383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2489538383
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.3436200589
Short name T780
Test name
Test status
Simulation time 175921081782 ps
CPU time 2694.02 seconds
Started Feb 29 02:26:00 PM PST 24
Finished Feb 29 03:10:55 PM PST 24
Peak memory 373492 kb
Host smart-ccf6fa2f-f6a4-40bd-b9f2-d4fec9e82ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436200589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.3436200589
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1061949470
Short name T338
Test name
Test status
Simulation time 14247472563 ps
CPU time 308.44 seconds
Started Feb 29 02:25:52 PM PST 24
Finished Feb 29 02:31:01 PM PST 24
Peak memory 202780 kb
Host smart-7e2429eb-4046-44e3-83b3-4c3913789ea3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061949470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1061949470
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2025162222
Short name T235
Test name
Test status
Simulation time 372817675 ps
CPU time 28.02 seconds
Started Feb 29 02:25:48 PM PST 24
Finished Feb 29 02:26:17 PM PST 24
Peak memory 284336 kb
Host smart-97e2113b-7d3b-4f42-9006-7e7e02abd58d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025162222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2025162222
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2259983135
Short name T646
Test name
Test status
Simulation time 3629890849 ps
CPU time 1047.66 seconds
Started Feb 29 02:25:58 PM PST 24
Finished Feb 29 02:43:27 PM PST 24
Peak memory 373464 kb
Host smart-80916328-da83-4be7-b0e6-2a09fc6a8dd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259983135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.2259983135
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.2049341284
Short name T850
Test name
Test status
Simulation time 15363874 ps
CPU time 0.63 seconds
Started Feb 29 02:26:15 PM PST 24
Finished Feb 29 02:26:16 PM PST 24
Peak memory 201712 kb
Host smart-76fc8120-97f8-4e31-8f91-a126e278b2f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049341284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.2049341284
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.552802369
Short name T179
Test name
Test status
Simulation time 764916127 ps
CPU time 16.22 seconds
Started Feb 29 02:26:00 PM PST 24
Finished Feb 29 02:26:16 PM PST 24
Peak memory 202676 kb
Host smart-9f327f13-16df-44bd-ae1d-206243d3450e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552802369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.
552802369
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.3206490941
Short name T552
Test name
Test status
Simulation time 73345642877 ps
CPU time 920.11 seconds
Started Feb 29 02:25:59 PM PST 24
Finished Feb 29 02:41:19 PM PST 24
Peak memory 351768 kb
Host smart-7287724f-becf-48d3-ae4d-5661dd92a6ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206490941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.3206490941
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.481033076
Short name T619
Test name
Test status
Simulation time 1561691137 ps
CPU time 10.54 seconds
Started Feb 29 02:25:59 PM PST 24
Finished Feb 29 02:26:10 PM PST 24
Peak memory 202736 kb
Host smart-8fc9f923-d4bf-4b43-acec-14182bd51f25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481033076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_esc
alation.481033076
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.4014286815
Short name T449
Test name
Test status
Simulation time 83237226 ps
CPU time 4.41 seconds
Started Feb 29 02:25:59 PM PST 24
Finished Feb 29 02:26:04 PM PST 24
Peak memory 219124 kb
Host smart-b85e5f5e-4855-4342-80b4-c3c06f1f118e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014286815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.4014286815
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.157878401
Short name T886
Test name
Test status
Simulation time 155057820 ps
CPU time 5.27 seconds
Started Feb 29 02:26:10 PM PST 24
Finished Feb 29 02:26:15 PM PST 24
Peak memory 210876 kb
Host smart-994dc895-6e30-4461-9a32-cee2dece467d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157878401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_mem_partial_access.157878401
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.2936379929
Short name T816
Test name
Test status
Simulation time 1748000630 ps
CPU time 10.78 seconds
Started Feb 29 02:26:11 PM PST 24
Finished Feb 29 02:26:22 PM PST 24
Peak memory 202660 kb
Host smart-1cf860f4-beb2-4a57-b5d7-6d570adb42e7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936379929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.2936379929
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.105047223
Short name T344
Test name
Test status
Simulation time 15935102644 ps
CPU time 285.14 seconds
Started Feb 29 02:26:00 PM PST 24
Finished Feb 29 02:30:45 PM PST 24
Peak memory 375040 kb
Host smart-6843a927-8771-47c7-920c-f146c5507e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105047223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.105047223
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.2647294256
Short name T374
Test name
Test status
Simulation time 602341771 ps
CPU time 60.03 seconds
Started Feb 29 02:25:58 PM PST 24
Finished Feb 29 02:26:59 PM PST 24
Peak memory 310788 kb
Host smart-456c8254-daa2-4c93-9394-35dc1d8f132f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647294256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.2647294256
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2224567891
Short name T861
Test name
Test status
Simulation time 11724403691 ps
CPU time 328.72 seconds
Started Feb 29 02:25:59 PM PST 24
Finished Feb 29 02:31:28 PM PST 24
Peak memory 202740 kb
Host smart-85bfd237-fe47-4c3b-abb4-5f52828e6d5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224567891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.2224567891
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.3281696442
Short name T590
Test name
Test status
Simulation time 84249430 ps
CPU time 0.82 seconds
Started Feb 29 02:26:10 PM PST 24
Finished Feb 29 02:26:11 PM PST 24
Peak memory 202636 kb
Host smart-79ecf7e6-d421-4c69-8f6b-ac34c92790d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281696442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3281696442
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.4022622637
Short name T473
Test name
Test status
Simulation time 2485647437 ps
CPU time 244.81 seconds
Started Feb 29 02:26:14 PM PST 24
Finished Feb 29 02:30:19 PM PST 24
Peak memory 359120 kb
Host smart-577d9d82-ea68-43be-9879-5ca2ad606ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022622637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.4022622637
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.1260405961
Short name T857
Test name
Test status
Simulation time 113824300 ps
CPU time 2.77 seconds
Started Feb 29 02:25:59 PM PST 24
Finished Feb 29 02:26:02 PM PST 24
Peak memory 202684 kb
Host smart-df0ad8b7-c6db-46b8-9a3b-fbde48816061
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260405961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1260405961
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.2826217040
Short name T253
Test name
Test status
Simulation time 51433860667 ps
CPU time 3390.07 seconds
Started Feb 29 02:26:10 PM PST 24
Finished Feb 29 03:22:40 PM PST 24
Peak memory 382688 kb
Host smart-bcc4964e-5466-4e3c-8d11-25c0bf8bad4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826217040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.2826217040
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1087147167
Short name T432
Test name
Test status
Simulation time 6296114664 ps
CPU time 319.67 seconds
Started Feb 29 02:26:00 PM PST 24
Finished Feb 29 02:31:20 PM PST 24
Peak memory 202812 kb
Host smart-4e4f593a-eecf-4294-a877-67af26f7d358
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087147167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.1087147167
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1896995285
Short name T144
Test name
Test status
Simulation time 301346789 ps
CPU time 155.96 seconds
Started Feb 29 02:26:00 PM PST 24
Finished Feb 29 02:28:36 PM PST 24
Peak memory 366104 kb
Host smart-9d728d82-5706-4877-8c32-d67e12bb5ff3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896995285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1896995285
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2287423879
Short name T10
Test name
Test status
Simulation time 7430129876 ps
CPU time 1231.3 seconds
Started Feb 29 02:26:22 PM PST 24
Finished Feb 29 02:46:54 PM PST 24
Peak memory 375484 kb
Host smart-1c9bcc81-7d57-4bdb-866e-27d81611b208
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287423879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.2287423879
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.413653565
Short name T520
Test name
Test status
Simulation time 28580487 ps
CPU time 0.63 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 02:26:25 PM PST 24
Peak memory 201716 kb
Host smart-47d2756f-bcad-48cc-affd-0e18cd59efcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413653565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.413653565
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.594063497
Short name T266
Test name
Test status
Simulation time 10422855299 ps
CPU time 44.1 seconds
Started Feb 29 02:26:10 PM PST 24
Finished Feb 29 02:26:54 PM PST 24
Peak memory 202760 kb
Host smart-0f4f638f-f75f-431d-825a-5a225b9bdb24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594063497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.
594063497
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.1198238072
Short name T384
Test name
Test status
Simulation time 15046685406 ps
CPU time 2474.39 seconds
Started Feb 29 02:26:23 PM PST 24
Finished Feb 29 03:07:38 PM PST 24
Peak memory 374496 kb
Host smart-3fd2d1e4-bdcc-4ff6-a65e-8188b0f1b9bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198238072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.1198238072
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1979134772
Short name T280
Test name
Test status
Simulation time 1008407526 ps
CPU time 10.33 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 02:26:35 PM PST 24
Peak memory 202680 kb
Host smart-ced61287-ab74-4540-8978-c954dde24650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979134772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1979134772
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3881370358
Short name T493
Test name
Test status
Simulation time 83554344 ps
CPU time 21.97 seconds
Started Feb 29 02:26:23 PM PST 24
Finished Feb 29 02:26:45 PM PST 24
Peak memory 268108 kb
Host smart-3ca629d2-b858-4ca2-904d-09c681d37611
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881370358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3881370358
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2028654349
Short name T75
Test name
Test status
Simulation time 64061059 ps
CPU time 4.96 seconds
Started Feb 29 02:26:23 PM PST 24
Finished Feb 29 02:26:28 PM PST 24
Peak memory 212020 kb
Host smart-5dc4c84d-85d9-4aa1-ade9-4483571e6da5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028654349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.2028654349
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.12688040
Short name T136
Test name
Test status
Simulation time 600163827 ps
CPU time 5.72 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 02:26:30 PM PST 24
Peak memory 202652 kb
Host smart-f8277c65-6d4a-4a25-a45e-20a0e84be752
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12688040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_
mem_walk.12688040
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3217984617
Short name T326
Test name
Test status
Simulation time 2343609186 ps
CPU time 171.12 seconds
Started Feb 29 02:26:14 PM PST 24
Finished Feb 29 02:29:06 PM PST 24
Peak memory 323868 kb
Host smart-688b9076-1de1-4a48-8ba8-7f992cda17f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217984617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3217984617
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.933427303
Short name T274
Test name
Test status
Simulation time 622219071 ps
CPU time 2.14 seconds
Started Feb 29 02:26:10 PM PST 24
Finished Feb 29 02:26:12 PM PST 24
Peak memory 202628 kb
Host smart-3ad648fe-3707-4993-80d9-c542c86d6039
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933427303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s
ram_ctrl_partial_access.933427303
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4035770901
Short name T159
Test name
Test status
Simulation time 8203117239 ps
CPU time 213.28 seconds
Started Feb 29 02:26:10 PM PST 24
Finished Feb 29 02:29:44 PM PST 24
Peak memory 202680 kb
Host smart-8b9b7e47-f73f-4b9c-a906-e7902d1c64d9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035770901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.4035770901
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.517573075
Short name T31
Test name
Test status
Simulation time 83472390 ps
CPU time 1.07 seconds
Started Feb 29 02:26:22 PM PST 24
Finished Feb 29 02:26:23 PM PST 24
Peak memory 202908 kb
Host smart-7de6ae38-2512-4b5c-b8e9-bc41547c629f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517573075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.517573075
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.761066547
Short name T248
Test name
Test status
Simulation time 3419322001 ps
CPU time 1419.05 seconds
Started Feb 29 02:26:22 PM PST 24
Finished Feb 29 02:50:01 PM PST 24
Peak memory 374320 kb
Host smart-ddd14900-57aa-4f49-bfe2-5c81b57b6938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761066547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.761066547
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.3138120854
Short name T830
Test name
Test status
Simulation time 175915651 ps
CPU time 7.15 seconds
Started Feb 29 02:26:14 PM PST 24
Finished Feb 29 02:26:22 PM PST 24
Peak memory 202664 kb
Host smart-2a84e77d-b31c-4268-8b4b-fd9bf2cb6853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138120854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3138120854
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.587176396
Short name T791
Test name
Test status
Simulation time 276196617220 ps
CPU time 7433.89 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 04:30:19 PM PST 24
Peak memory 383748 kb
Host smart-6758c278-669d-4eb6-a8b2-504e67fb9a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587176396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_stress_all.587176396
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2352113707
Short name T427
Test name
Test status
Simulation time 6482008960 ps
CPU time 315.85 seconds
Started Feb 29 02:26:09 PM PST 24
Finished Feb 29 02:31:26 PM PST 24
Peak memory 202764 kb
Host smart-ae5a9727-c096-47bb-a802-c80cf4b8a3d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352113707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.2352113707
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.901315403
Short name T140
Test name
Test status
Simulation time 328916068 ps
CPU time 23.43 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 02:26:48 PM PST 24
Peak memory 267864 kb
Host smart-c834b7d1-7592-4fa6-919e-50e95502e97a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901315403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.901315403
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.626260881
Short name T357
Test name
Test status
Simulation time 10123548786 ps
CPU time 758.81 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:34:03 PM PST 24
Peak memory 374444 kb
Host smart-d8b95693-a81c-4fa1-b084-96134b59c6e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626260881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.sram_ctrl_access_during_key_req.626260881
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.837756067
Short name T341
Test name
Test status
Simulation time 27900899 ps
CPU time 0.67 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:21:26 PM PST 24
Peak memory 201544 kb
Host smart-57cb38e5-15c4-4854-a06e-323396b6aa15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837756067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.837756067
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2143695239
Short name T869
Test name
Test status
Simulation time 9102130169 ps
CPU time 47.86 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:22:10 PM PST 24
Peak memory 202732 kb
Host smart-87f3b50f-261f-49ce-b1ba-ab4b089722f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143695239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2143695239
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.3222376968
Short name T760
Test name
Test status
Simulation time 19309367249 ps
CPU time 855.05 seconds
Started Feb 29 02:21:21 PM PST 24
Finished Feb 29 02:35:37 PM PST 24
Peak memory 373848 kb
Host smart-9342155d-6000-4648-a810-fbc18d803255
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222376968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.3222376968
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.2103923185
Short name T228
Test name
Test status
Simulation time 371611281 ps
CPU time 2.98 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:21:28 PM PST 24
Peak memory 202844 kb
Host smart-889ef5dc-36ac-4f22-8dc6-cc3116d18e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103923185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.2103923185
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.37266388
Short name T727
Test name
Test status
Simulation time 129816318 ps
CPU time 105.25 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:23:11 PM PST 24
Peak memory 337572 kb
Host smart-48157e59-8161-4835-ba3d-3b8923da336e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_max_throughput.37266388
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2709353131
Short name T223
Test name
Test status
Simulation time 124461000 ps
CPU time 5.04 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:21:27 PM PST 24
Peak memory 210912 kb
Host smart-bb2fb187-2e92-4503-bbe2-853a12d90eda
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709353131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.2709353131
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.248989816
Short name T870
Test name
Test status
Simulation time 134970468 ps
CPU time 8.69 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:21:35 PM PST 24
Peak memory 202636 kb
Host smart-138ebb96-04ef-48bf-b26b-27699d87a3a7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248989816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
mem_walk.248989816
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.3407569390
Short name T154
Test name
Test status
Simulation time 5146161741 ps
CPU time 513.06 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:29:55 PM PST 24
Peak memory 374032 kb
Host smart-4b57871d-ecce-489f-b23e-6b9aa62bb28a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407569390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.3407569390
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.3001667836
Short name T257
Test name
Test status
Simulation time 2001053491 ps
CPU time 21.53 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:21:48 PM PST 24
Peak memory 202656 kb
Host smart-7f380491-8800-4242-b1b9-8c2266822367
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001667836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.3001667836
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3783718987
Short name T63
Test name
Test status
Simulation time 62339915191 ps
CPU time 382.01 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:27:47 PM PST 24
Peak memory 202708 kb
Host smart-47c8e050-aa77-433d-a5ce-b0d42ebbc429
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783718987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.3783718987
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.3373901743
Short name T379
Test name
Test status
Simulation time 28066651 ps
CPU time 1.1 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:21:25 PM PST 24
Peak memory 202920 kb
Host smart-961ca8fd-184b-4b07-8828-31989c1995e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373901743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3373901743
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.3816134774
Short name T743
Test name
Test status
Simulation time 21020872259 ps
CPU time 597.3 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:31:22 PM PST 24
Peak memory 372752 kb
Host smart-fa0a2588-b59f-4c7a-ad62-e4ead1cd248d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816134774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3816134774
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3742120380
Short name T15
Test name
Test status
Simulation time 602175976 ps
CPU time 3.24 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:21:28 PM PST 24
Peak memory 220964 kb
Host smart-cefc2637-51bc-4d2c-a7dc-801b2805a69a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742120380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3742120380
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.3350694333
Short name T621
Test name
Test status
Simulation time 432470101 ps
CPU time 105.35 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:23:08 PM PST 24
Peak memory 329644 kb
Host smart-e52910eb-ecd6-44e1-9a62-0c8a1f6aae31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350694333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3350694333
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.3142070184
Short name T420
Test name
Test status
Simulation time 119369598878 ps
CPU time 2136.23 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:57:01 PM PST 24
Peak memory 382136 kb
Host smart-91474d2a-e122-4d03-ac1c-ef5340ece639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142070184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.3142070184
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.373388352
Short name T765
Test name
Test status
Simulation time 1355524517 ps
CPU time 137.36 seconds
Started Feb 29 02:21:21 PM PST 24
Finished Feb 29 02:23:39 PM PST 24
Peak memory 202644 kb
Host smart-d680630c-8741-4a2b-b9b7-2a4e63627f96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373388352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_stress_pipeline.373388352
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1962509825
Short name T675
Test name
Test status
Simulation time 209568819 ps
CPU time 145.39 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:23:48 PM PST 24
Peak memory 362960 kb
Host smart-bd1e0798-4c55-4de9-b6ba-a19efe273925
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962509825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1962509825
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1849627292
Short name T147
Test name
Test status
Simulation time 8419963224 ps
CPU time 536.11 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 02:35:21 PM PST 24
Peak memory 368440 kb
Host smart-15cd8127-9b1c-42a6-8137-a385cdb127bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849627292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1849627292
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2380566503
Short name T441
Test name
Test status
Simulation time 15507854 ps
CPU time 0.71 seconds
Started Feb 29 02:26:34 PM PST 24
Finished Feb 29 02:26:35 PM PST 24
Peak memory 201548 kb
Host smart-9e4bfb8e-0f1f-4f2d-a54c-a91feea50089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380566503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2380566503
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.3525523158
Short name T858
Test name
Test status
Simulation time 3265248148 ps
CPU time 36.28 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 02:27:01 PM PST 24
Peak memory 202748 kb
Host smart-d3e215c8-c16c-4fe9-99d8-d88b9a3f235f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525523158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.3525523158
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.3683014159
Short name T589
Test name
Test status
Simulation time 6235254622 ps
CPU time 491.62 seconds
Started Feb 29 02:26:35 PM PST 24
Finished Feb 29 02:34:47 PM PST 24
Peak memory 374580 kb
Host smart-a24b9446-6a1f-48cd-b44d-77e5b16d5f7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683014159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.3683014159
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.3941751925
Short name T356
Test name
Test status
Simulation time 772816662 ps
CPU time 6.94 seconds
Started Feb 29 02:26:23 PM PST 24
Finished Feb 29 02:26:30 PM PST 24
Peak memory 202756 kb
Host smart-4603c994-ac24-4d9c-9d20-3019e5c6f0d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941751925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.3941751925
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.597989126
Short name T550
Test name
Test status
Simulation time 78198550 ps
CPU time 22 seconds
Started Feb 29 02:26:28 PM PST 24
Finished Feb 29 02:26:50 PM PST 24
Peak memory 272124 kb
Host smart-d764e5a8-d0c4-4a7b-9ed4-16bd69fe75c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597989126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.597989126
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.851047852
Short name T539
Test name
Test status
Simulation time 324612879 ps
CPU time 5.11 seconds
Started Feb 29 02:26:34 PM PST 24
Finished Feb 29 02:26:39 PM PST 24
Peak memory 212016 kb
Host smart-1dd59c42-8885-444f-801c-d3bf7a2ca70f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851047852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_mem_partial_access.851047852
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.1709900425
Short name T778
Test name
Test status
Simulation time 892463907 ps
CPU time 5.54 seconds
Started Feb 29 02:26:35 PM PST 24
Finished Feb 29 02:26:41 PM PST 24
Peak memory 202620 kb
Host smart-4400d219-a187-4b19-ba7c-0f9dbf1d8346
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709900425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.1709900425
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.156995715
Short name T528
Test name
Test status
Simulation time 2616665511 ps
CPU time 847.7 seconds
Started Feb 29 02:26:22 PM PST 24
Finished Feb 29 02:40:30 PM PST 24
Peak memory 373472 kb
Host smart-6d490bc2-4212-4b52-a478-a2cee44f65ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156995715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multip
le_keys.156995715
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.3837372538
Short name T748
Test name
Test status
Simulation time 783609545 ps
CPU time 10.56 seconds
Started Feb 29 02:26:24 PM PST 24
Finished Feb 29 02:26:35 PM PST 24
Peak memory 239624 kb
Host smart-e25bb35d-9e2c-48df-af1c-ec5c3272def7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837372538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.3837372538
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4119921603
Short name T150
Test name
Test status
Simulation time 14081755766 ps
CPU time 348.69 seconds
Started Feb 29 02:26:23 PM PST 24
Finished Feb 29 02:32:12 PM PST 24
Peak memory 202824 kb
Host smart-a2753caf-8744-4f9b-a391-ff95e0ddd37c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119921603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.4119921603
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.2174358903
Short name T746
Test name
Test status
Simulation time 31307797 ps
CPU time 0.8 seconds
Started Feb 29 02:26:33 PM PST 24
Finished Feb 29 02:26:34 PM PST 24
Peak memory 202672 kb
Host smart-4b725a53-122b-4193-b927-1233b29f7d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174358903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2174358903
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3494731111
Short name T12
Test name
Test status
Simulation time 717142887 ps
CPU time 144.46 seconds
Started Feb 29 02:26:35 PM PST 24
Finished Feb 29 02:29:00 PM PST 24
Peak memory 345368 kb
Host smart-bf9294b2-7339-42f0-a8c1-585b706c3a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494731111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3494731111
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.688406313
Short name T39
Test name
Test status
Simulation time 2393775227 ps
CPU time 102.82 seconds
Started Feb 29 02:26:22 PM PST 24
Finished Feb 29 02:28:06 PM PST 24
Peak memory 334540 kb
Host smart-8d2b93b4-6f6d-4106-9d99-e3b6b1f8844e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688406313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.688406313
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.787072057
Short name T345
Test name
Test status
Simulation time 224436081843 ps
CPU time 4678.22 seconds
Started Feb 29 02:26:34 PM PST 24
Finished Feb 29 03:44:33 PM PST 24
Peak memory 374496 kb
Host smart-50e31424-e8c0-42a7-9b02-5f30bbc890f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787072057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_stress_all.787072057
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3094312518
Short name T839
Test name
Test status
Simulation time 10999364766 ps
CPU time 302.14 seconds
Started Feb 29 02:26:23 PM PST 24
Finished Feb 29 02:31:25 PM PST 24
Peak memory 202720 kb
Host smart-62762ec9-0788-483b-bfc4-64e2d2e3e70e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094312518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.3094312518
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2931946057
Short name T553
Test name
Test status
Simulation time 419488370 ps
CPU time 23.56 seconds
Started Feb 29 02:26:23 PM PST 24
Finished Feb 29 02:26:47 PM PST 24
Peak memory 271172 kb
Host smart-77387364-4c0c-478f-bf74-fb70f58d472b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931946057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2931946057
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.4259241791
Short name T482
Test name
Test status
Simulation time 2260007972 ps
CPU time 281.33 seconds
Started Feb 29 02:26:49 PM PST 24
Finished Feb 29 02:31:31 PM PST 24
Peak memory 374432 kb
Host smart-43dc3dd1-627f-4c65-b497-64c8797aae10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259241791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.4259241791
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.2701294697
Short name T725
Test name
Test status
Simulation time 13631197 ps
CPU time 0.65 seconds
Started Feb 29 02:26:48 PM PST 24
Finished Feb 29 02:26:48 PM PST 24
Peak memory 201640 kb
Host smart-ade23709-0ba9-46d9-a37f-d55072ce6441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701294697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.2701294697
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.1917735162
Short name T855
Test name
Test status
Simulation time 953860306 ps
CPU time 59.72 seconds
Started Feb 29 02:26:36 PM PST 24
Finished Feb 29 02:27:36 PM PST 24
Peak memory 202676 kb
Host smart-418eb05a-7738-4f87-a492-81e3f58b2293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917735162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.1917735162
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.3050587378
Short name T406
Test name
Test status
Simulation time 10996251847 ps
CPU time 959.05 seconds
Started Feb 29 02:26:46 PM PST 24
Finished Feb 29 02:42:45 PM PST 24
Peak memory 373444 kb
Host smart-ee96373e-de0a-4a67-b6df-1094e6fa24ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050587378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.3050587378
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.550791183
Short name T605
Test name
Test status
Simulation time 1506801012 ps
CPU time 5.18 seconds
Started Feb 29 02:26:48 PM PST 24
Finished Feb 29 02:26:53 PM PST 24
Peak memory 202660 kb
Host smart-3bd8cc15-0895-4f8b-9c77-c4dacfaeadbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550791183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_esc
alation.550791183
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.3853366853
Short name T833
Test name
Test status
Simulation time 41459840 ps
CPU time 2.11 seconds
Started Feb 29 02:26:47 PM PST 24
Finished Feb 29 02:26:49 PM PST 24
Peak memory 210912 kb
Host smart-4a28b31f-00d1-413c-9b2d-053fbda8b5c4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853366853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.3853366853
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.350809129
Short name T73
Test name
Test status
Simulation time 79146377 ps
CPU time 2.66 seconds
Started Feb 29 02:26:49 PM PST 24
Finished Feb 29 02:26:52 PM PST 24
Peak memory 210876 kb
Host smart-188d8364-bd60-4f24-89d6-b74a4787c0fb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350809129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.sram_ctrl_mem_partial_access.350809129
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.3517251333
Short name T422
Test name
Test status
Simulation time 228082505 ps
CPU time 5.06 seconds
Started Feb 29 02:26:48 PM PST 24
Finished Feb 29 02:26:54 PM PST 24
Peak memory 202660 kb
Host smart-1f38cfd5-eed4-4495-978d-f3b730f86480
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517251333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.3517251333
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.3098286259
Short name T790
Test name
Test status
Simulation time 17866941166 ps
CPU time 1868.52 seconds
Started Feb 29 02:26:34 PM PST 24
Finished Feb 29 02:57:43 PM PST 24
Peak memory 373532 kb
Host smart-f77293fc-6b0a-45ad-a814-fceefdd133ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098286259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.3098286259
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.2733205872
Short name T481
Test name
Test status
Simulation time 408275133 ps
CPU time 59.87 seconds
Started Feb 29 02:26:49 PM PST 24
Finished Feb 29 02:27:49 PM PST 24
Peak memory 301716 kb
Host smart-bd5d1542-f4e4-406f-b99e-1cd3417ea637
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733205872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.2733205872
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1052875123
Short name T88
Test name
Test status
Simulation time 13666709457 ps
CPU time 346.42 seconds
Started Feb 29 02:26:48 PM PST 24
Finished Feb 29 02:32:34 PM PST 24
Peak memory 202752 kb
Host smart-ef1d6743-1172-461e-a9ae-81cd56e528f4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052875123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.1052875123
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.4071582636
Short name T736
Test name
Test status
Simulation time 31893096 ps
CPU time 1.17 seconds
Started Feb 29 02:26:45 PM PST 24
Finished Feb 29 02:26:47 PM PST 24
Peak memory 202964 kb
Host smart-8d6a65b4-9350-4ca6-b9d1-de9cd6822510
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071582636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4071582636
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.2046304959
Short name T107
Test name
Test status
Simulation time 12118124426 ps
CPU time 639.94 seconds
Started Feb 29 02:26:46 PM PST 24
Finished Feb 29 02:37:26 PM PST 24
Peak memory 366492 kb
Host smart-6278564f-775e-4271-9638-e87ea4eac91f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046304959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2046304959
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.73873675
Short name T499
Test name
Test status
Simulation time 457818562 ps
CPU time 6.55 seconds
Started Feb 29 02:26:34 PM PST 24
Finished Feb 29 02:26:40 PM PST 24
Peak memory 202644 kb
Host smart-02b4ea6b-1bd7-418f-8b19-684376e15850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73873675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.73873675
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.2472311354
Short name T342
Test name
Test status
Simulation time 32738341830 ps
CPU time 3426.81 seconds
Started Feb 29 02:26:46 PM PST 24
Finished Feb 29 03:23:53 PM PST 24
Peak memory 375512 kb
Host smart-8e1447ed-8a7c-4823-8616-48fe8a992133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472311354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.2472311354
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.212259154
Short name T583
Test name
Test status
Simulation time 14221308384 ps
CPU time 239.27 seconds
Started Feb 29 02:26:46 PM PST 24
Finished Feb 29 02:30:45 PM PST 24
Peak memory 202740 kb
Host smart-074bb714-9fcd-47c4-b2e4-12875549ea27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212259154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.sram_ctrl_stress_pipeline.212259154
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2295236507
Short name T113
Test name
Test status
Simulation time 1392856635 ps
CPU time 40.77 seconds
Started Feb 29 02:26:46 PM PST 24
Finished Feb 29 02:27:27 PM PST 24
Peak memory 294760 kb
Host smart-4fc4547f-76b8-4446-819e-badf8a7f4515
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295236507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2295236507
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2344101248
Short name T149
Test name
Test status
Simulation time 3321372025 ps
CPU time 994.55 seconds
Started Feb 29 02:27:22 PM PST 24
Finished Feb 29 02:43:57 PM PST 24
Peak memory 371484 kb
Host smart-21376279-7fe1-4160-bb31-a112acede24f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344101248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.2344101248
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.1006117093
Short name T352
Test name
Test status
Simulation time 20004845 ps
CPU time 0.59 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:27:23 PM PST 24
Peak memory 202428 kb
Host smart-05e98efd-b7cc-4afc-81c4-903c1d51ccfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006117093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.1006117093
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1307353025
Short name T851
Test name
Test status
Simulation time 4458723534 ps
CPU time 76.83 seconds
Started Feb 29 02:26:48 PM PST 24
Finished Feb 29 02:28:05 PM PST 24
Peak memory 202660 kb
Host smart-78f8912b-d71b-4dc1-8345-5ad6adf71559
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307353025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1307353025
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.98425200
Short name T183
Test name
Test status
Simulation time 12447558394 ps
CPU time 1198.76 seconds
Started Feb 29 02:27:22 PM PST 24
Finished Feb 29 02:47:21 PM PST 24
Peak memory 374532 kb
Host smart-2df86d03-17f1-4475-9fc9-81a3f1e0bfed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98425200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable
.98425200
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.40058388
Short name T389
Test name
Test status
Simulation time 1246488115 ps
CPU time 9.21 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:27:33 PM PST 24
Peak memory 210828 kb
Host smart-6b16c2dd-2df0-44b4-b367-4277e0b93772
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40058388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esca
lation.40058388
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.4003610516
Short name T371
Test name
Test status
Simulation time 540049286 ps
CPU time 140.63 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:29:44 PM PST 24
Peak memory 367264 kb
Host smart-7f43130c-095c-4d79-95f8-40a5542cb1ab
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003610516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.4003610516
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2878254135
Short name T573
Test name
Test status
Simulation time 154378348 ps
CPU time 2.94 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:27:26 PM PST 24
Peak memory 215592 kb
Host smart-e44ef316-6543-4d49-a1ef-b5c33773852e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878254135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.2878254135
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.1069800811
Short name T802
Test name
Test status
Simulation time 267131085 ps
CPU time 8.6 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:27:32 PM PST 24
Peak memory 202620 kb
Host smart-49e4dc46-03f7-4ba4-8806-f605e49ad17e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069800811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.1069800811
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.4047233188
Short name T160
Test name
Test status
Simulation time 36576888101 ps
CPU time 922.77 seconds
Started Feb 29 02:26:45 PM PST 24
Finished Feb 29 02:42:08 PM PST 24
Peak memory 374608 kb
Host smart-148c0f28-ce60-47c6-ab36-dce24de11659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047233188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.4047233188
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.4218082703
Short name T225
Test name
Test status
Simulation time 2568811432 ps
CPU time 96.94 seconds
Started Feb 29 02:27:22 PM PST 24
Finished Feb 29 02:28:59 PM PST 24
Peak memory 336656 kb
Host smart-4457068f-bf68-46fd-810c-25b2122a1022
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218082703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.4218082703
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.139692719
Short name T669
Test name
Test status
Simulation time 41723940749 ps
CPU time 249.06 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:31:33 PM PST 24
Peak memory 202708 kb
Host smart-ef1b91cb-da08-4910-b16c-2e2090fddd0a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139692719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.sram_ctrl_partial_access_b2b.139692719
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3331886496
Short name T353
Test name
Test status
Simulation time 47675960 ps
CPU time 1.28 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:27:25 PM PST 24
Peak memory 202892 kb
Host smart-1049f458-aed3-4c25-8630-e9b638ea7562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331886496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3331886496
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.1876216346
Short name T615
Test name
Test status
Simulation time 14390999178 ps
CPU time 537.35 seconds
Started Feb 29 02:27:22 PM PST 24
Finished Feb 29 02:36:20 PM PST 24
Peak memory 361048 kb
Host smart-c25f8139-14be-4386-b374-af2211bd4499
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876216346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1876216346
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.3024788915
Short name T376
Test name
Test status
Simulation time 729492938 ps
CPU time 17.22 seconds
Started Feb 29 02:26:47 PM PST 24
Finished Feb 29 02:27:04 PM PST 24
Peak memory 202704 kb
Host smart-80c43ea6-b15c-4098-afe1-2235bb66c805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024788915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3024788915
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.7914986
Short name T735
Test name
Test status
Simulation time 16800505566 ps
CPU time 1501.51 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:52:25 PM PST 24
Peak memory 374692 kb
Host smart-abe3bdba-b41a-49b9-8e89-0240b448cb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7914986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_stress_all.7914986
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3910730567
Short name T526
Test name
Test status
Simulation time 8846172875 ps
CPU time 192.46 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:30:36 PM PST 24
Peak memory 202792 kb
Host smart-d1ea1b77-3562-4533-9548-d48144aa658f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910730567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.3910730567
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.272881339
Short name T308
Test name
Test status
Simulation time 242875304 ps
CPU time 62.03 seconds
Started Feb 29 02:27:23 PM PST 24
Finished Feb 29 02:28:25 PM PST 24
Peak memory 305932 kb
Host smart-2bf1df00-d8e0-4386-b07d-46b2c3239985
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272881339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.272881339
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2943511291
Short name T834
Test name
Test status
Simulation time 3968655572 ps
CPU time 1870.74 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:58:37 PM PST 24
Peak memory 371604 kb
Host smart-a5b892ca-d810-478e-a0fc-893ad6d955fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943511291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2943511291
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.148245090
Short name T813
Test name
Test status
Simulation time 17703135 ps
CPU time 0.65 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:27:25 PM PST 24
Peak memory 201716 kb
Host smart-c363170e-485d-4e94-b8f6-12b8c691148b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148245090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.148245090
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.2993733834
Short name T572
Test name
Test status
Simulation time 7283068426 ps
CPU time 39.9 seconds
Started Feb 29 02:27:22 PM PST 24
Finished Feb 29 02:28:02 PM PST 24
Peak memory 202652 kb
Host smart-52dab92a-087c-48c0-8d25-f35e66789a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993733834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.2993733834
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.308473524
Short name T733
Test name
Test status
Simulation time 16627825612 ps
CPU time 1521.79 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:52:48 PM PST 24
Peak memory 374508 kb
Host smart-f892a1a0-fc3d-4222-9ba1-0c39de4152c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308473524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl
e.308473524
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3022362548
Short name T466
Test name
Test status
Simulation time 562542047 ps
CPU time 6.16 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:27:32 PM PST 24
Peak memory 210916 kb
Host smart-70e396a6-62fc-473f-a7df-e1b0f8bf66d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022362548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3022362548
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.3075971668
Short name T451
Test name
Test status
Simulation time 47445393 ps
CPU time 3.41 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:27:29 PM PST 24
Peak memory 216680 kb
Host smart-2e171cc9-7de6-44ee-be57-1b7b03f3b307
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075971668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.3075971668
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3737773534
Short name T730
Test name
Test status
Simulation time 92299138 ps
CPU time 3.1 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:27:28 PM PST 24
Peak memory 215720 kb
Host smart-a94e8f61-23fa-4526-be76-764edafd0495
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737773534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.3737773534
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.1886268764
Short name T267
Test name
Test status
Simulation time 591690443 ps
CPU time 10.31 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:27:35 PM PST 24
Peak memory 202748 kb
Host smart-cbfa5004-0e83-47e6-943f-fc592836fe1b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886268764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.1886268764
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.3453668312
Short name T436
Test name
Test status
Simulation time 44007091204 ps
CPU time 894.11 seconds
Started Feb 29 02:27:22 PM PST 24
Finished Feb 29 02:42:17 PM PST 24
Peak memory 370348 kb
Host smart-f5055973-7dd3-4ead-98bc-bbae3696bc8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453668312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.3453668312
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.973479568
Short name T625
Test name
Test status
Simulation time 112936325 ps
CPU time 2.43 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:27:27 PM PST 24
Peak memory 202636 kb
Host smart-d89a6d4d-087c-4e0d-a50e-64f1d39cc6eb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973479568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s
ram_ctrl_partial_access.973479568
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3513536057
Short name T515
Test name
Test status
Simulation time 19681750476 ps
CPU time 299.98 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:32:25 PM PST 24
Peak memory 202708 kb
Host smart-06f4bcb5-69df-4ba0-bb07-cb16b7c3d591
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513536057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.3513536057
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.3301350253
Short name T810
Test name
Test status
Simulation time 32999760 ps
CPU time 1.14 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:27:27 PM PST 24
Peak memory 202920 kb
Host smart-cc1fbb7d-47e4-4746-a8fc-bb80aa8a5285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301350253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3301350253
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.4025267630
Short name T109
Test name
Test status
Simulation time 4713269012 ps
CPU time 686.06 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:38:51 PM PST 24
Peak memory 367860 kb
Host smart-f8dea539-b8c7-47a6-8eb5-7887fe2ec5e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025267630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.4025267630
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.4139456169
Short name T304
Test name
Test status
Simulation time 406681814 ps
CPU time 55.74 seconds
Started Feb 29 02:27:22 PM PST 24
Finished Feb 29 02:28:17 PM PST 24
Peak memory 296296 kb
Host smart-1801fce1-62dd-45d4-99f8-412a332fb0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139456169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4139456169
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2771783617
Short name T281
Test name
Test status
Simulation time 6348847173 ps
CPU time 309.36 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:32:34 PM PST 24
Peak memory 202756 kb
Host smart-95f5e755-2a4c-44d6-934f-2977a3a6b738
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771783617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.2771783617
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2807500874
Short name T815
Test name
Test status
Simulation time 541386737 ps
CPU time 119.64 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:29:24 PM PST 24
Peak memory 349216 kb
Host smart-5ad3202f-9df5-42fd-b9cd-1c556465e5de
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807500874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2807500874
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3224185001
Short name T336
Test name
Test status
Simulation time 2621181372 ps
CPU time 259.12 seconds
Started Feb 29 02:27:31 PM PST 24
Finished Feb 29 02:31:52 PM PST 24
Peak memory 357236 kb
Host smart-15a7b0a0-745b-464a-bece-810894bb71a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224185001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.3224185001
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.242363552
Short name T750
Test name
Test status
Simulation time 27332286 ps
CPU time 0.63 seconds
Started Feb 29 02:27:31 PM PST 24
Finished Feb 29 02:27:32 PM PST 24
Peak memory 202444 kb
Host smart-14afa970-544e-442f-9503-053e3eb75953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242363552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.242363552
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.196368390
Short name T270
Test name
Test status
Simulation time 2546093455 ps
CPU time 31.55 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:27:56 PM PST 24
Peak memory 202684 kb
Host smart-4b30a461-cae5-45ee-a076-0473e87949db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196368390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.
196368390
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.2004937025
Short name T585
Test name
Test status
Simulation time 46350280268 ps
CPU time 1983.73 seconds
Started Feb 29 02:27:35 PM PST 24
Finished Feb 29 03:00:40 PM PST 24
Peak memory 374468 kb
Host smart-392a2e0d-9274-4d25-905a-3fe4487683ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004937025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.2004937025
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.2044251511
Short name T806
Test name
Test status
Simulation time 422561199 ps
CPU time 8.94 seconds
Started Feb 29 02:27:31 PM PST 24
Finished Feb 29 02:27:41 PM PST 24
Peak memory 210848 kb
Host smart-638bea63-c7a7-429b-b75a-a5d3c760ce62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044251511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.2044251511
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.1990983480
Short name T233
Test name
Test status
Simulation time 650419697 ps
CPU time 138.22 seconds
Started Feb 29 02:27:31 PM PST 24
Finished Feb 29 02:29:50 PM PST 24
Peak memory 359128 kb
Host smart-61309535-b876-44be-a36c-0766cf48df9f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990983480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.1990983480
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1848938428
Short name T429
Test name
Test status
Simulation time 129104727 ps
CPU time 4.58 seconds
Started Feb 29 02:27:34 PM PST 24
Finished Feb 29 02:27:39 PM PST 24
Peak memory 210936 kb
Host smart-0f169689-4e7c-4e29-a20c-3caf39905da9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848938428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1848938428
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.3653810748
Short name T803
Test name
Test status
Simulation time 457839238 ps
CPU time 9.34 seconds
Started Feb 29 02:27:33 PM PST 24
Finished Feb 29 02:27:43 PM PST 24
Peak memory 202608 kb
Host smart-5b60841f-aa40-44b0-8a0a-96108ac2bb3c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653810748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.3653810748
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.3960196909
Short name T705
Test name
Test status
Simulation time 1551526022 ps
CPU time 194.47 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:30:40 PM PST 24
Peak memory 368376 kb
Host smart-cd61aa35-6aa5-4a28-8b1d-f34d8a5f965a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960196909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.3960196909
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.3240520997
Short name T492
Test name
Test status
Simulation time 1509106839 ps
CPU time 7.85 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:27:32 PM PST 24
Peak memory 202604 kb
Host smart-c626fdbb-5cf4-4ecf-bc1c-814a091e4540
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240520997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.3240520997
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3121188500
Short name T307
Test name
Test status
Simulation time 102786340774 ps
CPU time 550.65 seconds
Started Feb 29 02:27:30 PM PST 24
Finished Feb 29 02:36:41 PM PST 24
Peak memory 202668 kb
Host smart-7aa9eff0-1737-4dfa-a06a-8c7b2b260c96
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121188500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.3121188500
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.4249279908
Short name T726
Test name
Test status
Simulation time 79170285 ps
CPU time 0.81 seconds
Started Feb 29 02:27:33 PM PST 24
Finished Feb 29 02:27:34 PM PST 24
Peak memory 202624 kb
Host smart-4a8640e6-182b-4d91-936b-a1f3f4c893fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249279908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.4249279908
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.252784804
Short name T38
Test name
Test status
Simulation time 77325865597 ps
CPU time 814.42 seconds
Started Feb 29 02:27:33 PM PST 24
Finished Feb 29 02:41:08 PM PST 24
Peak memory 373732 kb
Host smart-0a250cf6-604d-40e3-a91d-ff1c54075839
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252784804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.252784804
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.2260338230
Short name T117
Test name
Test status
Simulation time 3950248672 ps
CPU time 17.33 seconds
Started Feb 29 02:27:25 PM PST 24
Finished Feb 29 02:27:43 PM PST 24
Peak memory 202764 kb
Host smart-80f3a153-7c41-491f-bf85-8ae8fcfc6034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260338230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2260338230
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3279187643
Short name T501
Test name
Test status
Simulation time 10078379973 ps
CPU time 5769.66 seconds
Started Feb 29 02:27:32 PM PST 24
Finished Feb 29 04:03:44 PM PST 24
Peak memory 374432 kb
Host smart-e02f62aa-23ed-46b4-8c10-287cfe10f858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279187643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3279187643
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3322722731
Short name T729
Test name
Test status
Simulation time 1667278654 ps
CPU time 155.77 seconds
Started Feb 29 02:27:24 PM PST 24
Finished Feb 29 02:30:00 PM PST 24
Peak memory 202712 kb
Host smart-e88bb609-f134-4983-b145-f559d8cb6055
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322722731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3322722731
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1195119353
Short name T294
Test name
Test status
Simulation time 251328977 ps
CPU time 96.26 seconds
Started Feb 29 02:27:30 PM PST 24
Finished Feb 29 02:29:07 PM PST 24
Peak memory 334440 kb
Host smart-67c9ccb7-aed0-4efa-8d93-67793c1efdca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195119353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1195119353
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3479924887
Short name T227
Test name
Test status
Simulation time 4087940614 ps
CPU time 1657.08 seconds
Started Feb 29 02:27:41 PM PST 24
Finished Feb 29 02:55:18 PM PST 24
Peak memory 373556 kb
Host smart-6540c1e3-ab56-489b-9b36-c7fccc71bc29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479924887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.3479924887
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.3997190451
Short name T197
Test name
Test status
Simulation time 20674891 ps
CPU time 0.65 seconds
Started Feb 29 02:27:37 PM PST 24
Finished Feb 29 02:27:38 PM PST 24
Peak memory 201500 kb
Host smart-d1938583-0ae5-4bef-84bd-627a124c6da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997190451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.3997190451
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.3093215261
Short name T190
Test name
Test status
Simulation time 15548886957 ps
CPU time 63.37 seconds
Started Feb 29 02:27:36 PM PST 24
Finished Feb 29 02:28:40 PM PST 24
Peak memory 202628 kb
Host smart-07611143-f3c1-45ab-afa0-1ca071fc4133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093215261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.3093215261
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.2359972220
Short name T259
Test name
Test status
Simulation time 27327506556 ps
CPU time 521.4 seconds
Started Feb 29 02:27:35 PM PST 24
Finished Feb 29 02:36:18 PM PST 24
Peak memory 361192 kb
Host smart-88f15274-6b46-44ed-93db-bc21a28bbb86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359972220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.2359972220
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.911707396
Short name T862
Test name
Test status
Simulation time 179835349 ps
CPU time 2.86 seconds
Started Feb 29 02:27:37 PM PST 24
Finished Feb 29 02:27:40 PM PST 24
Peak memory 213100 kb
Host smart-713f185d-6d8a-4f81-8008-760d0cd4756e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911707396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc
alation.911707396
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.546034089
Short name T158
Test name
Test status
Simulation time 242794227 ps
CPU time 106.75 seconds
Started Feb 29 02:27:36 PM PST 24
Finished Feb 29 02:29:23 PM PST 24
Peak memory 354356 kb
Host smart-02a6b03f-6329-4ae6-97fd-96d37845ef87
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546034089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.sram_ctrl_max_throughput.546034089
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3880624551
Short name T741
Test name
Test status
Simulation time 281639752 ps
CPU time 5.08 seconds
Started Feb 29 02:27:35 PM PST 24
Finished Feb 29 02:27:41 PM PST 24
Peak memory 210876 kb
Host smart-610267bd-2bf2-4807-ade9-b2347bf89659
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880624551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3880624551
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.1576959152
Short name T762
Test name
Test status
Simulation time 1407721687 ps
CPU time 6.25 seconds
Started Feb 29 02:27:46 PM PST 24
Finished Feb 29 02:27:53 PM PST 24
Peak memory 202536 kb
Host smart-8d68e22c-ccb5-4ce9-ab72-b5d825da8971
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576959152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.1576959152
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.3250758460
Short name T315
Test name
Test status
Simulation time 1668529635 ps
CPU time 619.51 seconds
Started Feb 29 02:27:31 PM PST 24
Finished Feb 29 02:37:52 PM PST 24
Peak memory 357096 kb
Host smart-2944929d-ab33-489a-b766-16d5b3491040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250758460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.3250758460
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.710417814
Short name T749
Test name
Test status
Simulation time 615604128 ps
CPU time 121.11 seconds
Started Feb 29 02:27:41 PM PST 24
Finished Feb 29 02:29:42 PM PST 24
Peak memory 362660 kb
Host smart-8331f32b-87eb-4101-a80b-723b38e48e8c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710417814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.s
ram_ctrl_partial_access.710417814
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2176758685
Short name T659
Test name
Test status
Simulation time 72317142985 ps
CPU time 487.42 seconds
Started Feb 29 02:27:45 PM PST 24
Finished Feb 29 02:35:54 PM PST 24
Peak memory 202660 kb
Host smart-e9044976-6f23-40cd-a7a6-f151e23b7511
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176758685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.2176758685
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.2902510798
Short name T804
Test name
Test status
Simulation time 27793517 ps
CPU time 0.86 seconds
Started Feb 29 02:27:45 PM PST 24
Finished Feb 29 02:27:46 PM PST 24
Peak memory 202632 kb
Host smart-601c5409-dbb6-4251-a56c-b40a084d9a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902510798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2902510798
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.2401870585
Short name T836
Test name
Test status
Simulation time 11734904806 ps
CPU time 879.98 seconds
Started Feb 29 02:27:45 PM PST 24
Finished Feb 29 02:42:25 PM PST 24
Peak memory 370456 kb
Host smart-eed4d6ca-a9c9-4636-bfaa-61bfb8a4900e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401870585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2401870585
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.2521736124
Short name T538
Test name
Test status
Simulation time 888392297 ps
CPU time 13.26 seconds
Started Feb 29 02:27:32 PM PST 24
Finished Feb 29 02:27:46 PM PST 24
Peak memory 202724 kb
Host smart-139bc9c2-f258-461b-9f1b-a4dfc3e0c328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521736124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2521736124
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.3543086315
Short name T694
Test name
Test status
Simulation time 39551210192 ps
CPU time 3259.65 seconds
Started Feb 29 02:27:41 PM PST 24
Finished Feb 29 03:22:01 PM PST 24
Peak memory 375600 kb
Host smart-84422816-00d3-425a-8d19-7dbd170236a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543086315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.3543086315
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.367328400
Short name T346
Test name
Test status
Simulation time 5102142792 ps
CPU time 255.03 seconds
Started Feb 29 02:27:37 PM PST 24
Finished Feb 29 02:31:52 PM PST 24
Peak memory 202756 kb
Host smart-d44f094f-63e6-4219-a129-030c22215968
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367328400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_stress_pipeline.367328400
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.770804854
Short name T867
Test name
Test status
Simulation time 167407850 ps
CPU time 2.46 seconds
Started Feb 29 02:27:46 PM PST 24
Finished Feb 29 02:27:49 PM PST 24
Peak memory 210816 kb
Host smart-42624b9f-1e2c-41b6-bdc0-db33c2332ee6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770804854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.770804854
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2018252343
Short name T514
Test name
Test status
Simulation time 8176929023 ps
CPU time 840.56 seconds
Started Feb 29 02:27:47 PM PST 24
Finished Feb 29 02:41:49 PM PST 24
Peak memory 371384 kb
Host smart-06aa1f0a-4e25-4b7a-a133-39b017011e47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018252343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2018252343
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.2261996059
Short name T661
Test name
Test status
Simulation time 13970054 ps
CPU time 0.64 seconds
Started Feb 29 02:27:49 PM PST 24
Finished Feb 29 02:27:50 PM PST 24
Peak memory 202432 kb
Host smart-a2f8ef26-7626-4b40-8d47-5411e00162c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261996059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.2261996059
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.3444654810
Short name T773
Test name
Test status
Simulation time 1577147403 ps
CPU time 48.59 seconds
Started Feb 29 02:27:45 PM PST 24
Finished Feb 29 02:28:33 PM PST 24
Peak memory 202688 kb
Host smart-8df03e87-326f-4b2a-b454-11870c85e506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444654810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.3444654810
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.2115060859
Short name T163
Test name
Test status
Simulation time 52428881819 ps
CPU time 1025.59 seconds
Started Feb 29 02:27:47 PM PST 24
Finished Feb 29 02:44:54 PM PST 24
Peak memory 372440 kb
Host smart-1d0de48f-9abf-4120-a445-a399fcb2fbf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115060859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.2115060859
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.3223913912
Short name T181
Test name
Test status
Simulation time 580878423 ps
CPU time 8.93 seconds
Started Feb 29 02:27:50 PM PST 24
Finished Feb 29 02:27:59 PM PST 24
Peak memory 210928 kb
Host smart-cfbfbe76-b541-4b81-8faa-c4dc1e0a1280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223913912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.3223913912
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3244056829
Short name T311
Test name
Test status
Simulation time 68834662 ps
CPU time 12.07 seconds
Started Feb 29 02:27:36 PM PST 24
Finished Feb 29 02:27:49 PM PST 24
Peak memory 251740 kb
Host smart-a9a0b044-7850-497f-9fb6-20885dcb30c1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244056829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3244056829
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.315353646
Short name T754
Test name
Test status
Simulation time 44687604 ps
CPU time 3.06 seconds
Started Feb 29 02:27:47 PM PST 24
Finished Feb 29 02:27:50 PM PST 24
Peak memory 210912 kb
Host smart-2274b4f3-9b16-4792-ad82-554014c49355
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315353646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_mem_partial_access.315353646
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.2930033453
Short name T667
Test name
Test status
Simulation time 342644138 ps
CPU time 5.5 seconds
Started Feb 29 02:27:49 PM PST 24
Finished Feb 29 02:27:55 PM PST 24
Peak memory 202772 kb
Host smart-70afd253-31d4-417f-b59f-e786a2f4c053
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930033453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.2930033453
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.4103367031
Short name T739
Test name
Test status
Simulation time 5400307576 ps
CPU time 565.76 seconds
Started Feb 29 02:27:37 PM PST 24
Finished Feb 29 02:37:03 PM PST 24
Peak memory 331972 kb
Host smart-3ec6020f-aee4-437b-885a-48ce669197c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103367031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.4103367031
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.839961359
Short name T289
Test name
Test status
Simulation time 1464076830 ps
CPU time 28.3 seconds
Started Feb 29 02:27:45 PM PST 24
Finished Feb 29 02:28:13 PM PST 24
Peak memory 273748 kb
Host smart-759b483f-230e-4e20-b37f-60c282149d4a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839961359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s
ram_ctrl_partial_access.839961359
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4001466783
Short name T347
Test name
Test status
Simulation time 17253430605 ps
CPU time 401.29 seconds
Started Feb 29 02:27:40 PM PST 24
Finished Feb 29 02:34:22 PM PST 24
Peak memory 202732 kb
Host smart-31009345-ee89-4f37-a4d7-ea51d05b5fff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001466783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.4001466783
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.4044040957
Short name T616
Test name
Test status
Simulation time 29284389 ps
CPU time 1.1 seconds
Started Feb 29 02:27:48 PM PST 24
Finished Feb 29 02:27:49 PM PST 24
Peak memory 202900 kb
Host smart-080bafce-25ae-4701-9d8c-dc3da34487e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044040957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.4044040957
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.1678161158
Short name T831
Test name
Test status
Simulation time 31608414159 ps
CPU time 884.24 seconds
Started Feb 29 02:27:47 PM PST 24
Finished Feb 29 02:42:32 PM PST 24
Peak memory 372368 kb
Host smart-294072e7-9d2d-4603-b336-cdf9ba084493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678161158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1678161158
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.4166158341
Short name T303
Test name
Test status
Simulation time 1557279924 ps
CPU time 9.09 seconds
Started Feb 29 02:27:40 PM PST 24
Finished Feb 29 02:27:49 PM PST 24
Peak memory 202708 kb
Host smart-2e4621e6-e9e7-414c-b808-0a38363cbe2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166158341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.4166158341
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1451761951
Short name T717
Test name
Test status
Simulation time 10526600086 ps
CPU time 4189.32 seconds
Started Feb 29 02:27:49 PM PST 24
Finished Feb 29 03:37:39 PM PST 24
Peak memory 382680 kb
Host smart-4784114c-3496-4b35-8e78-3fb05145b506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451761951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1451761951
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3107923629
Short name T541
Test name
Test status
Simulation time 1890401132 ps
CPU time 178.06 seconds
Started Feb 29 02:27:45 PM PST 24
Finished Feb 29 02:30:44 PM PST 24
Peak memory 202692 kb
Host smart-ce804ef6-0cb0-4837-9484-e6a6d0694029
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107923629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.3107923629
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2251959263
Short name T485
Test name
Test status
Simulation time 293356859 ps
CPU time 116.57 seconds
Started Feb 29 02:27:49 PM PST 24
Finished Feb 29 02:29:46 PM PST 24
Peak memory 356388 kb
Host smart-902abd07-92bc-4c4f-849a-a269faf6c322
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251959263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2251959263
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1614108833
Short name T123
Test name
Test status
Simulation time 822390581 ps
CPU time 109.77 seconds
Started Feb 29 02:28:15 PM PST 24
Finished Feb 29 02:30:05 PM PST 24
Peak memory 305620 kb
Host smart-3f4b4b8d-ef36-4807-b6a2-eee9fbfdc197
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614108833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.1614108833
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.1203808041
Short name T369
Test name
Test status
Simulation time 18256039 ps
CPU time 0.69 seconds
Started Feb 29 02:28:29 PM PST 24
Finished Feb 29 02:28:30 PM PST 24
Peak memory 201548 kb
Host smart-4ccffa95-330e-4155-afbf-80b8228d1237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203808041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.1203808041
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.772003787
Short name T340
Test name
Test status
Simulation time 5963957067 ps
CPU time 59.7 seconds
Started Feb 29 02:27:59 PM PST 24
Finished Feb 29 02:28:59 PM PST 24
Peak memory 202796 kb
Host smart-14b12ff9-f441-45b0-92ae-3628cbb4c0c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772003787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.
772003787
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.4014378690
Short name T425
Test name
Test status
Simulation time 16531681728 ps
CPU time 1487.59 seconds
Started Feb 29 02:28:12 PM PST 24
Finished Feb 29 02:53:00 PM PST 24
Peak memory 365120 kb
Host smart-d104f331-782f-4989-b57b-b4a1cf0f1bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014378690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.4014378690
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.476335433
Short name T7
Test name
Test status
Simulation time 200994871 ps
CPU time 3.09 seconds
Started Feb 29 02:28:12 PM PST 24
Finished Feb 29 02:28:15 PM PST 24
Peak memory 210920 kb
Host smart-b40d921d-0107-49d2-abfe-a3521806da6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476335433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc
alation.476335433
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3687602911
Short name T864
Test name
Test status
Simulation time 151975107 ps
CPU time 3.1 seconds
Started Feb 29 02:28:13 PM PST 24
Finished Feb 29 02:28:16 PM PST 24
Peak memory 217792 kb
Host smart-75638a6b-98b7-4ab1-8246-abcb759bea9d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687602911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3687602911
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4207749729
Short name T6
Test name
Test status
Simulation time 2083606934 ps
CPU time 5.76 seconds
Started Feb 29 02:28:12 PM PST 24
Finished Feb 29 02:28:18 PM PST 24
Peak memory 216020 kb
Host smart-9a2ae594-219e-4c1d-916d-a4bb284972e6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207749729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.4207749729
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1783555116
Short name T679
Test name
Test status
Simulation time 2316314357 ps
CPU time 10.6 seconds
Started Feb 29 02:28:12 PM PST 24
Finished Feb 29 02:28:23 PM PST 24
Peak memory 202828 kb
Host smart-f3fde33d-eb53-44e6-a4bd-ca1a109ac002
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783555116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1783555116
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.2175027949
Short name T361
Test name
Test status
Simulation time 75391193678 ps
CPU time 1263.37 seconds
Started Feb 29 02:27:58 PM PST 24
Finished Feb 29 02:49:01 PM PST 24
Peak memory 367380 kb
Host smart-03369f93-9ee5-4f92-956f-ed97d995e83d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175027949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.2175027949
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.245225717
Short name T251
Test name
Test status
Simulation time 2587965323 ps
CPU time 91.99 seconds
Started Feb 29 02:27:59 PM PST 24
Finished Feb 29 02:29:31 PM PST 24
Peak memory 318388 kb
Host smart-f449debc-3c54-427a-a7eb-fbb4b57dc169
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245225717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s
ram_ctrl_partial_access.245225717
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.479503660
Short name T80
Test name
Test status
Simulation time 38599814752 ps
CPU time 333.18 seconds
Started Feb 29 02:28:00 PM PST 24
Finished Feb 29 02:33:33 PM PST 24
Peak memory 202748 kb
Host smart-51d577dc-e5e4-4f4c-b2f7-4644e6232ff2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479503660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.sram_ctrl_partial_access_b2b.479503660
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.1195323158
Short name T161
Test name
Test status
Simulation time 73311078 ps
CPU time 0.82 seconds
Started Feb 29 02:28:13 PM PST 24
Finished Feb 29 02:28:14 PM PST 24
Peak memory 202664 kb
Host smart-4ce5d7f2-7a74-403e-a77f-654e9308f350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195323158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1195323158
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3977223938
Short name T517
Test name
Test status
Simulation time 24991189524 ps
CPU time 878.86 seconds
Started Feb 29 02:28:12 PM PST 24
Finished Feb 29 02:42:51 PM PST 24
Peak memory 371412 kb
Host smart-f7af8fb2-d9d3-4200-8319-3312b28898e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977223938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3977223938
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.2900299093
Short name T305
Test name
Test status
Simulation time 407342434 ps
CPU time 13.71 seconds
Started Feb 29 02:27:57 PM PST 24
Finished Feb 29 02:28:11 PM PST 24
Peak memory 202700 kb
Host smart-ef9906a5-7ac3-4030-9dbd-97eeee08e51c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900299093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2900299093
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.651305108
Short name T465
Test name
Test status
Simulation time 43122194085 ps
CPU time 5864.59 seconds
Started Feb 29 02:28:12 PM PST 24
Finished Feb 29 04:05:57 PM PST 24
Peak memory 375056 kb
Host smart-a11d1025-e543-4d47-bb91-8b07af6956b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651305108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_stress_all.651305108
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2787837553
Short name T209
Test name
Test status
Simulation time 12628854504 ps
CPU time 272.43 seconds
Started Feb 29 02:27:58 PM PST 24
Finished Feb 29 02:32:30 PM PST 24
Peak memory 202756 kb
Host smart-a6283827-1a05-4616-8b5c-d5b1bea00708
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787837553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2787837553
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3745458222
Short name T256
Test name
Test status
Simulation time 198319300 ps
CPU time 67.1 seconds
Started Feb 29 02:28:12 PM PST 24
Finished Feb 29 02:29:19 PM PST 24
Peak memory 318104 kb
Host smart-41fbf55e-c42b-4cae-86f0-77195343ff49
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745458222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3745458222
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1820344121
Short name T758
Test name
Test status
Simulation time 5323791078 ps
CPU time 658.64 seconds
Started Feb 29 02:28:27 PM PST 24
Finished Feb 29 02:39:26 PM PST 24
Peak memory 370432 kb
Host smart-9199c7d3-0234-4ad2-b82d-078e96677897
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820344121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.1820344121
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.2417803313
Short name T236
Test name
Test status
Simulation time 48348308 ps
CPU time 0.69 seconds
Started Feb 29 02:28:29 PM PST 24
Finished Feb 29 02:28:30 PM PST 24
Peak memory 201716 kb
Host smart-f62f46e6-6c75-473e-b0f0-bccf20061c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417803313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.2417803313
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.3005517065
Short name T241
Test name
Test status
Simulation time 814990164 ps
CPU time 24.71 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:28:52 PM PST 24
Peak memory 202724 kb
Host smart-71c747c7-4073-43ca-821f-b4c5366991d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005517065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.3005517065
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.322264169
Short name T111
Test name
Test status
Simulation time 3908622743 ps
CPU time 404.8 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:35:13 PM PST 24
Peak memory 339548 kb
Host smart-549f3825-c2f1-46fa-a344-2cdf580ea35d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322264169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl
e.322264169
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.2977435752
Short name T22
Test name
Test status
Simulation time 1094682933 ps
CPU time 16.12 seconds
Started Feb 29 02:28:27 PM PST 24
Finished Feb 29 02:28:43 PM PST 24
Peak memory 210928 kb
Host smart-6d52d4d4-93f9-4795-aa30-e27552dd1419
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977435752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.2977435752
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2474021390
Short name T643
Test name
Test status
Simulation time 93937971 ps
CPU time 42.41 seconds
Started Feb 29 02:28:29 PM PST 24
Finished Feb 29 02:29:12 PM PST 24
Peak memory 292596 kb
Host smart-fe9940ed-af1e-4418-b040-e5649d618fa4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474021390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2474021390
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.891315526
Short name T195
Test name
Test status
Simulation time 306402453 ps
CPU time 5.32 seconds
Started Feb 29 02:28:27 PM PST 24
Finished Feb 29 02:28:33 PM PST 24
Peak memory 210960 kb
Host smart-67ad00d6-3dd1-4117-91f1-5c18e7dcb265
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891315526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_mem_partial_access.891315526
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.728830334
Short name T135
Test name
Test status
Simulation time 594016950 ps
CPU time 4.83 seconds
Started Feb 29 02:28:29 PM PST 24
Finished Feb 29 02:28:34 PM PST 24
Peak memory 202576 kb
Host smart-48ed478f-ca12-46c9-bfac-0d00038b68b0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728830334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl
_mem_walk.728830334
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.927457391
Short name T805
Test name
Test status
Simulation time 11884434226 ps
CPU time 493.97 seconds
Started Feb 29 02:28:27 PM PST 24
Finished Feb 29 02:36:42 PM PST 24
Peak memory 369372 kb
Host smart-ee4ed577-7404-4eff-b1b4-f300c6911dfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927457391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip
le_keys.927457391
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.634799298
Short name T240
Test name
Test status
Simulation time 1163016449 ps
CPU time 166.33 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:31:15 PM PST 24
Peak memory 369276 kb
Host smart-ade7f45e-7c6c-4943-b399-ae394643dd3e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634799298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s
ram_ctrl_partial_access.634799298
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2366471960
Short name T287
Test name
Test status
Simulation time 51876951289 ps
CPU time 334.15 seconds
Started Feb 29 02:28:29 PM PST 24
Finished Feb 29 02:34:03 PM PST 24
Peak memory 202724 kb
Host smart-4cfeb0b3-f880-4a8e-9f5d-30837fe9d5da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366471960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.2366471960
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.4116355811
Short name T456
Test name
Test status
Simulation time 27321177 ps
CPU time 0.85 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:28:29 PM PST 24
Peak memory 202636 kb
Host smart-b15ead52-389a-464b-8777-fa5301b15588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116355811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.4116355811
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.3120598534
Short name T670
Test name
Test status
Simulation time 9499146055 ps
CPU time 1031.31 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:45:39 PM PST 24
Peak memory 367348 kb
Host smart-2a2ab01f-616c-4bb3-895b-72d7de804f9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120598534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3120598534
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.2761656808
Short name T885
Test name
Test status
Simulation time 476241698 ps
CPU time 12.96 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:28:41 PM PST 24
Peak memory 246760 kb
Host smart-e84c1e65-49c0-4603-8fed-85fb25cced31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761656808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2761656808
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.3295283604
Short name T343
Test name
Test status
Simulation time 360909702481 ps
CPU time 7328.57 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 04:30:38 PM PST 24
Peak memory 382348 kb
Host smart-a6f9178c-799b-4d04-bbf1-6fd3681d7015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295283604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.3295283604
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.4287700068
Short name T260
Test name
Test status
Simulation time 5236882439 ps
CPU time 241.69 seconds
Started Feb 29 02:28:27 PM PST 24
Finished Feb 29 02:32:29 PM PST 24
Peak memory 202756 kb
Host smart-26457be4-05ec-4a63-b5ce-d5069c48e9f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287700068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.4287700068
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1073100557
Short name T602
Test name
Test status
Simulation time 89446978 ps
CPU time 22.74 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:28:51 PM PST 24
Peak memory 274780 kb
Host smart-cde5dfea-8920-4d10-8f54-551d7b5d7bb6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073100557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1073100557
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.70177224
Short name T170
Test name
Test status
Simulation time 8235257466 ps
CPU time 353.95 seconds
Started Feb 29 02:28:42 PM PST 24
Finished Feb 29 02:34:36 PM PST 24
Peak memory 312584 kb
Host smart-9607c6e4-42ce-44a8-b3fc-91a2c0baa2bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70177224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.sram_ctrl_access_during_key_req.70177224
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.3302373339
Short name T207
Test name
Test status
Simulation time 61776656 ps
CPU time 0.63 seconds
Started Feb 29 02:28:44 PM PST 24
Finished Feb 29 02:28:45 PM PST 24
Peak memory 201452 kb
Host smart-69258118-a599-4b74-863f-e0f4eb57cd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302373339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.3302373339
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.9748362
Short name T295
Test name
Test status
Simulation time 940745265 ps
CPU time 30.65 seconds
Started Feb 29 02:28:29 PM PST 24
Finished Feb 29 02:28:59 PM PST 24
Peak memory 202700 kb
Host smart-467f200e-54f3-4a6a-b78c-bfb9b20b6955
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9748362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijecti
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.9748362
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.2067507984
Short name T794
Test name
Test status
Simulation time 24792872633 ps
CPU time 1210.39 seconds
Started Feb 29 02:28:40 PM PST 24
Finished Feb 29 02:48:51 PM PST 24
Peak memory 374536 kb
Host smart-8b8229e2-c329-4370-8016-2c208a366869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067507984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.2067507984
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1603514753
Short name T827
Test name
Test status
Simulation time 163285479 ps
CPU time 2.55 seconds
Started Feb 29 02:28:43 PM PST 24
Finished Feb 29 02:28:45 PM PST 24
Peak memory 202660 kb
Host smart-dde4a8b8-7ebf-40fc-8894-c13502add79e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603514753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1603514753
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.2638252895
Short name T116
Test name
Test status
Simulation time 521416108 ps
CPU time 152.99 seconds
Started Feb 29 02:28:43 PM PST 24
Finished Feb 29 02:31:17 PM PST 24
Peak memory 364712 kb
Host smart-f7dafcee-91b5-4339-ad1a-a0852cccf9c7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638252895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.2638252895
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3138847081
Short name T365
Test name
Test status
Simulation time 834109300 ps
CPU time 3.09 seconds
Started Feb 29 02:28:42 PM PST 24
Finished Feb 29 02:28:45 PM PST 24
Peak memory 210828 kb
Host smart-0db84344-a77f-429e-a5c8-ca45fd195bf8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138847081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.3138847081
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.666325305
Short name T633
Test name
Test status
Simulation time 957406608 ps
CPU time 9.44 seconds
Started Feb 29 02:28:42 PM PST 24
Finished Feb 29 02:28:51 PM PST 24
Peak memory 202636 kb
Host smart-cec78aa3-2b7d-47b2-9089-8a04b0258c40
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666325305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl
_mem_walk.666325305
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.1752213166
Short name T126
Test name
Test status
Simulation time 29010036614 ps
CPU time 1216.77 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:48:45 PM PST 24
Peak memory 374536 kb
Host smart-50a4fb12-b485-4b79-a5ba-890ea2ee0440
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752213166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.1752213166
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.327252790
Short name T586
Test name
Test status
Simulation time 151561755 ps
CPU time 3.37 seconds
Started Feb 29 02:28:43 PM PST 24
Finished Feb 29 02:28:47 PM PST 24
Peak memory 202780 kb
Host smart-597bc4ea-6f53-46f5-87e0-ad297617a4d4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327252790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s
ram_ctrl_partial_access.327252790
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.293179443
Short name T400
Test name
Test status
Simulation time 14491943425 ps
CPU time 308.17 seconds
Started Feb 29 02:28:41 PM PST 24
Finished Feb 29 02:33:50 PM PST 24
Peak memory 202696 kb
Host smart-7a91744e-89d8-4d3b-a822-826eb3cec5f7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293179443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.sram_ctrl_partial_access_b2b.293179443
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.744513956
Short name T696
Test name
Test status
Simulation time 28661298 ps
CPU time 1.06 seconds
Started Feb 29 02:28:44 PM PST 24
Finished Feb 29 02:28:45 PM PST 24
Peak memory 202852 kb
Host smart-93ad8b5a-578f-4ad0-adad-141c08bdc836
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744513956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.744513956
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.90404208
Short name T108
Test name
Test status
Simulation time 11915607501 ps
CPU time 896.96 seconds
Started Feb 29 02:28:42 PM PST 24
Finished Feb 29 02:43:39 PM PST 24
Peak memory 374504 kb
Host smart-76d76f46-90b4-443f-a5be-06f62a27b4a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90404208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.90404208
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.1945175749
Short name T690
Test name
Test status
Simulation time 2496070926 ps
CPU time 172.51 seconds
Started Feb 29 02:28:28 PM PST 24
Finished Feb 29 02:31:20 PM PST 24
Peak memory 373272 kb
Host smart-2286b295-0a4e-4ef8-87c5-763a0619904c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945175749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1945175749
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.451494864
Short name T79
Test name
Test status
Simulation time 1853340386 ps
CPU time 171.69 seconds
Started Feb 29 02:28:29 PM PST 24
Finished Feb 29 02:31:21 PM PST 24
Peak memory 202676 kb
Host smart-01248001-3404-4e95-b42e-8d2e14a36d75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451494864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.451494864
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.721707713
Short name T842
Test name
Test status
Simulation time 399761482 ps
CPU time 23.53 seconds
Started Feb 29 02:28:41 PM PST 24
Finished Feb 29 02:29:05 PM PST 24
Peak memory 269108 kb
Host smart-f548ed8a-feb0-42ac-a0f2-dbb9e5bca41b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721707713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_throughput_w_partial_write.721707713
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1303341633
Short name T620
Test name
Test status
Simulation time 57115688242 ps
CPU time 1061.55 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:39:04 PM PST 24
Peak memory 373136 kb
Host smart-145ee1ba-136a-4aab-9dde-191d58e3bd3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303341633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1303341633
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.4200426239
Short name T418
Test name
Test status
Simulation time 34329798 ps
CPU time 0.65 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:21:24 PM PST 24
Peak memory 201680 kb
Host smart-d396a67f-493b-43e6-83fb-e4604a07d0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200426239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.4200426239
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.249963477
Short name T121
Test name
Test status
Simulation time 2036778785 ps
CPU time 47.99 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:22:12 PM PST 24
Peak memory 202680 kb
Host smart-6153b2ed-c44c-4630-8a30-344bfe3a9b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249963477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.249963477
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.2558939050
Short name T354
Test name
Test status
Simulation time 2442055043 ps
CPU time 129.07 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:23:35 PM PST 24
Peak memory 332576 kb
Host smart-e5935e9b-8275-4320-81d2-61e4154a3b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558939050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.2558939050
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.4073171125
Short name T446
Test name
Test status
Simulation time 516209226 ps
CPU time 57.93 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:22:23 PM PST 24
Peak memory 304244 kb
Host smart-f925ea31-02bc-4351-9cc6-970d5371159a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073171125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.4073171125
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2385577644
Short name T76
Test name
Test status
Simulation time 377743816 ps
CPU time 3.16 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:21:28 PM PST 24
Peak memory 219096 kb
Host smart-80453435-ec8b-4d10-be8e-43fa75919296
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385577644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2385577644
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.1089414024
Short name T392
Test name
Test status
Simulation time 1762715491 ps
CPU time 9.54 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:21:32 PM PST 24
Peak memory 202624 kb
Host smart-ae4b3057-f21a-4b2c-ac30-b9dfe7311533
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089414024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.1089414024
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1993491745
Short name T873
Test name
Test status
Simulation time 2309972780 ps
CPU time 954.15 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:37:18 PM PST 24
Peak memory 368332 kb
Host smart-b74f3c19-45d9-49e4-bcc1-4e067e7d9eff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993491745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1993491745
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.3111115604
Short name T535
Test name
Test status
Simulation time 988435501 ps
CPU time 17.13 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:21:42 PM PST 24
Peak memory 254064 kb
Host smart-4e38f0e4-1146-4c82-a840-a66fba05d23d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111115604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.3111115604
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3034487893
Short name T546
Test name
Test status
Simulation time 18079034818 ps
CPU time 466.65 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:29:11 PM PST 24
Peak memory 202732 kb
Host smart-e0dec176-8bd2-4797-84e0-5ff4cadbccfb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034487893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.3034487893
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1369743754
Short name T261
Test name
Test status
Simulation time 187308505 ps
CPU time 1.14 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:21:26 PM PST 24
Peak memory 202944 kb
Host smart-f557f6bd-6232-465a-bd58-df8a4c513f47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369743754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1369743754
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.3639009556
Short name T210
Test name
Test status
Simulation time 11094544399 ps
CPU time 1418.29 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:45:04 PM PST 24
Peak memory 370500 kb
Host smart-a74bc75d-b4a2-4978-b5b2-684678f5dcf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639009556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3639009556
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.4059847811
Short name T291
Test name
Test status
Simulation time 200485113 ps
CPU time 26.48 seconds
Started Feb 29 02:21:23 PM PST 24
Finished Feb 29 02:21:51 PM PST 24
Peak memory 285404 kb
Host smart-f474a6b8-701b-4878-bfeb-f69bfd2873e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059847811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4059847811
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.162770450
Short name T244
Test name
Test status
Simulation time 117162717709 ps
CPU time 3525.64 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 03:20:13 PM PST 24
Peak memory 372508 kb
Host smart-7c757724-5362-43ea-9f4f-d94d27e4c4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162770450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_stress_all.162770450
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.141541494
Short name T455
Test name
Test status
Simulation time 8001099355 ps
CPU time 193.43 seconds
Started Feb 29 02:21:21 PM PST 24
Finished Feb 29 02:24:35 PM PST 24
Peak memory 202752 kb
Host smart-d66e3540-861f-4cf0-a601-8cb5e2db34f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141541494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
sram_ctrl_stress_pipeline.141541494
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3056555726
Short name T576
Test name
Test status
Simulation time 281293564 ps
CPU time 20.36 seconds
Started Feb 29 02:21:22 PM PST 24
Finished Feb 29 02:21:43 PM PST 24
Peak memory 275864 kb
Host smart-6415609a-a74c-4ffc-b949-e0fe8eb5cb1f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056555726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3056555726
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1059612971
Short name T203
Test name
Test status
Simulation time 10476750194 ps
CPU time 1825.07 seconds
Started Feb 29 02:21:29 PM PST 24
Finished Feb 29 02:51:55 PM PST 24
Peak memory 374460 kb
Host smart-c3d23bc5-4e35-41cc-aecd-7e785d99dd5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059612971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.1059612971
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.2249519096
Short name T800
Test name
Test status
Simulation time 32408557 ps
CPU time 0.65 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:21:27 PM PST 24
Peak memory 201688 kb
Host smart-e25a29ac-0aab-4589-b0b2-81a26488b44b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249519096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.2249519096
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.1211960407
Short name T511
Test name
Test status
Simulation time 1604351101 ps
CPU time 35.54 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:22:00 PM PST 24
Peak memory 202676 kb
Host smart-b4bf05c1-442c-44b6-9902-8cd4f50f4ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211960407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
1211960407
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.2861232399
Short name T686
Test name
Test status
Simulation time 53872532985 ps
CPU time 628.57 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:31:55 PM PST 24
Peak memory 368344 kb
Host smart-ac008bbf-349e-4b74-a6f9-f830145af288
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861232399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.2861232399
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.253084892
Short name T504
Test name
Test status
Simulation time 446324973 ps
CPU time 6.19 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:21:32 PM PST 24
Peak memory 202764 kb
Host smart-6f178ecc-1444-4743-abb1-06bd790b9c53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253084892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca
lation.253084892
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.69386053
Short name T627
Test name
Test status
Simulation time 122455796 ps
CPU time 118.22 seconds
Started Feb 29 02:21:28 PM PST 24
Finished Feb 29 02:23:26 PM PST 24
Peak memory 335640 kb
Host smart-fc4873b1-44f5-4c6f-8fd0-bacdfff806e2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69386053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_max_throughput.69386053
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2126949232
Short name T222
Test name
Test status
Simulation time 73475658 ps
CPU time 4.67 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:21:31 PM PST 24
Peak memory 212348 kb
Host smart-0fcf76c0-ef1c-41ba-a476-a8c755c5788d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126949232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.2126949232
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.2732241068
Short name T738
Test name
Test status
Simulation time 1140216143 ps
CPU time 5.67 seconds
Started Feb 29 02:21:31 PM PST 24
Finished Feb 29 02:21:37 PM PST 24
Peak memory 202604 kb
Host smart-ca4350cd-325c-4510-8628-89edbee53282
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732241068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.2732241068
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.384388277
Short name T644
Test name
Test status
Simulation time 3068079630 ps
CPU time 1158.1 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:40:45 PM PST 24
Peak memory 373464 kb
Host smart-f2108397-7df0-4124-9031-53655bacaddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384388277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl
e_keys.384388277
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.2989750517
Short name T763
Test name
Test status
Simulation time 7956920496 ps
CPU time 16.58 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:21:42 PM PST 24
Peak memory 202764 kb
Host smart-e9db0400-4403-4750-bc82-ba93012d9b38
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989750517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.2989750517
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1745693458
Short name T237
Test name
Test status
Simulation time 360619822958 ps
CPU time 691.78 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:32:57 PM PST 24
Peak memory 202664 kb
Host smart-a4416107-1433-498c-86c2-64b2b41d1e2e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745693458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.1745693458
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.3858610078
Short name T339
Test name
Test status
Simulation time 51818526 ps
CPU time 0.84 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:21:27 PM PST 24
Peak memory 202672 kb
Host smart-8b270e50-57da-4b0c-a344-2d24a470a1a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858610078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3858610078
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3813152926
Short name T402
Test name
Test status
Simulation time 2741928201 ps
CPU time 796.29 seconds
Started Feb 29 02:21:27 PM PST 24
Finished Feb 29 02:34:44 PM PST 24
Peak memory 367304 kb
Host smart-b7aaaa0d-a175-4aa8-8610-eb4c458ef7d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813152926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3813152926
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.1257704292
Short name T134
Test name
Test status
Simulation time 25294490 ps
CPU time 1.33 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:21:26 PM PST 24
Peak memory 202720 kb
Host smart-ee696dc9-1dd3-4500-aedf-8ce66914eb08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257704292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1257704292
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.2335667774
Short name T264
Test name
Test status
Simulation time 86234851947 ps
CPU time 2625.11 seconds
Started Feb 29 02:21:28 PM PST 24
Finished Feb 29 03:05:13 PM PST 24
Peak memory 375556 kb
Host smart-498fb707-19f0-4d30-a793-e1c0961adf72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335667774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.2335667774
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1010897515
Short name T217
Test name
Test status
Simulation time 14904886159 ps
CPU time 365 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:27:31 PM PST 24
Peak memory 202728 kb
Host smart-cbd55762-ef68-4bc3-b1c3-bb3f1da39301
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010897515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.1010897515
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2017267898
Short name T81
Test name
Test status
Simulation time 97027938 ps
CPU time 33.81 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:22:00 PM PST 24
Peak memory 278396 kb
Host smart-dd65579d-20ef-4788-b9d6-86e245823459
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017267898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2017267898
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2519829619
Short name T840
Test name
Test status
Simulation time 2960599705 ps
CPU time 1194.48 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:41:28 PM PST 24
Peak memory 372540 kb
Host smart-9b5d43f6-245e-461f-8a3c-d12509961209
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519829619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.2519829619
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.139806082
Short name T20
Test name
Test status
Simulation time 14089904 ps
CPU time 0.65 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:21:34 PM PST 24
Peak memory 202472 kb
Host smart-0b032601-cd85-47a1-bc58-3c7423c8454b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139806082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.139806082
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.25703363
Short name T721
Test name
Test status
Simulation time 1129602908 ps
CPU time 34.11 seconds
Started Feb 29 02:21:29 PM PST 24
Finished Feb 29 02:22:04 PM PST 24
Peak memory 202704 kb
Host smart-8794e3e8-ea7f-4a81-9b89-f036a0e33728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25703363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.25703363
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.3145768799
Short name T439
Test name
Test status
Simulation time 9725137708 ps
CPU time 1187.12 seconds
Started Feb 29 02:21:28 PM PST 24
Finished Feb 29 02:41:15 PM PST 24
Peak memory 369292 kb
Host smart-c51d552c-71ac-4720-86f7-7d3ec3b86f22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145768799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.3145768799
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.99925825
Short name T153
Test name
Test status
Simulation time 290036553 ps
CPU time 8.05 seconds
Started Feb 29 02:21:32 PM PST 24
Finished Feb 29 02:21:41 PM PST 24
Peak memory 210948 kb
Host smart-c0adfa19-0680-4c8c-b09b-f18064c25854
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99925825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escal
ation.99925825
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.1956641546
Short name T157
Test name
Test status
Simulation time 118565892 ps
CPU time 74.35 seconds
Started Feb 29 02:21:29 PM PST 24
Finished Feb 29 02:22:44 PM PST 24
Peak memory 328444 kb
Host smart-6198e579-3472-4817-9055-0ea650d71a30
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956641546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.1956641546
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3989631593
Short name T171
Test name
Test status
Simulation time 170653259 ps
CPU time 3.1 seconds
Started Feb 29 02:21:32 PM PST 24
Finished Feb 29 02:21:36 PM PST 24
Peak memory 218996 kb
Host smart-e7edd594-ad70-4ab4-b438-4d7e0e3afe87
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989631593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.3989631593
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.1378668352
Short name T776
Test name
Test status
Simulation time 148979798 ps
CPU time 8.22 seconds
Started Feb 29 02:21:32 PM PST 24
Finished Feb 29 02:21:41 PM PST 24
Peak memory 202632 kb
Host smart-1faec750-5448-40d6-a0d7-2cbe73232e36
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378668352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.1378668352
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.794915720
Short name T852
Test name
Test status
Simulation time 9250302324 ps
CPU time 38.07 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:22:12 PM PST 24
Peak memory 212936 kb
Host smart-3d423033-9af3-4223-aef3-f4cc242983c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794915720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl
e_keys.794915720
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1307305721
Short name T131
Test name
Test status
Simulation time 884654020 ps
CPU time 17.66 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:21:51 PM PST 24
Peak memory 202628 kb
Host smart-a9aea314-e747-4de8-a02e-ca3616fe3558
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307305721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1307305721
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3937366207
Short name T611
Test name
Test status
Simulation time 16745312646 ps
CPU time 217.05 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:25:11 PM PST 24
Peak memory 202772 kb
Host smart-3d1b14f4-2535-402c-8a70-fcb5ff9024ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937366207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.3937366207
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3856362315
Short name T359
Test name
Test status
Simulation time 28812991 ps
CPU time 0.83 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:21:34 PM PST 24
Peak memory 202728 kb
Host smart-8cf52593-ba96-4fc8-92a3-a4588ffad662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856362315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3856362315
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.407435494
Short name T24
Test name
Test status
Simulation time 14363624737 ps
CPU time 1019.92 seconds
Started Feb 29 02:21:31 PM PST 24
Finished Feb 29 02:38:31 PM PST 24
Peak memory 372888 kb
Host smart-ffd23b11-dc93-4816-9b5a-b8f3808f4b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407435494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.407435494
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.1408974473
Short name T723
Test name
Test status
Simulation time 9279751373 ps
CPU time 73.22 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:22:39 PM PST 24
Peak memory 312148 kb
Host smart-e4ecd150-5235-4eaa-b68c-76f43770c692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408974473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1408974473
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.302878519
Short name T314
Test name
Test status
Simulation time 15262773866 ps
CPU time 5526.32 seconds
Started Feb 29 02:21:31 PM PST 24
Finished Feb 29 03:53:39 PM PST 24
Peak memory 375400 kb
Host smart-a4a2007d-0e20-464c-a8e3-ef55477d5d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302878519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_stress_all.302878519
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4028031430
Short name T826
Test name
Test status
Simulation time 7313758226 ps
CPU time 170.4 seconds
Started Feb 29 02:21:30 PM PST 24
Finished Feb 29 02:24:21 PM PST 24
Peak memory 202764 kb
Host smart-c2782601-3901-4e24-b5b0-43f805cc09cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028031430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.4028031430
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2012366165
Short name T613
Test name
Test status
Simulation time 117503106 ps
CPU time 54.47 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:22:28 PM PST 24
Peak memory 305772 kb
Host smart-b7ac84d1-c316-4306-803d-6deabd82ce00
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012366165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2012366165
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1641321752
Short name T547
Test name
Test status
Simulation time 29989060537 ps
CPU time 1229.17 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:41:54 PM PST 24
Peak memory 374240 kb
Host smart-a6835267-8d3b-44b3-9578-47b0433df44b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641321752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.1641321752
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.958103180
Short name T19
Test name
Test status
Simulation time 14631488 ps
CPU time 0.67 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:21:27 PM PST 24
Peak memory 201512 kb
Host smart-a1599ab7-1187-4ee8-b7c5-b12687d6f0ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958103180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.958103180
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.546979621
Short name T151
Test name
Test status
Simulation time 2718656882 ps
CPU time 55.87 seconds
Started Feb 29 02:21:31 PM PST 24
Finished Feb 29 02:22:27 PM PST 24
Peak memory 202740 kb
Host smart-936a07ed-c37b-4328-8751-7a2bd6818ee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546979621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.546979621
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.605796224
Short name T332
Test name
Test status
Simulation time 6623117377 ps
CPU time 1391.75 seconds
Started Feb 29 02:21:27 PM PST 24
Finished Feb 29 02:44:39 PM PST 24
Peak memory 369532 kb
Host smart-cdbafbb6-32f1-4f45-bd68-5dec685d3cca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605796224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable
.605796224
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.318852279
Short name T651
Test name
Test status
Simulation time 7857991731 ps
CPU time 7.15 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:21:40 PM PST 24
Peak memory 213812 kb
Host smart-9d1f74a8-d408-4c88-bf50-c31c37a08660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318852279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca
lation.318852279
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.1686292121
Short name T129
Test name
Test status
Simulation time 335146724 ps
CPU time 42.11 seconds
Started Feb 29 02:21:33 PM PST 24
Finished Feb 29 02:22:16 PM PST 24
Peak memory 287168 kb
Host smart-da4e13a2-d286-4253-9642-7c7e38e10de6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686292121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.1686292121
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2664714992
Short name T453
Test name
Test status
Simulation time 68886280 ps
CPU time 5.13 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:21:29 PM PST 24
Peak memory 212272 kb
Host smart-f06257bb-d1d2-49d2-b4ff-2a75155adb2e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664714992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.2664714992
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.953650472
Short name T212
Test name
Test status
Simulation time 655612976 ps
CPU time 10.18 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:21:37 PM PST 24
Peak memory 202616 kb
Host smart-a01e0eeb-3dec-40e5-95f8-f6a58e73708d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953650472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
mem_walk.953650472
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.4105734889
Short name T445
Test name
Test status
Simulation time 4171750580 ps
CPU time 330.8 seconds
Started Feb 29 02:21:31 PM PST 24
Finished Feb 29 02:27:02 PM PST 24
Peak memory 314152 kb
Host smart-7561b5c6-5d9e-422c-9abb-08d48f71685d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105734889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.4105734889
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.3227873442
Short name T672
Test name
Test status
Simulation time 639814058 ps
CPU time 4.56 seconds
Started Feb 29 02:21:34 PM PST 24
Finished Feb 29 02:21:38 PM PST 24
Peak memory 202704 kb
Host smart-3de5b6de-5993-43d6-89ea-5d437834d8e6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227873442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.3227873442
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3901887185
Short name T300
Test name
Test status
Simulation time 38028536685 ps
CPU time 461.92 seconds
Started Feb 29 02:21:34 PM PST 24
Finished Feb 29 02:29:16 PM PST 24
Peak memory 202752 kb
Host smart-6b3fce29-f882-4c88-a561-4f537259dd64
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901887185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.3901887185
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.3528764158
Short name T647
Test name
Test status
Simulation time 28259520 ps
CPU time 0.87 seconds
Started Feb 29 02:21:24 PM PST 24
Finished Feb 29 02:21:26 PM PST 24
Peak memory 202660 kb
Host smart-df711e59-2321-4a95-951a-0e2071f4c7ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528764158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3528764158
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3150043365
Short name T845
Test name
Test status
Simulation time 4241994960 ps
CPU time 423.11 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:28:30 PM PST 24
Peak memory 364884 kb
Host smart-ba6243ae-5fd6-4c52-bd2b-5f51d38a4068
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150043365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3150043365
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.1724131793
Short name T40
Test name
Test status
Simulation time 957905002 ps
CPU time 13.06 seconds
Started Feb 29 02:21:32 PM PST 24
Finished Feb 29 02:21:46 PM PST 24
Peak memory 245560 kb
Host smart-96828c88-23d5-4771-a20d-1c2ddf53a997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724131793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1724131793
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.342850628
Short name T880
Test name
Test status
Simulation time 135874457311 ps
CPU time 2255.06 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:59:02 PM PST 24
Peak memory 375548 kb
Host smart-210fb03a-c54f-4738-bc3a-c3b7bec411fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342850628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_stress_all.342850628
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2142197202
Short name T461
Test name
Test status
Simulation time 10229762922 ps
CPU time 167.05 seconds
Started Feb 29 02:21:32 PM PST 24
Finished Feb 29 02:24:20 PM PST 24
Peak memory 202792 kb
Host smart-0a9f7656-4a99-4ff0-927a-dd5f37d57338
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142197202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2142197202
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1891545093
Short name T496
Test name
Test status
Simulation time 320025300 ps
CPU time 119.54 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:23:25 PM PST 24
Peak memory 365344 kb
Host smart-c0468b6a-4671-46f5-bff8-b982d7f5cfc5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891545093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1891545093
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1052075118
Short name T396
Test name
Test status
Simulation time 12622239551 ps
CPU time 1397.23 seconds
Started Feb 29 02:21:36 PM PST 24
Finished Feb 29 02:44:54 PM PST 24
Peak memory 372472 kb
Host smart-4777c2b2-8e69-4d06-b9a0-ab0ef984e72f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052075118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.1052075118
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.478321989
Short name T600
Test name
Test status
Simulation time 43019439 ps
CPU time 0.65 seconds
Started Feb 29 02:21:37 PM PST 24
Finished Feb 29 02:21:38 PM PST 24
Peak memory 202472 kb
Host smart-644d6ed1-c90a-40e2-af60-ad28ffd8c6d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478321989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.478321989
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.970796100
Short name T327
Test name
Test status
Simulation time 24117167412 ps
CPU time 70.51 seconds
Started Feb 29 02:21:27 PM PST 24
Finished Feb 29 02:22:38 PM PST 24
Peak memory 202896 kb
Host smart-e5998659-f2b4-46fe-becf-f61e98d173bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970796100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.970796100
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.3265608091
Short name T132
Test name
Test status
Simulation time 30711643423 ps
CPU time 509.38 seconds
Started Feb 29 02:21:44 PM PST 24
Finished Feb 29 02:30:13 PM PST 24
Peak memory 367068 kb
Host smart-9385170e-0ecf-432c-ae9c-20c337e0f05f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265608091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.3265608091
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.825012425
Short name T883
Test name
Test status
Simulation time 1358473568 ps
CPU time 8.65 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:21:35 PM PST 24
Peak memory 210888 kb
Host smart-bd85d1ba-8e8e-43a9-aacc-92a53ed3573d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825012425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca
lation.825012425
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2600005437
Short name T411
Test name
Test status
Simulation time 263995447 ps
CPU time 140.24 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:23:47 PM PST 24
Peak memory 357024 kb
Host smart-08c3db92-bc80-44ac-923b-720f6c0571bb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600005437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2600005437
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.91518358
Short name T198
Test name
Test status
Simulation time 66010304 ps
CPU time 4.69 seconds
Started Feb 29 02:21:34 PM PST 24
Finished Feb 29 02:21:39 PM PST 24
Peak memory 211144 kb
Host smart-f82bf7b3-58cd-4509-8f21-03df040871c2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91518358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_mem_partial_access.91518358
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.3902022978
Short name T464
Test name
Test status
Simulation time 700105757 ps
CPU time 10.29 seconds
Started Feb 29 02:21:44 PM PST 24
Finished Feb 29 02:21:54 PM PST 24
Peak memory 202460 kb
Host smart-096eeae1-9a82-4b16-8f53-d11aafb12158
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902022978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.3902022978
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.1089534414
Short name T187
Test name
Test status
Simulation time 51528891673 ps
CPU time 1018.86 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:38:25 PM PST 24
Peak memory 372468 kb
Host smart-cc7ecc3e-7e15-45df-92f0-b40b22ea5d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089534414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.1089534414
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.385541090
Short name T362
Test name
Test status
Simulation time 1281390639 ps
CPU time 2.84 seconds
Started Feb 29 02:21:25 PM PST 24
Finished Feb 29 02:21:29 PM PST 24
Peak memory 202648 kb
Host smart-1f2990bc-94e3-41cc-83a3-faac072e485f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385541090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr
am_ctrl_partial_access.385541090
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2130459684
Short name T215
Test name
Test status
Simulation time 32091931932 ps
CPU time 444.97 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:28:52 PM PST 24
Peak memory 202740 kb
Host smart-decfec57-8c3a-449a-bd50-bcf3138e9554
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130459684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2130459684
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.4125255305
Short name T631
Test name
Test status
Simulation time 183320355 ps
CPU time 0.92 seconds
Started Feb 29 02:21:42 PM PST 24
Finished Feb 29 02:21:44 PM PST 24
Peak memory 202576 kb
Host smart-2a2ed7e0-acbf-4e33-a58c-a17a46f5fd1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125255305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.4125255305
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.136045682
Short name T560
Test name
Test status
Simulation time 2808400815 ps
CPU time 906.67 seconds
Started Feb 29 02:21:39 PM PST 24
Finished Feb 29 02:36:46 PM PST 24
Peak memory 374148 kb
Host smart-488353d1-7ee2-4a5e-8150-df0e4e25f92d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136045682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.136045682
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.4273213811
Short name T443
Test name
Test status
Simulation time 1596503566 ps
CPU time 17.81 seconds
Started Feb 29 02:21:30 PM PST 24
Finished Feb 29 02:21:48 PM PST 24
Peak memory 202556 kb
Host smart-06a1aac5-20ad-47c8-b5a8-0fddb0d9b6f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273213811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.4273213811
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.3873368245
Short name T587
Test name
Test status
Simulation time 101783742412 ps
CPU time 3942.08 seconds
Started Feb 29 02:21:35 PM PST 24
Finished Feb 29 03:27:17 PM PST 24
Peak memory 376332 kb
Host smart-3f408771-91f6-4bae-abe4-16ab5694f5c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873368245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.3873368245
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.408090874
Short name T468
Test name
Test status
Simulation time 11083630798 ps
CPU time 245.95 seconds
Started Feb 29 02:21:30 PM PST 24
Finished Feb 29 02:25:36 PM PST 24
Peak memory 202728 kb
Host smart-52525586-3b80-403c-8058-0eb133fe250d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408090874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_stress_pipeline.408090874
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2370239780
Short name T188
Test name
Test status
Simulation time 118133534 ps
CPU time 52.31 seconds
Started Feb 29 02:21:26 PM PST 24
Finished Feb 29 02:22:19 PM PST 24
Peak memory 322208 kb
Host smart-783425c0-62a3-487b-8c50-4ce99d08edfb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370239780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2370239780
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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