Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	141843680	1			T1	792782		T2	571672		T3	739960
instr_valid_dis	111587665	1			T1	754040		T2	257720		T3	393970
instr_en	22827265	1			T1	17262		T2	206630		T3	227374

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10207352	1			T1	128216		T2	94814		T3	116626
sram_ifetch_valid_disable	109777842	1			T1	438816		T2	265814		T3	126134
sram_ifetch_enable	21858486	1			T1	225750		T2	211044		T3	497200

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	141843680	1			T1	792782		T2	571672		T3	739960
hw_debug_en_valid_off	109683024	1			T1	544598		T2	190238		T3	189816
hw_debug_en_on	20821998	1			T1	194578		T2	213908		T3	134234

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109777842	1			T1	438816		T2	265814		T3	126134
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97963561	1			T1	438816		T2	106250		T3	51958
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8657237	1			T2	77690		T3	74176		T10	10306
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3942628	1			T1	77394		T3	61420		T10	16980
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1723382	1			T1	77394		T24	47156		T52	10802
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1459122	1			T3	61420		T10	16980		T5	26264
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3969810	1			T1	33338		T2	51764		T10	39370
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1506572	1			T1	33338		T2	51764		T10	11264
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1999596	1			T10	28106		T24	13916		T23	16406
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7617598	1			T1	22058		T2	82172		T3	57944
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3275524	1			T1	22058		T2	12164		T3	2936
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3178466	1			T2	70008		T3	55008		T10	10306

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9866882	1			T1	17262		T2	113960		T3	36572
lc_exec_en	9234590	1			T1	139182		T2	79972		T3	76290
valid_exec_dis	107180970	1			T1	603766		T2	181192		T3	410202
invalid_exec_dis	32065838	1			T1	353966		T2	305858		T3	613826