Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42820106	1			T1	247453		T2	103831		T3	227487
triple_byte_access	2444560	1			T1	5084		T2	2173		T3	4178
halfword_access	3668045	1			T1	7415		T2	3188		T3	6209
byte_access	4899769	1			T1	9842		T2	4203		T3	8345
zero_access	1233485	1			T1	2490		T2	983		T3	2151

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27481095

1

T1

136015

T2

57038

T3

124308

auto[1]

27584870

1

T1

136269

T2

57340

T3

124062

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21362191	1			T1	123700		T2	51806		T3	113816
auto[0]	triple_byte_access	1218211	1			T1	2505		T2	1060		T3	2114
auto[0]	halfword_access	1831118	1			T1	3695		T2	1594		T3	3098
auto[0]	byte_access	2449186	1			T1	4887		T2	2099		T3	4227
auto[0]	zero_access	620389	1			T1	1228		T2	479		T3	1053
auto[1]	word_access	21457915	1			T1	123753		T2	52025		T3	113671
auto[1]	triple_byte_access	1226349	1			T1	2579		T2	1113		T3	2064
auto[1]	halfword_access	1836927	1			T1	3720		T2	1594		T3	3111
auto[1]	byte_access	2450583	1			T1	4955		T2	2104		T3	4118
auto[1]	zero_access	613096	1			T1	1262		T2	504		T3	1098