Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147623128	1			T1	640		T2	433686		T3	236712
instr_valid_dis	118465647	1			T1	640		T3	136150		T4	8228
instr_en	19688532	1			T2	433686		T3	86256		T6	24840

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11327559	1			T2	39166		T3	39188		T6	11414
sram_ifetch_valid_disable	115293594	1			T1	640		T2	342240		T3	153264
sram_ifetch_enable	21001975	1			T2	52280		T3	44260		T6	119312

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147623128	1			T1	640		T2	433686		T3	236712
hw_debug_en_valid_off	115651863	1			T1	640		T2	210744		T3	235440
hw_debug_en_on	20918808	1			T2	180614		T3	1272		T6	58914

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115293594	1			T1	640		T2	342240		T3	153264
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	104310085	1			T1	640		T3	136150		T4	8228
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7448228	1			T2	342240		T3	17114		T6	14230
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4307402	1			T2	12438		T3	39188		T6	11414
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1660204	1			T7	58696		T142	82388		T145	1292
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1687062	1			T2	12438		T3	39188		T19	93926
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4733269	1			T2	26728		T7	11522		T19	10646
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1927429	1			T142	2990		T143	27734		T145	21356
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1934278	1			T2	26728		T19	10646		T62	17580
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8450170	1			T2	153886		T6	17150		T19	21904
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4156306	1			T6	17150		T62	21262		T75	84
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3081382	1			T2	153886		T19	21904		T20	171386

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7335144	1			T2	52280		T3	29954		T6	10610
lc_exec_en	7735369	1			T3	1272		T6	41764		T19	75468
valid_exec_dis	112763804	1			T1	640		T2	146026		T3	153264
invalid_exec_dis	32329534	1			T2	91446		T3	83448		T6	130726