Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44392213	1			T1	25		T2	78844		T3	42859
triple_byte_access	2588397	1			T1	2		T2	1545		T3	878
halfword_access	3884068	1			T2	2397		T3	1281		T4	4
byte_access	5191649	1			T1	1		T2	3097		T3	1734
zero_access	1305972	1			T2	766		T3	430		T4	2

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28631490

1

T1

10

T2

43417

T3

23461

auto[1]

28730809

1

T1

18

T2

43232

T3

23721

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22150417	1			T1	9		T2	39579		T3	21342
auto[0]	triple_byte_access	1290710	1			T1	1		T2	750		T3	423
auto[0]	halfword_access	1938490	1			T2	1150		T3	604		T4	3
auto[0]	byte_access	2595556	1			T2	1549		T3	871		T4	1
auto[0]	zero_access	656317	1			T2	389		T3	221		T4	1
auto[1]	word_access	22241796	1			T1	16		T2	39265		T3	21517
auto[1]	triple_byte_access	1297687	1			T1	1		T2	795		T3	455
auto[1]	halfword_access	1945578	1			T2	1247		T3	677		T4	1
auto[1]	byte_access	2596093	1			T1	1		T2	1548		T3	863
auto[1]	zero_access	649655	1			T2	377		T3	209		T4	1