Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1027
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T796 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3504418285 May 21 01:56:53 PM PDT 24 May 21 01:56:56 PM PDT 24 40585684 ps
T797 /workspace/coverage/default/37.sram_ctrl_multiple_keys.1759670571 May 21 02:00:41 PM PDT 24 May 21 02:09:39 PM PDT 24 7537992525 ps
T798 /workspace/coverage/default/20.sram_ctrl_ram_cfg.1787671494 May 21 01:58:30 PM PDT 24 May 21 01:58:32 PM PDT 24 165531004 ps
T799 /workspace/coverage/default/13.sram_ctrl_max_throughput.3150385668 May 21 01:57:37 PM PDT 24 May 21 01:59:58 PM PDT 24 137671586 ps
T800 /workspace/coverage/default/15.sram_ctrl_multiple_keys.3883468651 May 21 01:57:51 PM PDT 24 May 21 02:06:47 PM PDT 24 8146483717 ps
T801 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.732504125 May 21 01:56:56 PM PDT 24 May 21 02:00:43 PM PDT 24 8647852483 ps
T88 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1266681668 May 21 01:57:14 PM PDT 24 May 21 01:57:22 PM PDT 24 65442497 ps
T802 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3721488658 May 21 01:56:50 PM PDT 24 May 21 01:56:53 PM PDT 24 46100930 ps
T803 /workspace/coverage/default/43.sram_ctrl_alert_test.3738196942 May 21 02:01:42 PM PDT 24 May 21 02:01:44 PM PDT 24 19511096 ps
T804 /workspace/coverage/default/28.sram_ctrl_executable.1664813088 May 21 01:59:30 PM PDT 24 May 21 02:02:09 PM PDT 24 18217940732 ps
T805 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4130687546 May 21 01:58:52 PM PDT 24 May 21 02:03:44 PM PDT 24 49007221259 ps
T806 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2095307426 May 21 01:57:40 PM PDT 24 May 21 02:14:02 PM PDT 24 3173741974 ps
T807 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2496362289 May 21 02:00:26 PM PDT 24 May 21 02:08:17 PM PDT 24 3184651436 ps
T808 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1517408317 May 21 01:57:09 PM PDT 24 May 21 02:02:29 PM PDT 24 15888743372 ps
T809 /workspace/coverage/default/45.sram_ctrl_regwen.3419651773 May 21 02:01:58 PM PDT 24 May 21 02:25:01 PM PDT 24 11135997546 ps
T810 /workspace/coverage/default/0.sram_ctrl_multiple_keys.2745542978 May 21 01:56:42 PM PDT 24 May 21 02:13:23 PM PDT 24 12209332059 ps
T811 /workspace/coverage/default/25.sram_ctrl_alert_test.2914995260 May 21 01:59:11 PM PDT 24 May 21 01:59:12 PM PDT 24 16005446 ps
T812 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3766564507 May 21 02:01:47 PM PDT 24 May 21 02:02:39 PM PDT 24 117772207 ps
T813 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3282507867 May 21 01:56:50 PM PDT 24 May 21 01:58:45 PM PDT 24 1882123844 ps
T814 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2029310938 May 21 01:58:37 PM PDT 24 May 21 02:08:37 PM PDT 24 2762444146 ps
T815 /workspace/coverage/default/25.sram_ctrl_regwen.302843440 May 21 01:59:07 PM PDT 24 May 21 02:09:07 PM PDT 24 1418273373 ps
T816 /workspace/coverage/default/24.sram_ctrl_partial_access.2130482921 May 21 01:58:59 PM PDT 24 May 21 02:01:33 PM PDT 24 1657834269 ps
T817 /workspace/coverage/default/30.sram_ctrl_executable.1399109014 May 21 01:59:45 PM PDT 24 May 21 02:15:00 PM PDT 24 14047046000 ps
T818 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3308524339 May 21 01:57:18 PM PDT 24 May 21 02:01:04 PM PDT 24 15382367764 ps
T819 /workspace/coverage/default/34.sram_ctrl_ram_cfg.935835519 May 21 02:00:18 PM PDT 24 May 21 02:00:19 PM PDT 24 29799591 ps
T820 /workspace/coverage/default/23.sram_ctrl_lc_escalation.920870695 May 21 01:58:50 PM PDT 24 May 21 01:58:55 PM PDT 24 366808990 ps
T821 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2622748106 May 21 02:00:17 PM PDT 24 May 21 02:01:54 PM PDT 24 364505797 ps
T822 /workspace/coverage/default/16.sram_ctrl_ram_cfg.548626923 May 21 01:57:57 PM PDT 24 May 21 01:58:00 PM PDT 24 32940255 ps
T823 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.4157607408 May 21 01:57:52 PM PDT 24 May 21 02:06:27 PM PDT 24 2405418924 ps
T824 /workspace/coverage/default/36.sram_ctrl_partial_access.229293161 May 21 02:00:34 PM PDT 24 May 21 02:01:56 PM PDT 24 1867817670 ps
T825 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1088941829 May 21 01:58:16 PM PDT 24 May 21 02:05:53 PM PDT 24 21006089534 ps
T826 /workspace/coverage/default/39.sram_ctrl_ram_cfg.3446768259 May 21 02:01:05 PM PDT 24 May 21 02:01:06 PM PDT 24 94099616 ps
T827 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2599199410 May 21 01:57:31 PM PDT 24 May 21 01:57:33 PM PDT 24 30350954 ps
T828 /workspace/coverage/default/18.sram_ctrl_stress_all.3388552611 May 21 01:58:16 PM PDT 24 May 21 02:21:08 PM PDT 24 146085346754 ps
T829 /workspace/coverage/default/36.sram_ctrl_ram_cfg.2947046284 May 21 02:00:39 PM PDT 24 May 21 02:00:41 PM PDT 24 76671732 ps
T830 /workspace/coverage/default/3.sram_ctrl_bijection.197674863 May 21 01:56:54 PM PDT 24 May 21 01:57:45 PM PDT 24 12136062421 ps
T831 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1773212343 May 21 01:57:28 PM PDT 24 May 21 02:02:03 PM PDT 24 15519212468 ps
T832 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3871530545 May 21 01:57:20 PM PDT 24 May 21 01:57:23 PM PDT 24 37375662 ps
T32 /workspace/coverage/default/2.sram_ctrl_sec_cm.4126524411 May 21 01:56:54 PM PDT 24 May 21 01:57:00 PM PDT 24 123078271 ps
T833 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1131938620 May 21 01:57:22 PM PDT 24 May 21 02:00:38 PM PDT 24 2217308769 ps
T834 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.112218099 May 21 01:56:53 PM PDT 24 May 21 02:01:53 PM PDT 24 8623381857 ps
T835 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3475717331 May 21 01:57:31 PM PDT 24 May 21 01:57:33 PM PDT 24 80371695 ps
T836 /workspace/coverage/default/5.sram_ctrl_stress_all.1885942150 May 21 01:57:11 PM PDT 24 May 21 02:51:44 PM PDT 24 145339783228 ps
T837 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.807038206 May 21 02:00:44 PM PDT 24 May 21 02:04:12 PM PDT 24 2629354325 ps
T838 /workspace/coverage/default/24.sram_ctrl_max_throughput.361821916 May 21 01:58:56 PM PDT 24 May 21 01:58:59 PM PDT 24 50635443 ps
T839 /workspace/coverage/default/16.sram_ctrl_regwen.1156733669 May 21 01:58:00 PM PDT 24 May 21 02:18:30 PM PDT 24 63732353403 ps
T840 /workspace/coverage/default/31.sram_ctrl_stress_all.4080312491 May 21 01:59:55 PM PDT 24 May 21 02:59:39 PM PDT 24 165922673665 ps
T841 /workspace/coverage/default/17.sram_ctrl_ram_cfg.1794665019 May 21 01:58:05 PM PDT 24 May 21 01:58:07 PM PDT 24 46090036 ps
T842 /workspace/coverage/default/4.sram_ctrl_smoke.1295960652 May 21 01:57:01 PM PDT 24 May 21 01:57:36 PM PDT 24 349369882 ps
T843 /workspace/coverage/default/9.sram_ctrl_partial_access.938287035 May 21 01:57:18 PM PDT 24 May 21 01:57:23 PM PDT 24 312120392 ps
T844 /workspace/coverage/default/48.sram_ctrl_partial_access.2001287006 May 21 02:02:20 PM PDT 24 May 21 02:02:30 PM PDT 24 79216699 ps
T845 /workspace/coverage/default/34.sram_ctrl_alert_test.1637608591 May 21 02:00:21 PM PDT 24 May 21 02:00:22 PM PDT 24 34745993 ps
T846 /workspace/coverage/default/20.sram_ctrl_regwen.1091532167 May 21 01:58:32 PM PDT 24 May 21 02:14:06 PM PDT 24 12458841676 ps
T847 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.431065443 May 21 02:01:00 PM PDT 24 May 21 02:01:06 PM PDT 24 253299865 ps
T848 /workspace/coverage/default/6.sram_ctrl_smoke.560027651 May 21 01:57:06 PM PDT 24 May 21 01:57:26 PM PDT 24 958343688 ps
T849 /workspace/coverage/default/25.sram_ctrl_max_throughput.2159098480 May 21 01:59:06 PM PDT 24 May 21 01:59:42 PM PDT 24 382805091 ps
T850 /workspace/coverage/default/47.sram_ctrl_executable.4104510251 May 21 02:02:11 PM PDT 24 May 21 02:04:39 PM PDT 24 1674792762 ps
T116 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.361414636 May 21 02:02:05 PM PDT 24 May 21 02:03:19 PM PDT 24 9978440933 ps
T851 /workspace/coverage/default/40.sram_ctrl_partial_access.1763651083 May 21 02:01:09 PM PDT 24 May 21 02:01:22 PM PDT 24 225175485 ps
T852 /workspace/coverage/default/6.sram_ctrl_executable.2635312502 May 21 01:57:09 PM PDT 24 May 21 02:00:06 PM PDT 24 6772765195 ps
T853 /workspace/coverage/default/49.sram_ctrl_stress_all.3297792990 May 21 02:02:33 PM PDT 24 May 21 02:04:15 PM PDT 24 27255206992 ps
T854 /workspace/coverage/default/42.sram_ctrl_lc_escalation.4147109809 May 21 02:01:29 PM PDT 24 May 21 02:01:36 PM PDT 24 524179311 ps
T855 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.39115384 May 21 02:00:11 PM PDT 24 May 21 02:02:37 PM PDT 24 7787085114 ps
T856 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3914000565 May 21 02:01:22 PM PDT 24 May 21 02:01:47 PM PDT 24 191610790 ps
T857 /workspace/coverage/default/10.sram_ctrl_regwen.1338156072 May 21 01:57:20 PM PDT 24 May 21 02:17:49 PM PDT 24 138094656761 ps
T858 /workspace/coverage/default/38.sram_ctrl_multiple_keys.3414151310 May 21 02:00:52 PM PDT 24 May 21 02:14:29 PM PDT 24 14561786866 ps
T859 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2817054300 May 21 02:01:34 PM PDT 24 May 21 02:06:52 PM PDT 24 3218636903 ps
T860 /workspace/coverage/default/39.sram_ctrl_alert_test.3520665168 May 21 02:01:10 PM PDT 24 May 21 02:01:11 PM PDT 24 14177971 ps
T861 /workspace/coverage/default/3.sram_ctrl_lc_escalation.917348319 May 21 01:56:55 PM PDT 24 May 21 01:57:00 PM PDT 24 230570122 ps
T862 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1183021273 May 21 01:56:56 PM PDT 24 May 21 02:02:12 PM PDT 24 368017024 ps
T117 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.773107065 May 21 01:58:56 PM PDT 24 May 21 01:59:38 PM PDT 24 2686828353 ps
T863 /workspace/coverage/default/5.sram_ctrl_multiple_keys.763996189 May 21 01:57:07 PM PDT 24 May 21 02:14:17 PM PDT 24 3280711800 ps
T864 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3860896592 May 21 01:59:32 PM PDT 24 May 21 02:05:15 PM PDT 24 4817360866 ps
T865 /workspace/coverage/default/13.sram_ctrl_ram_cfg.1372248011 May 21 01:57:38 PM PDT 24 May 21 01:57:40 PM PDT 24 44642023 ps
T866 /workspace/coverage/default/36.sram_ctrl_max_throughput.1514748288 May 21 02:00:39 PM PDT 24 May 21 02:00:54 PM PDT 24 150655096 ps
T867 /workspace/coverage/default/46.sram_ctrl_alert_test.3495616135 May 21 02:02:05 PM PDT 24 May 21 02:02:06 PM PDT 24 49907478 ps
T868 /workspace/coverage/default/23.sram_ctrl_bijection.1410314741 May 21 01:58:50 PM PDT 24 May 21 02:00:06 PM PDT 24 18797279178 ps
T869 /workspace/coverage/default/34.sram_ctrl_stress_all.929674106 May 21 02:00:20 PM PDT 24 May 21 02:22:11 PM PDT 24 30488673553 ps
T870 /workspace/coverage/default/31.sram_ctrl_mem_walk.1327579030 May 21 01:59:54 PM PDT 24 May 21 01:59:59 PM PDT 24 72769967 ps
T871 /workspace/coverage/default/39.sram_ctrl_max_throughput.1954545481 May 21 02:01:05 PM PDT 24 May 21 02:04:04 PM PDT 24 143810148 ps
T872 /workspace/coverage/default/14.sram_ctrl_stress_all.962778420 May 21 01:57:50 PM PDT 24 May 21 02:42:43 PM PDT 24 126408081044 ps
T873 /workspace/coverage/default/10.sram_ctrl_executable.3448227271 May 21 01:57:19 PM PDT 24 May 21 02:12:19 PM PDT 24 43462274730 ps
T874 /workspace/coverage/default/22.sram_ctrl_multiple_keys.3210823341 May 21 01:58:38 PM PDT 24 May 21 02:23:49 PM PDT 24 34310857705 ps
T875 /workspace/coverage/default/35.sram_ctrl_max_throughput.2305061546 May 21 02:00:24 PM PDT 24 May 21 02:00:58 PM PDT 24 373469995 ps
T876 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3193059626 May 21 01:59:11 PM PDT 24 May 21 01:59:15 PM PDT 24 50084810 ps
T877 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3005316323 May 21 02:01:53 PM PDT 24 May 21 02:02:21 PM PDT 24 114410355 ps
T878 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.530538970 May 21 01:59:25 PM PDT 24 May 21 01:59:31 PM PDT 24 152163391 ps
T879 /workspace/coverage/default/40.sram_ctrl_lc_escalation.1923382253 May 21 02:01:14 PM PDT 24 May 21 02:01:23 PM PDT 24 4803080677 ps
T880 /workspace/coverage/default/10.sram_ctrl_bijection.3268977034 May 21 01:57:21 PM PDT 24 May 21 01:58:40 PM PDT 24 11438733086 ps
T881 /workspace/coverage/default/36.sram_ctrl_multiple_keys.3968853925 May 21 02:00:34 PM PDT 24 May 21 02:13:29 PM PDT 24 8527419610 ps
T882 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3411494040 May 21 01:58:17 PM PDT 24 May 21 01:59:38 PM PDT 24 5325369856 ps
T883 /workspace/coverage/default/29.sram_ctrl_executable.724955161 May 21 01:59:37 PM PDT 24 May 21 02:12:15 PM PDT 24 38655289331 ps
T884 /workspace/coverage/default/48.sram_ctrl_lc_escalation.1260421631 May 21 02:02:17 PM PDT 24 May 21 02:02:27 PM PDT 24 4300324517 ps
T885 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1249929437 May 21 01:57:38 PM PDT 24 May 21 01:57:42 PM PDT 24 92873439 ps
T886 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2710729721 May 21 02:00:40 PM PDT 24 May 21 02:00:43 PM PDT 24 115184198 ps
T887 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2114298523 May 21 01:56:52 PM PDT 24 May 21 02:00:54 PM PDT 24 2450931516 ps
T33 /workspace/coverage/default/4.sram_ctrl_sec_cm.2468614924 May 21 01:57:08 PM PDT 24 May 21 01:57:13 PM PDT 24 716341805 ps
T888 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.813222354 May 21 02:01:34 PM PDT 24 May 21 02:06:46 PM PDT 24 12387272750 ps
T889 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2428633184 May 21 01:59:41 PM PDT 24 May 21 02:20:57 PM PDT 24 136534701240 ps
T890 /workspace/coverage/default/11.sram_ctrl_max_throughput.1019382511 May 21 01:57:25 PM PDT 24 May 21 01:59:15 PM PDT 24 271437191 ps
T891 /workspace/coverage/default/47.sram_ctrl_max_throughput.1532933657 May 21 02:02:13 PM PDT 24 May 21 02:02:58 PM PDT 24 193427894 ps
T892 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.841709919 May 21 01:59:17 PM PDT 24 May 21 02:11:28 PM PDT 24 12780396170 ps
T893 /workspace/coverage/default/1.sram_ctrl_max_throughput.899284608 May 21 01:56:46 PM PDT 24 May 21 01:57:06 PM PDT 24 85133833 ps
T894 /workspace/coverage/default/26.sram_ctrl_multiple_keys.2402891245 May 21 01:59:10 PM PDT 24 May 21 02:04:53 PM PDT 24 27250831705 ps
T895 /workspace/coverage/default/2.sram_ctrl_multiple_keys.1466132491 May 21 01:56:48 PM PDT 24 May 21 02:22:03 PM PDT 24 20291427926 ps
T896 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2970732465 May 21 02:00:26 PM PDT 24 May 21 02:03:11 PM PDT 24 3787462090 ps
T897 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.191149465 May 21 01:58:24 PM PDT 24 May 21 02:02:34 PM PDT 24 3770528127 ps
T898 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1170273401 May 21 02:01:42 PM PDT 24 May 21 02:01:46 PM PDT 24 49471980 ps
T899 /workspace/coverage/default/7.sram_ctrl_partial_access.2060729517 May 21 01:57:15 PM PDT 24 May 21 01:58:20 PM PDT 24 863642274 ps
T900 /workspace/coverage/default/38.sram_ctrl_bijection.3615495634 May 21 02:00:50 PM PDT 24 May 21 02:01:16 PM PDT 24 1641662758 ps
T901 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1046129667 May 21 01:58:02 PM PDT 24 May 21 02:21:04 PM PDT 24 18121348716 ps
T902 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3311957797 May 21 02:01:04 PM PDT 24 May 21 02:06:37 PM PDT 24 13814932331 ps
T903 /workspace/coverage/default/26.sram_ctrl_regwen.122567063 May 21 01:59:16 PM PDT 24 May 21 02:15:13 PM PDT 24 2658763060 ps
T904 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3526977221 May 21 02:01:40 PM PDT 24 May 21 02:03:03 PM PDT 24 704863731 ps
T905 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4006564754 May 21 01:58:30 PM PDT 24 May 21 01:59:17 PM PDT 24 3151027601 ps
T906 /workspace/coverage/default/7.sram_ctrl_regwen.695622260 May 21 01:57:13 PM PDT 24 May 21 02:09:38 PM PDT 24 18156855700 ps
T907 /workspace/coverage/default/33.sram_ctrl_max_throughput.4054716311 May 21 02:00:06 PM PDT 24 May 21 02:00:26 PM PDT 24 270623591 ps
T908 /workspace/coverage/default/22.sram_ctrl_max_throughput.1180264427 May 21 01:58:44 PM PDT 24 May 21 01:59:25 PM PDT 24 188535120 ps
T909 /workspace/coverage/default/12.sram_ctrl_multiple_keys.3493851315 May 21 01:57:27 PM PDT 24 May 21 02:15:23 PM PDT 24 21769698662 ps
T910 /workspace/coverage/default/7.sram_ctrl_alert_test.1759083828 May 21 01:57:13 PM PDT 24 May 21 01:57:17 PM PDT 24 11423968 ps
T911 /workspace/coverage/default/8.sram_ctrl_smoke.3050697539 May 21 01:57:12 PM PDT 24 May 21 01:57:24 PM PDT 24 9829366906 ps
T912 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1139289962 May 21 01:59:46 PM PDT 24 May 21 02:04:37 PM PDT 24 5535097068 ps
T913 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3568656278 May 21 01:56:50 PM PDT 24 May 21 02:08:56 PM PDT 24 2677319541 ps
T914 /workspace/coverage/default/35.sram_ctrl_lc_escalation.3386228480 May 21 02:00:25 PM PDT 24 May 21 02:00:31 PM PDT 24 1007339804 ps
T915 /workspace/coverage/default/18.sram_ctrl_alert_test.2424504265 May 21 01:58:18 PM PDT 24 May 21 01:58:21 PM PDT 24 30479431 ps
T916 /workspace/coverage/default/19.sram_ctrl_max_throughput.3647398468 May 21 01:58:17 PM PDT 24 May 21 01:58:32 PM PDT 24 320555156 ps
T917 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.664141321 May 21 02:00:00 PM PDT 24 May 21 02:00:05 PM PDT 24 823397648 ps
T918 /workspace/coverage/default/1.sram_ctrl_stress_all.3370920964 May 21 01:56:50 PM PDT 24 May 21 02:57:56 PM PDT 24 89778169202 ps
T919 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1464302590 May 21 01:57:38 PM PDT 24 May 21 02:01:36 PM PDT 24 37537454078 ps
T920 /workspace/coverage/default/22.sram_ctrl_smoke.2978935413 May 21 01:58:36 PM PDT 24 May 21 01:59:43 PM PDT 24 230623268 ps
T921 /workspace/coverage/default/32.sram_ctrl_executable.1531517503 May 21 02:00:00 PM PDT 24 May 21 02:10:54 PM PDT 24 14102351567 ps
T922 /workspace/coverage/default/35.sram_ctrl_regwen.499187586 May 21 02:00:25 PM PDT 24 May 21 02:17:50 PM PDT 24 11938823408 ps
T923 /workspace/coverage/default/35.sram_ctrl_smoke.2516233839 May 21 02:00:21 PM PDT 24 May 21 02:01:18 PM PDT 24 3878405384 ps
T924 /workspace/coverage/default/49.sram_ctrl_executable.4244210449 May 21 02:02:28 PM PDT 24 May 21 02:06:25 PM PDT 24 1185742526 ps
T925 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3366304072 May 21 01:59:42 PM PDT 24 May 21 02:02:15 PM PDT 24 149657845 ps
T926 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.678372524 May 21 02:00:02 PM PDT 24 May 21 02:07:10 PM PDT 24 76132941482 ps
T927 /workspace/coverage/default/32.sram_ctrl_lc_escalation.3975014571 May 21 02:00:01 PM PDT 24 May 21 02:00:05 PM PDT 24 1850181114 ps
T928 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2785107098 May 21 01:58:49 PM PDT 24 May 21 01:58:54 PM PDT 24 334980277 ps
T929 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3274513238 May 21 02:02:18 PM PDT 24 May 21 02:02:59 PM PDT 24 1676586669 ps
T930 /workspace/coverage/default/39.sram_ctrl_bijection.1300449280 May 21 02:00:58 PM PDT 24 May 21 02:01:29 PM PDT 24 19242098270 ps
T931 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2666646338 May 21 01:58:49 PM PDT 24 May 21 01:58:51 PM PDT 24 99763173 ps
T932 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.52783552 May 21 01:57:11 PM PDT 24 May 21 01:57:17 PM PDT 24 165993469 ps
T933 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3728770190 May 21 02:01:58 PM PDT 24 May 21 02:02:06 PM PDT 24 660019514 ps
T934 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1528342730 May 21 12:37:59 PM PDT 24 May 21 12:38:17 PM PDT 24 121400064 ps
T106 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1483527599 May 21 12:37:54 PM PDT 24 May 21 12:38:11 PM PDT 24 466783109 ps
T103 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3450254788 May 21 12:37:55 PM PDT 24 May 21 12:38:11 PM PDT 24 51062963 ps
T107 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3992083418 May 21 12:37:58 PM PDT 24 May 21 12:38:17 PM PDT 24 384384935 ps
T935 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2158199966 May 21 12:38:00 PM PDT 24 May 21 12:38:18 PM PDT 24 31209445 ps
T936 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3595636245 May 21 12:37:41 PM PDT 24 May 21 12:37:59 PM PDT 24 331742884 ps
T937 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2506112408 May 21 12:37:55 PM PDT 24 May 21 12:38:12 PM PDT 24 128351339 ps
T94 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.277922364 May 21 12:37:55 PM PDT 24 May 21 12:38:12 PM PDT 24 21702004 ps
T104 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.258981554 May 21 12:38:01 PM PDT 24 May 21 12:38:18 PM PDT 24 16907730 ps
T938 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1269356641 May 21 12:37:59 PM PDT 24 May 21 12:38:19 PM PDT 24 37378120 ps
T64 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.710089112 May 21 12:37:57 PM PDT 24 May 21 12:38:17 PM PDT 24 444472807 ps
T65 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.899107783 May 21 12:37:53 PM PDT 24 May 21 12:38:09 PM PDT 24 15229722 ps
T95 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3272512242 May 21 12:37:56 PM PDT 24 May 21 12:38:13 PM PDT 24 46240592 ps
T939 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2971606224 May 21 12:38:03 PM PDT 24 May 21 12:38:22 PM PDT 24 40157656 ps
T940 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1355606887 May 21 12:37:56 PM PDT 24 May 21 12:38:16 PM PDT 24 126142438 ps
T66 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.792907938 May 21 12:37:54 PM PDT 24 May 21 12:38:09 PM PDT 24 51596801 ps
T941 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3930512912 May 21 12:37:57 PM PDT 24 May 21 12:38:15 PM PDT 24 764157866 ps
T108 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1267576815 May 21 12:37:55 PM PDT 24 May 21 12:38:12 PM PDT 24 366464423 ps
T942 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3047883848 May 21 12:37:57 PM PDT 24 May 21 12:38:19 PM PDT 24 162801026 ps
T67 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2201570793 May 21 12:38:26 PM PDT 24 May 21 12:38:40 PM PDT 24 456705442 ps
T943 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4287593897 May 21 12:37:43 PM PDT 24 May 21 12:38:02 PM PDT 24 465431025 ps
T68 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1569605638 May 21 12:38:02 PM PDT 24 May 21 12:38:20 PM PDT 24 32930649 ps
T69 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3760846009 May 21 12:37:51 PM PDT 24 May 21 12:38:09 PM PDT 24 379855549 ps
T70 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3834323540 May 21 12:37:52 PM PDT 24 May 21 12:38:09 PM PDT 24 339082799 ps
T944 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3501345327 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 29568550 ps
T945 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2823809584 May 21 12:37:54 PM PDT 24 May 21 12:38:10 PM PDT 24 44147134 ps
T71 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1949304167 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 66817763 ps
T946 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4131300759 May 21 12:37:59 PM PDT 24 May 21 12:38:19 PM PDT 24 77616969 ps
T129 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2632857208 May 21 12:37:56 PM PDT 24 May 21 12:38:14 PM PDT 24 176707776 ps
T947 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.506712367 May 21 12:37:53 PM PDT 24 May 21 12:38:10 PM PDT 24 72489954 ps
T72 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2022585250 May 21 12:37:41 PM PDT 24 May 21 12:37:58 PM PDT 24 917054980 ps
T73 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.220878740 May 21 12:37:54 PM PDT 24 May 21 12:38:10 PM PDT 24 15697953 ps
T948 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.196480226 May 21 12:37:52 PM PDT 24 May 21 12:38:08 PM PDT 24 18382202 ps
T949 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1764400254 May 21 12:37:57 PM PDT 24 May 21 12:38:16 PM PDT 24 87916520 ps
T950 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2460626356 May 21 12:37:56 PM PDT 24 May 21 12:38:12 PM PDT 24 29340329 ps
T96 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3528106758 May 21 12:37:55 PM PDT 24 May 21 12:38:11 PM PDT 24 96231627 ps
T130 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3694123435 May 21 12:37:43 PM PDT 24 May 21 12:37:59 PM PDT 24 2101504905 ps
T951 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1885298367 May 21 12:37:53 PM PDT 24 May 21 12:38:10 PM PDT 24 13978496 ps
T952 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4009398815 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 54225831 ps
T133 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2136220549 May 21 12:37:54 PM PDT 24 May 21 12:38:11 PM PDT 24 145986984 ps
T79 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2159305410 May 21 12:37:58 PM PDT 24 May 21 12:38:17 PM PDT 24 405051621 ps
T135 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2481386159 May 21 12:37:57 PM PDT 24 May 21 12:38:16 PM PDT 24 182170048 ps
T131 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1622059070 May 21 12:37:55 PM PDT 24 May 21 12:38:13 PM PDT 24 266549905 ps
T953 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1109206687 May 21 12:37:57 PM PDT 24 May 21 12:38:16 PM PDT 24 26319834 ps
T136 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.551498870 May 21 12:37:55 PM PDT 24 May 21 12:38:13 PM PDT 24 1183656371 ps
T954 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1906371630 May 21 12:37:54 PM PDT 24 May 21 12:38:10 PM PDT 24 131275826 ps
T955 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2090519443 May 21 12:38:01 PM PDT 24 May 21 12:38:19 PM PDT 24 28310566 ps
T956 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.768577191 May 21 12:37:39 PM PDT 24 May 21 12:37:55 PM PDT 24 36471146 ps
T957 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1708878616 May 21 12:37:42 PM PDT 24 May 21 12:37:58 PM PDT 24 24814015 ps
T80 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2527860895 May 21 12:37:42 PM PDT 24 May 21 12:38:00 PM PDT 24 479201634 ps
T958 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.546281341 May 21 12:37:43 PM PDT 24 May 21 12:37:58 PM PDT 24 30808948 ps
T959 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2280876856 May 21 12:37:42 PM PDT 24 May 21 12:37:57 PM PDT 24 22364665 ps
T960 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3088718720 May 21 12:37:39 PM PDT 24 May 21 12:37:56 PM PDT 24 45115516 ps
T89 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2124489506 May 21 12:37:49 PM PDT 24 May 21 12:38:05 PM PDT 24 711419487 ps
T132 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1549695453 May 21 12:37:58 PM PDT 24 May 21 12:38:18 PM PDT 24 1819907574 ps
T81 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3796050504 May 21 12:37:47 PM PDT 24 May 21 12:38:05 PM PDT 24 1702856187 ps
T961 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.486783299 May 21 12:37:56 PM PDT 24 May 21 12:38:13 PM PDT 24 22844594 ps
T962 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1964720607 May 21 12:37:39 PM PDT 24 May 21 12:37:56 PM PDT 24 27762591 ps
T963 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.921613934 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 38487954 ps
T137 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2806919732 May 21 12:37:51 PM PDT 24 May 21 12:38:08 PM PDT 24 341583618 ps
T964 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2991841798 May 21 12:37:56 PM PDT 24 May 21 12:38:13 PM PDT 24 74689849 ps
T93 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2043498694 May 21 12:38:03 PM PDT 24 May 21 12:38:23 PM PDT 24 1584208051 ps
T965 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3447191543 May 21 12:37:55 PM PDT 24 May 21 12:38:12 PM PDT 24 901840807 ps
T966 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1786038835 May 21 12:38:00 PM PDT 24 May 21 12:38:19 PM PDT 24 377022825 ps
T138 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1635204144 May 21 12:37:58 PM PDT 24 May 21 12:38:18 PM PDT 24 254364599 ps
T82 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.215949464 May 21 12:38:00 PM PDT 24 May 21 12:38:20 PM PDT 24 1427473324 ps
T83 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3622456199 May 21 12:37:56 PM PDT 24 May 21 12:38:15 PM PDT 24 1895611283 ps
T967 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.611319505 May 21 12:37:40 PM PDT 24 May 21 12:37:57 PM PDT 24 103155501 ps
T90 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2894923448 May 21 12:37:53 PM PDT 24 May 21 12:38:12 PM PDT 24 424397388 ps
T968 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1261142349 May 21 12:37:52 PM PDT 24 May 21 12:38:07 PM PDT 24 50523080 ps
T969 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.395500275 May 21 12:37:43 PM PDT 24 May 21 12:38:00 PM PDT 24 81363581 ps
T970 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2101121479 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 29029587 ps
T971 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3255232023 May 21 12:37:55 PM PDT 24 May 21 12:38:15 PM PDT 24 134170273 ps
T972 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2297461221 May 21 12:37:56 PM PDT 24 May 21 12:38:12 PM PDT 24 46918990 ps
T973 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4012440977 May 21 12:38:02 PM PDT 24 May 21 12:38:20 PM PDT 24 110177192 ps
T974 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3647914925 May 21 12:37:42 PM PDT 24 May 21 12:37:57 PM PDT 24 63859336 ps
T975 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.796684511 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 23930347 ps
T91 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3096028746 May 21 12:38:00 PM PDT 24 May 21 12:38:18 PM PDT 24 201728687 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3482914505 May 21 12:37:43 PM PDT 24 May 21 12:37:58 PM PDT 24 50573254 ps
T977 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2490529018 May 21 12:37:41 PM PDT 24 May 21 12:38:01 PM PDT 24 158151064 ps
T978 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1261119033 May 21 12:37:56 PM PDT 24 May 21 12:38:14 PM PDT 24 357404978 ps
T979 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4170033133 May 21 12:37:40 PM PDT 24 May 21 12:37:57 PM PDT 24 66498743 ps
T980 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1694446120 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 41297452 ps
T981 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3734771688 May 21 12:38:00 PM PDT 24 May 21 12:38:18 PM PDT 24 190767332 ps
T982 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.471876021 May 21 12:37:56 PM PDT 24 May 21 12:38:16 PM PDT 24 112300689 ps
T983 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.142387228 May 21 12:37:55 PM PDT 24 May 21 12:38:12 PM PDT 24 21172066 ps
T984 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3783238548 May 21 12:37:42 PM PDT 24 May 21 12:37:58 PM PDT 24 61467698 ps
T985 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3377419295 May 21 12:37:58 PM PDT 24 May 21 12:38:17 PM PDT 24 204016995 ps
T986 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4289708745 May 21 12:37:48 PM PDT 24 May 21 12:38:05 PM PDT 24 566505677 ps
T987 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4039274192 May 21 12:37:54 PM PDT 24 May 21 12:38:12 PM PDT 24 452374858 ps
T988 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3694552040 May 21 12:37:57 PM PDT 24 May 21 12:38:13 PM PDT 24 13029718 ps
T989 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2817942836 May 21 12:37:59 PM PDT 24 May 21 12:38:17 PM PDT 24 96142995 ps
T990 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3732061751 May 21 12:37:56 PM PDT 24 May 21 12:38:13 PM PDT 24 95107498 ps
T134 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3520542156 May 21 12:37:42 PM PDT 24 May 21 12:37:58 PM PDT 24 331077234 ps
T991 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3532475837 May 21 12:38:18 PM PDT 24 May 21 12:38:31 PM PDT 24 15167753 ps
T92 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.206746324 May 21 12:37:56 PM PDT 24 May 21 12:38:16 PM PDT 24 771752826 ps
T992 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.355104851 May 21 12:37:49 PM PDT 24 May 21 12:38:04 PM PDT 24 71948299 ps
T993 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.347779019 May 21 12:37:59 PM PDT 24 May 21 12:38:17 PM PDT 24 48933723 ps
T994 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3618216241 May 21 12:37:54 PM PDT 24 May 21 12:38:10 PM PDT 24 13107744 ps
T995 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3426420912 May 21 12:38:17 PM PDT 24 May 21 12:38:32 PM PDT 24 226293803 ps
T996 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.488191225 May 21 12:37:53 PM PDT 24 May 21 12:38:09 PM PDT 24 18791628 ps
T997 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3616558418 May 21 12:37:55 PM PDT 24 May 21 12:38:14 PM PDT 24 175385048 ps
T998 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.313635763 May 21 12:37:58 PM PDT 24 May 21 12:38:16 PM PDT 24 14819843 ps
T999 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3105320164 May 21 12:37:41 PM PDT 24 May 21 12:37:57 PM PDT 24 25131867 ps
T1000 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2926201209 May 21 12:37:47 PM PDT 24 May 21 12:38:02 PM PDT 24 13600038 ps
T1001 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.304100895 May 21 12:37:48 PM PDT 24 May 21 12:38:07 PM PDT 24 1520040636 ps
T1002 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3769911179 May 21 12:37:42 PM PDT 24 May 21 12:37:57 PM PDT 24 37355407 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%