Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	152234050	1			T2	410480		T3	52464		T4	8938
instr_valid_dis	119279033	1			T2	410480		T3	52464		T4	8938
instr_en	24329651	1			T7	411398		T14	483572		T60	53246

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10749300	1			T7	188432		T14	211648		T17	138224
sram_ifetch_valid_disable	118199215	1			T2	410480		T3	52464		T4	8938
sram_ifetch_enable	23285535	1			T7	544536		T14	485062		T17	165600

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	152234050	1			T2	410480		T3	52464		T4	8938
hw_debug_en_valid_off	117949141	1			T2	410480		T3	52464		T4	8938
hw_debug_en_on	23037010	1			T7	270386		T14	567108		T17	220030

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118199215	1			T2	410480		T3	52464		T4	8938
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	105390216	1			T2	410480		T3	52464		T4	8938
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9473871	1			T7	151832		T14	211194		T60	47982
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4868742	1			T7	105324		T14	50366		T17	122806
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1967704	1			T7	66686		T14	43574		T133	16710
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2010590	1			T7	38638		T14	6792		T35	95188
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4359602	1			T7	66694		T14	141282		T17	15418
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1852540	1			T7	46916		T14	4688		T60	29002
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1904820	1			T7	19778		T14	96594		T133	2956
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10048758	1			T7	68786		T14	189022		T17	47230
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4598412	1			T7	25396		T14	139382		T60	21782
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3956325	1			T7	11374		T14	49640		T133	236

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10209182	1			T7	201150		T14	168992		T60	5264
lc_exec_en	8628650	1			T7	134906		T14	236804		T17	157382
valid_exec_dis	113361266	1			T2	410480		T3	52464		T4	8938
invalid_exec_dis	34034835	1			T7	732968		T14	696710		T17	303824