Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	46238620	1			T2	186608		T3	23813		T4	4073
triple_byte_access	2466532	1			T2	3782		T3	484		T4	88
halfword_access	3698365	1			T2	5581		T3	712		T4	113
byte_access	4937829	1			T2	7403		T3	994		T4	157
zero_access	1244684	1			T2	1866		T3	229		T4	38

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29235965

1

T2

102525

T3

13121

T4

2240

auto[1]

29350065

1

T2

102715

T3

13111

T4

2229

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	23066355	1			T2	93301		T3	11861		T4	2040
auto[0]	triple_byte_access	1230119	1			T2	1858		T3	241		T4	36
auto[0]	halfword_access	1844513	1			T2	2781		T3	361		T4	61
auto[0]	byte_access	2467497	1			T2	3647		T3	531		T4	80
auto[0]	zero_access	627481	1			T2	938		T3	127		T4	23
auto[1]	word_access	23172265	1			T2	93307		T3	11952		T4	2033
auto[1]	triple_byte_access	1236413	1			T2	1924		T3	243		T4	52
auto[1]	halfword_access	1853852	1			T2	2800		T3	351		T4	52
auto[1]	byte_access	2470332	1			T2	3756		T3	463		T4	77
auto[1]	zero_access	617203	1			T2	928		T3	102		T4	15