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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 98.99 92.48 99.31 100.00 95.26 98.38 97.26


Total test records in report: 1027
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T795 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.821483308 Jun 06 02:47:20 PM PDT 24 Jun 06 02:52:11 PM PDT 24 4253618901 ps
T796 /workspace/coverage/default/48.sram_ctrl_lc_escalation.2236436312 Jun 06 02:48:24 PM PDT 24 Jun 06 02:48:33 PM PDT 24 2512996148 ps
T797 /workspace/coverage/default/33.sram_ctrl_executable.104805846 Jun 06 02:46:47 PM PDT 24 Jun 06 03:04:39 PM PDT 24 116694676038 ps
T798 /workspace/coverage/default/9.sram_ctrl_executable.652492166 Jun 06 02:44:56 PM PDT 24 Jun 06 02:54:19 PM PDT 24 36978389576 ps
T799 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.332504024 Jun 06 02:46:51 PM PDT 24 Jun 06 02:51:07 PM PDT 24 34466857018 ps
T800 /workspace/coverage/default/34.sram_ctrl_stress_all.2478569476 Jun 06 02:46:52 PM PDT 24 Jun 06 03:51:57 PM PDT 24 56319824381 ps
T801 /workspace/coverage/default/39.sram_ctrl_alert_test.3743205733 Jun 06 02:47:21 PM PDT 24 Jun 06 02:47:24 PM PDT 24 48287288 ps
T802 /workspace/coverage/default/13.sram_ctrl_multiple_keys.640648796 Jun 06 02:45:04 PM PDT 24 Jun 06 02:53:39 PM PDT 24 2128635593 ps
T803 /workspace/coverage/default/47.sram_ctrl_bijection.3119922133 Jun 06 02:48:54 PM PDT 24 Jun 06 02:49:48 PM PDT 24 2515974417 ps
T804 /workspace/coverage/default/34.sram_ctrl_multiple_keys.1025016760 Jun 06 02:46:44 PM PDT 24 Jun 06 03:06:45 PM PDT 24 3918027068 ps
T805 /workspace/coverage/default/26.sram_ctrl_lc_escalation.1088906449 Jun 06 02:46:06 PM PDT 24 Jun 06 02:46:15 PM PDT 24 2376787642 ps
T806 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3934645174 Jun 06 02:45:14 PM PDT 24 Jun 06 02:45:16 PM PDT 24 237549432 ps
T807 /workspace/coverage/default/33.sram_ctrl_partial_access.697156539 Jun 06 02:46:44 PM PDT 24 Jun 06 02:46:57 PM PDT 24 611891338 ps
T808 /workspace/coverage/default/17.sram_ctrl_stress_all.1672475895 Jun 06 02:45:26 PM PDT 24 Jun 06 03:15:47 PM PDT 24 27285278234 ps
T809 /workspace/coverage/default/16.sram_ctrl_partial_access.2174473053 Jun 06 02:45:19 PM PDT 24 Jun 06 02:45:37 PM PDT 24 311431941 ps
T810 /workspace/coverage/default/27.sram_ctrl_executable.2307390214 Jun 06 02:46:08 PM PDT 24 Jun 06 02:53:06 PM PDT 24 1278134022 ps
T811 /workspace/coverage/default/20.sram_ctrl_mem_walk.3248102805 Jun 06 02:45:35 PM PDT 24 Jun 06 02:45:43 PM PDT 24 346448816 ps
T812 /workspace/coverage/default/7.sram_ctrl_ram_cfg.1159334581 Jun 06 02:44:48 PM PDT 24 Jun 06 02:44:51 PM PDT 24 61732210 ps
T813 /workspace/coverage/default/17.sram_ctrl_multiple_keys.3953074347 Jun 06 02:45:22 PM PDT 24 Jun 06 02:47:39 PM PDT 24 1271448005 ps
T814 /workspace/coverage/default/10.sram_ctrl_alert_test.3221538970 Jun 06 02:44:57 PM PDT 24 Jun 06 02:45:00 PM PDT 24 12905181 ps
T815 /workspace/coverage/default/40.sram_ctrl_mem_walk.680861817 Jun 06 02:47:20 PM PDT 24 Jun 06 02:47:33 PM PDT 24 912743896 ps
T816 /workspace/coverage/default/14.sram_ctrl_partial_access.1521689429 Jun 06 02:45:12 PM PDT 24 Jun 06 02:45:24 PM PDT 24 716802017 ps
T817 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2221964564 Jun 06 02:48:04 PM PDT 24 Jun 06 02:48:06 PM PDT 24 80617274 ps
T818 /workspace/coverage/default/6.sram_ctrl_smoke.468130926 Jun 06 02:44:40 PM PDT 24 Jun 06 02:45:26 PM PDT 24 533671298 ps
T819 /workspace/coverage/default/5.sram_ctrl_partial_access.3504859337 Jun 06 02:44:41 PM PDT 24 Jun 06 02:46:07 PM PDT 24 2355195653 ps
T820 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2504763033 Jun 06 02:45:05 PM PDT 24 Jun 06 02:45:08 PM PDT 24 41145637 ps
T821 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3253083017 Jun 06 02:44:39 PM PDT 24 Jun 06 02:48:19 PM PDT 24 2307213119 ps
T822 /workspace/coverage/default/11.sram_ctrl_max_throughput.2530542268 Jun 06 02:45:07 PM PDT 24 Jun 06 02:45:17 PM PDT 24 67681950 ps
T823 /workspace/coverage/default/15.sram_ctrl_smoke.595386547 Jun 06 02:45:13 PM PDT 24 Jun 06 02:45:19 PM PDT 24 254178770 ps
T824 /workspace/coverage/default/37.sram_ctrl_ram_cfg.3977144227 Jun 06 02:47:04 PM PDT 24 Jun 06 02:47:06 PM PDT 24 42458837 ps
T825 /workspace/coverage/default/5.sram_ctrl_bijection.2858379598 Jun 06 02:44:38 PM PDT 24 Jun 06 02:45:29 PM PDT 24 8700810837 ps
T826 /workspace/coverage/default/11.sram_ctrl_partial_access.1981599829 Jun 06 02:44:57 PM PDT 24 Jun 06 02:45:19 PM PDT 24 371454709 ps
T827 /workspace/coverage/default/19.sram_ctrl_partial_access.3563559258 Jun 06 02:45:30 PM PDT 24 Jun 06 02:46:03 PM PDT 24 431138891 ps
T828 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.4200949933 Jun 06 02:46:10 PM PDT 24 Jun 06 03:04:46 PM PDT 24 7442343023 ps
T829 /workspace/coverage/default/22.sram_ctrl_partial_access.1231613530 Jun 06 02:45:55 PM PDT 24 Jun 06 02:46:06 PM PDT 24 2131138749 ps
T830 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.929064734 Jun 06 02:46:17 PM PDT 24 Jun 06 02:46:48 PM PDT 24 4527508557 ps
T831 /workspace/coverage/default/6.sram_ctrl_max_throughput.66480454 Jun 06 02:44:48 PM PDT 24 Jun 06 02:46:48 PM PDT 24 2059904414 ps
T832 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1137683063 Jun 06 02:47:32 PM PDT 24 Jun 06 02:51:48 PM PDT 24 2698137556 ps
T833 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.651763153 Jun 06 02:45:59 PM PDT 24 Jun 06 02:46:44 PM PDT 24 109561187 ps
T834 /workspace/coverage/default/47.sram_ctrl_ram_cfg.564242636 Jun 06 02:48:18 PM PDT 24 Jun 06 02:48:22 PM PDT 24 30898811 ps
T835 /workspace/coverage/default/13.sram_ctrl_regwen.2352506848 Jun 06 02:45:07 PM PDT 24 Jun 06 02:54:49 PM PDT 24 47068625190 ps
T836 /workspace/coverage/default/43.sram_ctrl_ram_cfg.693546600 Jun 06 02:48:02 PM PDT 24 Jun 06 02:48:05 PM PDT 24 49464431 ps
T837 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3304982839 Jun 06 02:48:13 PM PDT 24 Jun 06 02:48:45 PM PDT 24 191807223 ps
T838 /workspace/coverage/default/5.sram_ctrl_regwen.3575465973 Jun 06 02:44:43 PM PDT 24 Jun 06 02:45:04 PM PDT 24 4008723350 ps
T839 /workspace/coverage/default/11.sram_ctrl_ram_cfg.3449155424 Jun 06 02:45:03 PM PDT 24 Jun 06 02:45:05 PM PDT 24 44661347 ps
T840 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1865084724 Jun 06 02:44:48 PM PDT 24 Jun 06 02:57:11 PM PDT 24 10553453589 ps
T841 /workspace/coverage/default/16.sram_ctrl_mem_walk.262763230 Jun 06 02:45:22 PM PDT 24 Jun 06 02:45:35 PM PDT 24 1514704148 ps
T842 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1993100831 Jun 06 02:46:51 PM PDT 24 Jun 06 02:46:59 PM PDT 24 314973018 ps
T843 /workspace/coverage/default/37.sram_ctrl_max_throughput.3049473082 Jun 06 02:47:04 PM PDT 24 Jun 06 02:47:51 PM PDT 24 101853570 ps
T844 /workspace/coverage/default/28.sram_ctrl_mem_walk.4109628615 Jun 06 02:46:17 PM PDT 24 Jun 06 02:46:25 PM PDT 24 897368286 ps
T845 /workspace/coverage/default/27.sram_ctrl_max_throughput.2542936678 Jun 06 02:46:10 PM PDT 24 Jun 06 02:48:41 PM PDT 24 536140105 ps
T846 /workspace/coverage/default/35.sram_ctrl_smoke.1785427596 Jun 06 02:46:54 PM PDT 24 Jun 06 02:47:16 PM PDT 24 1043553226 ps
T847 /workspace/coverage/default/25.sram_ctrl_multiple_keys.193838337 Jun 06 02:46:08 PM PDT 24 Jun 06 02:50:32 PM PDT 24 124377012983 ps
T848 /workspace/coverage/default/42.sram_ctrl_bijection.3718812716 Jun 06 02:47:31 PM PDT 24 Jun 06 02:48:48 PM PDT 24 10195431919 ps
T849 /workspace/coverage/default/35.sram_ctrl_stress_all.22570927 Jun 06 02:46:53 PM PDT 24 Jun 06 03:21:10 PM PDT 24 41731775318 ps
T850 /workspace/coverage/default/2.sram_ctrl_alert_test.743273939 Jun 06 02:44:33 PM PDT 24 Jun 06 02:44:36 PM PDT 24 19203110 ps
T851 /workspace/coverage/default/39.sram_ctrl_executable.3140728219 Jun 06 02:47:18 PM PDT 24 Jun 06 03:11:24 PM PDT 24 6990016645 ps
T852 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2310754538 Jun 06 02:44:32 PM PDT 24 Jun 06 02:46:40 PM PDT 24 1306638223 ps
T853 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.444224776 Jun 06 02:45:30 PM PDT 24 Jun 06 03:00:12 PM PDT 24 3472935399 ps
T854 /workspace/coverage/default/46.sram_ctrl_executable.1580622172 Jun 06 02:48:14 PM PDT 24 Jun 06 02:55:42 PM PDT 24 26823813163 ps
T855 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1845429405 Jun 06 02:45:40 PM PDT 24 Jun 06 02:45:47 PM PDT 24 926631254 ps
T856 /workspace/coverage/default/40.sram_ctrl_regwen.4046555410 Jun 06 02:47:18 PM PDT 24 Jun 06 03:11:02 PM PDT 24 90090248914 ps
T857 /workspace/coverage/default/31.sram_ctrl_smoke.1946978681 Jun 06 02:46:26 PM PDT 24 Jun 06 02:46:39 PM PDT 24 860593908 ps
T858 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.825979126 Jun 06 02:45:13 PM PDT 24 Jun 06 02:45:19 PM PDT 24 238179422 ps
T859 /workspace/coverage/default/31.sram_ctrl_max_throughput.393810567 Jun 06 02:46:24 PM PDT 24 Jun 06 02:47:36 PM PDT 24 105502800 ps
T860 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3963353957 Jun 06 02:48:25 PM PDT 24 Jun 06 02:50:41 PM PDT 24 163146371 ps
T861 /workspace/coverage/default/9.sram_ctrl_max_throughput.1096180939 Jun 06 02:44:55 PM PDT 24 Jun 06 02:44:58 PM PDT 24 114784447 ps
T862 /workspace/coverage/default/28.sram_ctrl_max_throughput.317208294 Jun 06 02:46:08 PM PDT 24 Jun 06 02:46:52 PM PDT 24 93112529 ps
T863 /workspace/coverage/default/25.sram_ctrl_max_throughput.2392237578 Jun 06 02:46:00 PM PDT 24 Jun 06 02:47:28 PM PDT 24 463384145 ps
T864 /workspace/coverage/default/18.sram_ctrl_executable.533607117 Jun 06 02:45:25 PM PDT 24 Jun 06 02:47:25 PM PDT 24 10310630865 ps
T865 /workspace/coverage/default/21.sram_ctrl_partial_access.3920247881 Jun 06 02:45:39 PM PDT 24 Jun 06 02:45:54 PM PDT 24 2417821340 ps
T866 /workspace/coverage/default/21.sram_ctrl_smoke.3899867172 Jun 06 02:45:39 PM PDT 24 Jun 06 02:47:11 PM PDT 24 116505659 ps
T867 /workspace/coverage/default/25.sram_ctrl_alert_test.3853878975 Jun 06 02:46:01 PM PDT 24 Jun 06 02:46:04 PM PDT 24 12870636 ps
T868 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2305957363 Jun 06 02:44:30 PM PDT 24 Jun 06 02:44:36 PM PDT 24 249638263 ps
T869 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2577783023 Jun 06 02:44:48 PM PDT 24 Jun 06 02:45:05 PM PDT 24 319305801 ps
T870 /workspace/coverage/default/45.sram_ctrl_ram_cfg.3752940878 Jun 06 02:48:12 PM PDT 24 Jun 06 02:48:16 PM PDT 24 105600609 ps
T871 /workspace/coverage/default/4.sram_ctrl_stress_all.595953519 Jun 06 02:44:41 PM PDT 24 Jun 06 04:09:15 PM PDT 24 51308373840 ps
T872 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.593521819 Jun 06 02:47:27 PM PDT 24 Jun 06 02:48:41 PM PDT 24 251102342 ps
T873 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2532076175 Jun 06 02:47:19 PM PDT 24 Jun 06 02:48:00 PM PDT 24 4770699561 ps
T874 /workspace/coverage/default/48.sram_ctrl_regwen.2703483753 Jun 06 02:48:25 PM PDT 24 Jun 06 02:50:33 PM PDT 24 14551734591 ps
T875 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2993644786 Jun 06 02:48:18 PM PDT 24 Jun 06 02:48:22 PM PDT 24 100122933 ps
T876 /workspace/coverage/default/5.sram_ctrl_lc_escalation.184209272 Jun 06 02:44:40 PM PDT 24 Jun 06 02:44:45 PM PDT 24 402372901 ps
T877 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1392547060 Jun 06 02:45:07 PM PDT 24 Jun 06 03:11:13 PM PDT 24 3226812223 ps
T878 /workspace/coverage/default/22.sram_ctrl_mem_walk.3813310936 Jun 06 02:45:54 PM PDT 24 Jun 06 02:46:03 PM PDT 24 2530168918 ps
T879 /workspace/coverage/default/9.sram_ctrl_stress_all.664023532 Jun 06 02:44:55 PM PDT 24 Jun 06 03:44:43 PM PDT 24 46793631225 ps
T880 /workspace/coverage/default/20.sram_ctrl_smoke.3243473874 Jun 06 02:45:30 PM PDT 24 Jun 06 02:45:33 PM PDT 24 218410197 ps
T881 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2413142180 Jun 06 02:45:33 PM PDT 24 Jun 06 02:50:01 PM PDT 24 9869158204 ps
T882 /workspace/coverage/default/18.sram_ctrl_mem_walk.1022650902 Jun 06 02:45:35 PM PDT 24 Jun 06 02:45:43 PM PDT 24 235738656 ps
T883 /workspace/coverage/default/34.sram_ctrl_bijection.2187879916 Jun 06 02:46:49 PM PDT 24 Jun 06 02:47:27 PM PDT 24 4536035291 ps
T884 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2663911633 Jun 06 02:48:02 PM PDT 24 Jun 06 02:48:09 PM PDT 24 152273259 ps
T885 /workspace/coverage/default/12.sram_ctrl_smoke.4186537948 Jun 06 02:45:08 PM PDT 24 Jun 06 02:45:19 PM PDT 24 465683601 ps
T886 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3770643592 Jun 06 02:48:22 PM PDT 24 Jun 06 02:53:31 PM PDT 24 12961829282 ps
T887 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3923788058 Jun 06 02:48:06 PM PDT 24 Jun 06 02:48:14 PM PDT 24 274718810 ps
T888 /workspace/coverage/default/0.sram_ctrl_smoke.3159945758 Jun 06 02:44:20 PM PDT 24 Jun 06 02:44:37 PM PDT 24 468706109 ps
T889 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1164046969 Jun 06 02:45:32 PM PDT 24 Jun 06 03:03:08 PM PDT 24 26833021239 ps
T890 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.388775999 Jun 06 02:45:15 PM PDT 24 Jun 06 02:54:42 PM PDT 24 21132649839 ps
T891 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.765473261 Jun 06 02:44:56 PM PDT 24 Jun 06 02:48:15 PM PDT 24 4008691157 ps
T892 /workspace/coverage/default/9.sram_ctrl_ram_cfg.2076400124 Jun 06 02:44:56 PM PDT 24 Jun 06 02:44:58 PM PDT 24 387559659 ps
T893 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1047175628 Jun 06 02:44:25 PM PDT 24 Jun 06 02:46:12 PM PDT 24 306068125 ps
T894 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1881931832 Jun 06 02:47:29 PM PDT 24 Jun 06 02:47:31 PM PDT 24 117952334 ps
T895 /workspace/coverage/default/32.sram_ctrl_multiple_keys.657796849 Jun 06 02:46:37 PM PDT 24 Jun 06 02:55:57 PM PDT 24 8166932730 ps
T896 /workspace/coverage/default/29.sram_ctrl_partial_access.2274732872 Jun 06 02:46:16 PM PDT 24 Jun 06 02:48:21 PM PDT 24 645952911 ps
T897 /workspace/coverage/default/12.sram_ctrl_max_throughput.1600007741 Jun 06 02:45:06 PM PDT 24 Jun 06 02:45:31 PM PDT 24 324519416 ps
T898 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.4126653523 Jun 06 02:44:31 PM PDT 24 Jun 06 02:44:37 PM PDT 24 434162862 ps
T899 /workspace/coverage/default/44.sram_ctrl_stress_all.4005267579 Jun 06 02:48:09 PM PDT 24 Jun 06 03:38:15 PM PDT 24 68390810436 ps
T900 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2447955556 Jun 06 02:44:41 PM PDT 24 Jun 06 02:45:14 PM PDT 24 411766543 ps
T901 /workspace/coverage/default/35.sram_ctrl_executable.938223240 Jun 06 02:46:53 PM PDT 24 Jun 06 02:58:45 PM PDT 24 7565637618 ps
T902 /workspace/coverage/default/49.sram_ctrl_ram_cfg.2209348596 Jun 06 02:48:37 PM PDT 24 Jun 06 02:48:40 PM PDT 24 28666563 ps
T903 /workspace/coverage/default/14.sram_ctrl_mem_walk.815580007 Jun 06 02:45:12 PM PDT 24 Jun 06 02:45:19 PM PDT 24 274658275 ps
T904 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1359145128 Jun 06 02:45:24 PM PDT 24 Jun 06 02:46:35 PM PDT 24 1363162480 ps
T905 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3209040830 Jun 06 02:44:33 PM PDT 24 Jun 06 02:44:50 PM PDT 24 162016853 ps
T906 /workspace/coverage/default/29.sram_ctrl_max_throughput.355524690 Jun 06 02:46:15 PM PDT 24 Jun 06 02:47:00 PM PDT 24 198922960 ps
T907 /workspace/coverage/default/41.sram_ctrl_bijection.3492209289 Jun 06 02:47:28 PM PDT 24 Jun 06 02:48:47 PM PDT 24 16410435972 ps
T908 /workspace/coverage/default/19.sram_ctrl_mem_walk.4291467760 Jun 06 02:45:33 PM PDT 24 Jun 06 02:45:44 PM PDT 24 654371119 ps
T909 /workspace/coverage/default/29.sram_ctrl_stress_all.1665122793 Jun 06 02:46:17 PM PDT 24 Jun 06 03:24:57 PM PDT 24 103352830442 ps
T910 /workspace/coverage/default/12.sram_ctrl_bijection.3460174764 Jun 06 02:45:05 PM PDT 24 Jun 06 02:46:29 PM PDT 24 50885635286 ps
T911 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2396767934 Jun 06 02:45:05 PM PDT 24 Jun 06 02:45:13 PM PDT 24 686766667 ps
T912 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1724539111 Jun 06 02:46:15 PM PDT 24 Jun 06 02:51:39 PM PDT 24 5109624702 ps
T913 /workspace/coverage/default/42.sram_ctrl_stress_all.1972497830 Jun 06 02:48:02 PM PDT 24 Jun 06 03:49:17 PM PDT 24 157995733404 ps
T914 /workspace/coverage/default/30.sram_ctrl_smoke.868064786 Jun 06 02:46:18 PM PDT 24 Jun 06 02:46:31 PM PDT 24 660868144 ps
T915 /workspace/coverage/default/22.sram_ctrl_bijection.632619976 Jun 06 02:45:54 PM PDT 24 Jun 06 02:46:36 PM PDT 24 2377925156 ps
T916 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1121061093 Jun 06 02:45:42 PM PDT 24 Jun 06 02:55:33 PM PDT 24 1685031018 ps
T917 /workspace/coverage/default/36.sram_ctrl_stress_all.1269109146 Jun 06 02:47:03 PM PDT 24 Jun 06 03:26:21 PM PDT 24 24416649990 ps
T918 /workspace/coverage/default/8.sram_ctrl_alert_test.344670603 Jun 06 02:44:47 PM PDT 24 Jun 06 02:44:50 PM PDT 24 39466396 ps
T919 /workspace/coverage/default/29.sram_ctrl_regwen.3212348614 Jun 06 02:46:17 PM PDT 24 Jun 06 03:00:49 PM PDT 24 13562067828 ps
T920 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2635708439 Jun 06 02:45:22 PM PDT 24 Jun 06 02:45:30 PM PDT 24 321956557 ps
T921 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2229060273 Jun 06 02:46:11 PM PDT 24 Jun 06 02:48:58 PM PDT 24 25471808854 ps
T922 /workspace/coverage/default/27.sram_ctrl_lc_escalation.1836938404 Jun 06 02:46:13 PM PDT 24 Jun 06 02:46:23 PM PDT 24 1588927011 ps
T923 /workspace/coverage/default/20.sram_ctrl_lc_escalation.480270267 Jun 06 02:45:36 PM PDT 24 Jun 06 02:45:44 PM PDT 24 662722198 ps
T924 /workspace/coverage/default/18.sram_ctrl_max_throughput.2499517096 Jun 06 02:45:22 PM PDT 24 Jun 06 02:46:50 PM PDT 24 230828526 ps
T925 /workspace/coverage/default/5.sram_ctrl_multiple_keys.658435208 Jun 06 02:44:41 PM PDT 24 Jun 06 03:03:27 PM PDT 24 28679295826 ps
T926 /workspace/coverage/default/33.sram_ctrl_stress_all.3358980804 Jun 06 02:46:46 PM PDT 24 Jun 06 03:33:41 PM PDT 24 32821478307 ps
T927 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3864788606 Jun 06 02:44:46 PM PDT 24 Jun 06 02:45:32 PM PDT 24 1034150871 ps
T928 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.835530017 Jun 06 02:45:42 PM PDT 24 Jun 06 02:47:26 PM PDT 24 8319079156 ps
T929 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2922840892 Jun 06 02:45:30 PM PDT 24 Jun 06 02:48:28 PM PDT 24 503474368 ps
T930 /workspace/coverage/default/3.sram_ctrl_max_throughput.1680712577 Jun 06 02:44:36 PM PDT 24 Jun 06 02:44:56 PM PDT 24 78978425 ps
T931 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.313238200 Jun 06 02:47:11 PM PDT 24 Jun 06 02:54:01 PM PDT 24 15953860051 ps
T932 /workspace/coverage/default/4.sram_ctrl_mem_walk.4219801555 Jun 06 02:44:38 PM PDT 24 Jun 06 02:44:50 PM PDT 24 457863087 ps
T933 /workspace/coverage/default/35.sram_ctrl_lc_escalation.4288515238 Jun 06 02:46:52 PM PDT 24 Jun 06 02:46:56 PM PDT 24 528818503 ps
T934 /workspace/coverage/default/39.sram_ctrl_regwen.2033164993 Jun 06 02:47:20 PM PDT 24 Jun 06 02:52:29 PM PDT 24 18515720225 ps
T935 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2213441623 Jun 06 02:45:05 PM PDT 24 Jun 06 03:02:02 PM PDT 24 5656831024 ps
T936 /workspace/coverage/default/43.sram_ctrl_bijection.434468903 Jun 06 02:48:02 PM PDT 24 Jun 06 02:48:21 PM PDT 24 511122951 ps
T61 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1579973646 Jun 06 01:05:38 PM PDT 24 Jun 06 01:05:39 PM PDT 24 146755250 ps
T937 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3748430328 Jun 06 01:05:35 PM PDT 24 Jun 06 01:05:41 PM PDT 24 503200690 ps
T62 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3705687236 Jun 06 01:05:46 PM PDT 24 Jun 06 01:05:48 PM PDT 24 21149010 ps
T63 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3178103017 Jun 06 01:05:45 PM PDT 24 Jun 06 01:05:49 PM PDT 24 876112952 ps
T57 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.929934163 Jun 06 01:05:57 PM PDT 24 Jun 06 01:06:00 PM PDT 24 626687563 ps
T58 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4119348414 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:50 PM PDT 24 821044106 ps
T100 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3665326215 Jun 06 01:05:55 PM PDT 24 Jun 06 01:05:57 PM PDT 24 14857171 ps
T73 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.625073466 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:51 PM PDT 24 19449337 ps
T938 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.561093505 Jun 06 01:05:51 PM PDT 24 Jun 06 01:05:54 PM PDT 24 25441300 ps
T74 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.242369980 Jun 06 01:05:46 PM PDT 24 Jun 06 01:05:49 PM PDT 24 1226172454 ps
T939 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3161804802 Jun 06 01:05:54 PM PDT 24 Jun 06 01:05:56 PM PDT 24 32404964 ps
T940 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2631566392 Jun 06 01:05:50 PM PDT 24 Jun 06 01:05:53 PM PDT 24 43886243 ps
T941 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1887971352 Jun 06 01:05:35 PM PDT 24 Jun 06 01:05:38 PM PDT 24 127689641 ps
T59 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4008781334 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:37 PM PDT 24 350175001 ps
T942 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1692302584 Jun 06 01:05:38 PM PDT 24 Jun 06 01:05:41 PM PDT 24 47929719 ps
T123 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4130396759 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:37 PM PDT 24 335449520 ps
T943 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2294193501 Jun 06 01:05:48 PM PDT 24 Jun 06 01:05:50 PM PDT 24 93585283 ps
T101 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3881648813 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:37 PM PDT 24 835021669 ps
T75 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.374651357 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:36 PM PDT 24 22234146 ps
T76 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2357338284 Jun 06 01:05:59 PM PDT 24 Jun 06 01:06:01 PM PDT 24 38025935 ps
T944 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1687054394 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:53 PM PDT 24 118739602 ps
T945 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3479559440 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:49 PM PDT 24 148276079 ps
T102 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3095469018 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:42 PM PDT 24 58668648 ps
T77 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2046929729 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:51 PM PDT 24 42577857 ps
T78 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.122711420 Jun 06 01:05:53 PM PDT 24 Jun 06 01:05:55 PM PDT 24 18884610 ps
T946 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3627495678 Jun 06 01:05:35 PM PDT 24 Jun 06 01:05:37 PM PDT 24 57923017 ps
T947 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2634575061 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:53 PM PDT 24 228760367 ps
T79 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2927163053 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:52 PM PDT 24 408357060 ps
T80 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.726935049 Jun 06 01:05:42 PM PDT 24 Jun 06 01:05:44 PM PDT 24 111032744 ps
T120 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.628256216 Jun 06 01:05:44 PM PDT 24 Jun 06 01:05:47 PM PDT 24 126218195 ps
T124 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1238981451 Jun 06 01:05:41 PM PDT 24 Jun 06 01:05:45 PM PDT 24 319899778 ps
T948 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4130012325 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:42 PM PDT 24 17508020 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.95163261 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:42 PM PDT 24 19686586 ps
T950 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3419240775 Jun 06 01:05:35 PM PDT 24 Jun 06 01:05:39 PM PDT 24 242534950 ps
T121 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.927951187 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:53 PM PDT 24 783627487 ps
T951 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2273925842 Jun 06 01:05:46 PM PDT 24 Jun 06 01:05:52 PM PDT 24 410716767 ps
T952 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3173644944 Jun 06 01:05:42 PM PDT 24 Jun 06 01:05:44 PM PDT 24 20332250 ps
T953 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1251471649 Jun 06 01:05:44 PM PDT 24 Jun 06 01:05:45 PM PDT 24 17887929 ps
T954 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1223793470 Jun 06 01:05:41 PM PDT 24 Jun 06 01:05:43 PM PDT 24 11059584 ps
T81 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1552243436 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:53 PM PDT 24 279848448 ps
T955 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.862984746 Jun 06 01:05:48 PM PDT 24 Jun 06 01:05:54 PM PDT 24 142914373 ps
T956 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3145257660 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:49 PM PDT 24 20258849 ps
T957 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1834868348 Jun 06 01:05:39 PM PDT 24 Jun 06 01:05:41 PM PDT 24 139981881 ps
T82 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3831542687 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:52 PM PDT 24 201277499 ps
T958 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.72164048 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:52 PM PDT 24 232081485 ps
T125 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.456769910 Jun 06 01:05:48 PM PDT 24 Jun 06 01:05:51 PM PDT 24 122325849 ps
T83 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3046459751 Jun 06 01:05:54 PM PDT 24 Jun 06 01:05:56 PM PDT 24 16223604 ps
T84 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1342855761 Jun 06 01:05:58 PM PDT 24 Jun 06 01:06:02 PM PDT 24 480231653 ps
T959 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2424292601 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:43 PM PDT 24 46135062 ps
T960 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.244143586 Jun 06 01:05:38 PM PDT 24 Jun 06 01:05:43 PM PDT 24 104201272 ps
T961 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2742692522 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:36 PM PDT 24 17181198 ps
T962 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.540750548 Jun 06 01:05:58 PM PDT 24 Jun 06 01:06:01 PM PDT 24 35308594 ps
T963 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2618007017 Jun 06 01:05:37 PM PDT 24 Jun 06 01:05:39 PM PDT 24 16308831 ps
T964 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.197852223 Jun 06 01:05:52 PM PDT 24 Jun 06 01:05:54 PM PDT 24 105303473 ps
T965 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3494386537 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:51 PM PDT 24 85345261 ps
T966 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.257823490 Jun 06 01:05:51 PM PDT 24 Jun 06 01:05:56 PM PDT 24 1052157407 ps
T967 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.25450230 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:49 PM PDT 24 38776553 ps
T968 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1259874430 Jun 06 01:05:42 PM PDT 24 Jun 06 01:05:45 PM PDT 24 96141635 ps
T969 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.377593924 Jun 06 01:05:48 PM PDT 24 Jun 06 01:05:55 PM PDT 24 1123096273 ps
T85 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2403543816 Jun 06 01:05:51 PM PDT 24 Jun 06 01:05:54 PM PDT 24 57300585 ps
T970 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1086343820 Jun 06 01:05:35 PM PDT 24 Jun 06 01:05:38 PM PDT 24 31126468 ps
T971 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3918176724 Jun 06 01:05:51 PM PDT 24 Jun 06 01:05:53 PM PDT 24 212844934 ps
T972 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.824561847 Jun 06 01:05:39 PM PDT 24 Jun 06 01:05:42 PM PDT 24 343759219 ps
T86 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.301938425 Jun 06 01:05:49 PM PDT 24 Jun 06 01:05:51 PM PDT 24 32773439 ps
T973 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.325341841 Jun 06 01:05:50 PM PDT 24 Jun 06 01:05:52 PM PDT 24 36003329 ps
T98 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1178533415 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:36 PM PDT 24 16126138 ps
T974 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1073630389 Jun 06 01:05:45 PM PDT 24 Jun 06 01:05:47 PM PDT 24 37087670 ps
T126 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1833257261 Jun 06 01:05:38 PM PDT 24 Jun 06 01:05:41 PM PDT 24 306655127 ps
T92 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3016953508 Jun 06 01:05:36 PM PDT 24 Jun 06 01:05:38 PM PDT 24 21653893 ps
T93 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1374769428 Jun 06 01:05:52 PM PDT 24 Jun 06 01:05:56 PM PDT 24 495476375 ps
T975 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1744844833 Jun 06 01:05:58 PM PDT 24 Jun 06 01:06:01 PM PDT 24 383971583 ps
T976 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.732173696 Jun 06 01:05:45 PM PDT 24 Jun 06 01:05:47 PM PDT 24 44658417 ps
T94 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4040827127 Jun 06 01:05:51 PM PDT 24 Jun 06 01:05:55 PM PDT 24 472182162 ps
T977 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.213309749 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:43 PM PDT 24 46348604 ps
T978 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2037895233 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:42 PM PDT 24 43907139 ps
T979 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2278835788 Jun 06 01:05:41 PM PDT 24 Jun 06 01:05:46 PM PDT 24 412526953 ps
T980 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1630265818 Jun 06 01:05:39 PM PDT 24 Jun 06 01:05:41 PM PDT 24 96310761 ps
T981 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.586482801 Jun 06 01:05:45 PM PDT 24 Jun 06 01:05:48 PM PDT 24 46398837 ps
T982 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1197499110 Jun 06 01:05:43 PM PDT 24 Jun 06 01:05:45 PM PDT 24 13006513 ps
T983 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.221061584 Jun 06 01:05:59 PM PDT 24 Jun 06 01:06:01 PM PDT 24 26372877 ps
T984 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3296028842 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:44 PM PDT 24 58221765 ps
T985 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3917321781 Jun 06 01:05:43 PM PDT 24 Jun 06 01:05:48 PM PDT 24 108597863 ps
T986 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3812588249 Jun 06 01:05:32 PM PDT 24 Jun 06 01:05:38 PM PDT 24 123849437 ps
T131 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1333447157 Jun 06 01:05:50 PM PDT 24 Jun 06 01:05:54 PM PDT 24 336747653 ps
T95 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2521689910 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:38 PM PDT 24 409242030 ps
T987 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2675499564 Jun 06 01:05:44 PM PDT 24 Jun 06 01:05:46 PM PDT 24 14402329 ps
T988 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2973450905 Jun 06 01:05:32 PM PDT 24 Jun 06 01:05:35 PM PDT 24 33389391 ps
T96 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2837952398 Jun 06 01:05:40 PM PDT 24 Jun 06 01:05:45 PM PDT 24 407892220 ps
T99 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3210612205 Jun 06 01:05:41 PM PDT 24 Jun 06 01:05:44 PM PDT 24 215921259 ps
T989 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2924787049 Jun 06 01:05:52 PM PDT 24 Jun 06 01:05:54 PM PDT 24 12676885 ps
T990 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2170654102 Jun 06 01:05:47 PM PDT 24 Jun 06 01:05:52 PM PDT 24 976953220 ps
T132 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3341690062 Jun 06 01:05:45 PM PDT 24 Jun 06 01:05:48 PM PDT 24 242669537 ps
T991 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4270884445 Jun 06 01:05:50 PM PDT 24 Jun 06 01:05:52 PM PDT 24 22288792 ps
T992 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2931798677 Jun 06 01:05:57 PM PDT 24 Jun 06 01:05:59 PM PDT 24 133114446 ps
T993 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.937497570 Jun 06 01:05:50 PM PDT 24 Jun 06 01:05:53 PM PDT 24 180769802 ps
T994 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4184561911 Jun 06 01:05:42 PM PDT 24 Jun 06 01:05:45 PM PDT 24 323416225 ps
T995 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2642647436 Jun 06 01:05:41 PM PDT 24 Jun 06 01:05:47 PM PDT 24 489455694 ps
T996 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.361280177 Jun 06 01:05:58 PM PDT 24 Jun 06 01:06:00 PM PDT 24 21650336 ps
T997 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2631474686 Jun 06 01:05:45 PM PDT 24 Jun 06 01:05:48 PM PDT 24 147986383 ps
T137 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.467868232 Jun 06 01:05:45 PM PDT 24 Jun 06 01:05:48 PM PDT 24 240132234 ps
T998 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3405549602 Jun 06 01:05:50 PM PDT 24 Jun 06 01:05:52 PM PDT 24 18360911 ps
T999 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2888532084 Jun 06 01:05:38 PM PDT 24 Jun 06 01:05:40 PM PDT 24 50606935 ps
T1000 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2305140007 Jun 06 01:05:39 PM PDT 24 Jun 06 01:05:41 PM PDT 24 20244114 ps
T127 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4152425021 Jun 06 01:05:39 PM PDT 24 Jun 06 01:05:43 PM PDT 24 641570014 ps
T1001 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2857302492 Jun 06 01:05:50 PM PDT 24 Jun 06 01:05:55 PM PDT 24 184207547 ps
T1002 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3923731185 Jun 06 01:05:51 PM PDT 24 Jun 06 01:05:54 PM PDT 24 79667821 ps
T1003 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3968824757 Jun 06 01:05:44 PM PDT 24 Jun 06 01:05:50 PM PDT 24 1471926512 ps
T1004 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3727507249 Jun 06 01:05:31 PM PDT 24 Jun 06 01:05:34 PM PDT 24 85212711 ps
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