Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	139363878	1			T1	7184		T2	668988		T3	16332
instr_valid_dis	108770078	1			T1	7184		T2	668988		T3	16332
instr_en	24287448	1			T11	357130		T23	17464		T22	157954

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9145195	1			T11	61746		T22	76890		T16	114
sram_ifetch_valid_disable	109668643	1			T1	7184		T2	668988		T3	16332
sram_ifetch_enable	20550040	1			T11	128998		T23	67088		T22	289784

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	139363878	1			T1	7184		T2	668988		T3	16332
hw_debug_en_valid_off	110063600	1			T1	7184		T2	668988		T3	16332
hw_debug_en_on	19686616	1			T11	179040		T23	84552		T22	242366

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109668643	1			T1	7184		T2	668988		T3	16332
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97739146	1			T1	7184		T2	668988		T3	16332
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9603919	1			T11	166386		T23	17464		T22	56676
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3388453	1			T11	27714		T22	32822		T16	114
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1459827	1			T22	13122		T16	114		T31	5746
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1486118	1			T11	27714		T22	19700		T121	19188
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4195358	1			T11	6012		T22	44068		T17	310
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1479750	1			T22	26532		T118	36980		T122	27538
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2014140	1			T11	6012		T22	17536		T32	75312
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7145224	1			T11	119224		T23	17464		T22	144950
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3164784	1			T22	27840		T39	16908		T31	122160
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3166898	1			T11	119224		T23	17464		T22	41900

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10565903	1			T11	128998		T22	64042		T21	676
lc_exec_en	8346034	1			T11	53804		T23	67088		T22	53348
valid_exec_dis	105454466	1			T1	7184		T2	668988		T3	16332
invalid_exec_dis	29695235	1			T11	190744		T23	67088		T22	366674