Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	41992189	1			T1	1119		T2	304163		T3	6653
triple_byte_access	2469585	1			T1	25		T2	6223		T3	288
halfword_access	3710543	1			T1	40		T2	9063		T3	472
byte_access	4952698	1			T1	51		T2	12078		T3	591
zero_access	1246587	1			T1	13		T2	2967		T3	162

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27132250

1

T1

581

T2

167390

T3

4100

auto[1]

27239352

1

T1

667

T2

167104

T3

4066

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	20947434	1			T1	521		T2	152188		T3	3356
auto[0]	triple_byte_access	1232424	1			T1	8		T2	3133		T3	144
auto[0]	halfword_access	1851913	1			T1	22		T2	4560		T3	235
auto[0]	byte_access	2473534	1			T1	24		T2	6011		T3	292
auto[0]	zero_access	626945	1			T1	6		T2	1498		T3	73
auto[1]	word_access	21044755	1			T1	598		T2	151975		T3	3297
auto[1]	triple_byte_access	1237161	1			T1	17		T2	3090		T3	144
auto[1]	halfword_access	1858630	1			T1	18		T2	4503		T3	237
auto[1]	byte_access	2479164	1			T1	27		T2	6067		T3	299
auto[1]	zero_access	619642	1			T1	7		T2	1469		T3	89