| T792 |
/workspace/coverage/default/0.sram_ctrl_executable.66375901 |
|
|
Jun 09 02:03:42 PM PDT 24 |
Jun 09 02:22:06 PM PDT 24 |
19356593083 ps |
| T793 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2522610724 |
|
|
Jun 09 02:05:15 PM PDT 24 |
Jun 09 02:05:27 PM PDT 24 |
448021390 ps |
| T794 |
/workspace/coverage/default/18.sram_ctrl_smoke.2885617408 |
|
|
Jun 09 02:07:07 PM PDT 24 |
Jun 09 02:07:10 PM PDT 24 |
111717804 ps |
| T795 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.1870142020 |
|
|
Jun 09 02:04:53 PM PDT 24 |
Jun 09 02:04:59 PM PDT 24 |
2765738105 ps |
| T796 |
/workspace/coverage/default/33.sram_ctrl_partial_access.544992930 |
|
|
Jun 09 02:09:33 PM PDT 24 |
Jun 09 02:12:03 PM PDT 24 |
1319759848 ps |
| T797 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3094468480 |
|
|
Jun 09 02:10:56 PM PDT 24 |
Jun 09 02:22:42 PM PDT 24 |
11329497189 ps |
| T798 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2415515553 |
|
|
Jun 09 02:05:32 PM PDT 24 |
Jun 09 02:07:34 PM PDT 24 |
1743477056 ps |
| T799 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1828376747 |
|
|
Jun 09 02:09:14 PM PDT 24 |
Jun 09 02:12:59 PM PDT 24 |
9075433890 ps |
| T800 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3615280996 |
|
|
Jun 09 02:12:21 PM PDT 24 |
Jun 09 02:12:24 PM PDT 24 |
45328035 ps |
| T801 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.1076695986 |
|
|
Jun 09 02:07:26 PM PDT 24 |
Jun 09 02:19:51 PM PDT 24 |
48510083727 ps |
| T802 |
/workspace/coverage/default/29.sram_ctrl_partial_access.3478295329 |
|
|
Jun 09 02:08:51 PM PDT 24 |
Jun 09 02:08:56 PM PDT 24 |
61454622 ps |
| T803 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2578784342 |
|
|
Jun 09 02:08:49 PM PDT 24 |
Jun 09 02:52:25 PM PDT 24 |
57514682963 ps |
| T804 |
/workspace/coverage/default/4.sram_ctrl_partial_access.4134489191 |
|
|
Jun 09 02:04:27 PM PDT 24 |
Jun 09 02:05:04 PM PDT 24 |
159589677 ps |
| T805 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1930862270 |
|
|
Jun 09 02:04:04 PM PDT 24 |
Jun 09 02:25:18 PM PDT 24 |
85297086075 ps |
| T806 |
/workspace/coverage/default/12.sram_ctrl_smoke.3066852837 |
|
|
Jun 09 02:05:59 PM PDT 24 |
Jun 09 02:06:01 PM PDT 24 |
521623632 ps |
| T807 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1389779216 |
|
|
Jun 09 02:03:46 PM PDT 24 |
Jun 09 02:05:13 PM PDT 24 |
3793547454 ps |
| T808 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.3645316278 |
|
|
Jun 09 02:09:15 PM PDT 24 |
Jun 09 02:09:24 PM PDT 24 |
656713686 ps |
| T809 |
/workspace/coverage/default/37.sram_ctrl_stress_all.4006648216 |
|
|
Jun 09 02:10:18 PM PDT 24 |
Jun 09 02:28:09 PM PDT 24 |
21898979225 ps |
| T810 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1062855351 |
|
|
Jun 09 02:06:23 PM PDT 24 |
Jun 09 02:06:44 PM PDT 24 |
110456219 ps |
| T811 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2377061283 |
|
|
Jun 09 02:07:23 PM PDT 24 |
Jun 09 02:07:24 PM PDT 24 |
29268377 ps |
| T812 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1594709654 |
|
|
Jun 09 02:07:41 PM PDT 24 |
Jun 09 02:07:45 PM PDT 24 |
857386118 ps |
| T813 |
/workspace/coverage/default/21.sram_ctrl_stress_all.2106989956 |
|
|
Jun 09 02:07:45 PM PDT 24 |
Jun 09 02:36:17 PM PDT 24 |
29659545946 ps |
| T814 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3838886111 |
|
|
Jun 09 02:05:12 PM PDT 24 |
Jun 09 02:05:18 PM PDT 24 |
85271973 ps |
| T815 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3570633346 |
|
|
Jun 09 02:08:10 PM PDT 24 |
Jun 09 02:08:24 PM PDT 24 |
2692197477 ps |
| T816 |
/workspace/coverage/default/12.sram_ctrl_executable.1705823620 |
|
|
Jun 09 02:06:02 PM PDT 24 |
Jun 09 02:09:02 PM PDT 24 |
1039483110 ps |
| T817 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3741695990 |
|
|
Jun 09 02:10:50 PM PDT 24 |
Jun 09 02:15:40 PM PDT 24 |
9928313735 ps |
| T818 |
/workspace/coverage/default/49.sram_ctrl_smoke.1031127752 |
|
|
Jun 09 02:12:25 PM PDT 24 |
Jun 09 02:13:01 PM PDT 24 |
417057047 ps |
| T819 |
/workspace/coverage/default/5.sram_ctrl_smoke.2477907565 |
|
|
Jun 09 02:04:45 PM PDT 24 |
Jun 09 02:05:00 PM PDT 24 |
522353177 ps |
| T820 |
/workspace/coverage/default/39.sram_ctrl_bijection.56161547 |
|
|
Jun 09 02:10:33 PM PDT 24 |
Jun 09 02:11:08 PM PDT 24 |
7832741854 ps |
| T821 |
/workspace/coverage/default/14.sram_ctrl_regwen.3816407281 |
|
|
Jun 09 02:06:23 PM PDT 24 |
Jun 09 02:26:42 PM PDT 24 |
68796070240 ps |
| T822 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2131243089 |
|
|
Jun 09 02:11:20 PM PDT 24 |
Jun 09 02:11:28 PM PDT 24 |
1937345271 ps |
| T823 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.236443376 |
|
|
Jun 09 02:04:46 PM PDT 24 |
Jun 09 02:09:05 PM PDT 24 |
2596857714 ps |
| T824 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2091820659 |
|
|
Jun 09 02:05:14 PM PDT 24 |
Jun 09 02:35:54 PM PDT 24 |
175300806600 ps |
| T825 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1986137220 |
|
|
Jun 09 02:07:15 PM PDT 24 |
Jun 09 02:07:16 PM PDT 24 |
93716733 ps |
| T826 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.810452828 |
|
|
Jun 09 02:03:42 PM PDT 24 |
Jun 09 02:04:41 PM PDT 24 |
294103482 ps |
| T827 |
/workspace/coverage/default/35.sram_ctrl_smoke.2766229468 |
|
|
Jun 09 02:09:55 PM PDT 24 |
Jun 09 02:12:20 PM PDT 24 |
451999235 ps |
| T828 |
/workspace/coverage/default/11.sram_ctrl_executable.2080113252 |
|
|
Jun 09 02:05:56 PM PDT 24 |
Jun 09 02:14:18 PM PDT 24 |
4194203869 ps |
| T829 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2489479647 |
|
|
Jun 09 02:04:22 PM PDT 24 |
Jun 09 02:08:28 PM PDT 24 |
3066845913 ps |
| T830 |
/workspace/coverage/default/46.sram_ctrl_bijection.2144166747 |
|
|
Jun 09 02:11:50 PM PDT 24 |
Jun 09 02:12:39 PM PDT 24 |
2886796748 ps |
| T831 |
/workspace/coverage/default/20.sram_ctrl_smoke.3902234437 |
|
|
Jun 09 02:07:25 PM PDT 24 |
Jun 09 02:07:27 PM PDT 24 |
273482211 ps |
| T832 |
/workspace/coverage/default/41.sram_ctrl_alert_test.4142204591 |
|
|
Jun 09 02:11:04 PM PDT 24 |
Jun 09 02:11:05 PM PDT 24 |
11572507 ps |
| T833 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1906388341 |
|
|
Jun 09 02:05:01 PM PDT 24 |
Jun 09 02:05:02 PM PDT 24 |
46388798 ps |
| T834 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2533813249 |
|
|
Jun 09 02:06:09 PM PDT 24 |
Jun 09 02:27:25 PM PDT 24 |
25356147991 ps |
| T835 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2272078348 |
|
|
Jun 09 02:05:09 PM PDT 24 |
Jun 09 02:05:15 PM PDT 24 |
435746528 ps |
| T836 |
/workspace/coverage/default/32.sram_ctrl_regwen.2042941821 |
|
|
Jun 09 02:09:30 PM PDT 24 |
Jun 09 02:30:30 PM PDT 24 |
91621236477 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_smoke.2165554073 |
|
|
Jun 09 02:09:40 PM PDT 24 |
Jun 09 02:10:14 PM PDT 24 |
96322848 ps |
| T838 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1708978527 |
|
|
Jun 09 02:10:07 PM PDT 24 |
Jun 09 02:20:29 PM PDT 24 |
1698085749 ps |
| T839 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.1946387677 |
|
|
Jun 09 02:07:42 PM PDT 24 |
Jun 09 02:09:21 PM PDT 24 |
133426095 ps |
| T840 |
/workspace/coverage/default/36.sram_ctrl_executable.23315052 |
|
|
Jun 09 02:10:08 PM PDT 24 |
Jun 09 02:16:52 PM PDT 24 |
14171474629 ps |
| T841 |
/workspace/coverage/default/21.sram_ctrl_smoke.721771898 |
|
|
Jun 09 02:07:34 PM PDT 24 |
Jun 09 02:10:13 PM PDT 24 |
2401022571 ps |
| T842 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.1228138607 |
|
|
Jun 09 02:09:10 PM PDT 24 |
Jun 09 02:09:17 PM PDT 24 |
1376392164 ps |
| T843 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.252529579 |
|
|
Jun 09 02:07:46 PM PDT 24 |
Jun 09 02:37:25 PM PDT 24 |
20043358526 ps |
| T844 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1569707975 |
|
|
Jun 09 02:04:35 PM PDT 24 |
Jun 09 02:07:31 PM PDT 24 |
26499586267 ps |
| T845 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2912007201 |
|
|
Jun 09 02:03:54 PM PDT 24 |
Jun 09 02:03:55 PM PDT 24 |
42081392 ps |
| T846 |
/workspace/coverage/default/6.sram_ctrl_regwen.3773403096 |
|
|
Jun 09 02:05:01 PM PDT 24 |
Jun 09 02:29:41 PM PDT 24 |
19633639932 ps |
| T847 |
/workspace/coverage/default/40.sram_ctrl_executable.4225751682 |
|
|
Jun 09 02:10:46 PM PDT 24 |
Jun 09 02:25:27 PM PDT 24 |
67183855877 ps |
| T848 |
/workspace/coverage/default/28.sram_ctrl_smoke.1777414823 |
|
|
Jun 09 02:08:39 PM PDT 24 |
Jun 09 02:08:45 PM PDT 24 |
247930243 ps |
| T849 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.859754726 |
|
|
Jun 09 02:11:35 PM PDT 24 |
Jun 09 02:11:42 PM PDT 24 |
3693353599 ps |
| T850 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1745439245 |
|
|
Jun 09 02:05:50 PM PDT 24 |
Jun 09 02:10:56 PM PDT 24 |
3128705647 ps |
| T851 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1153946222 |
|
|
Jun 09 02:10:16 PM PDT 24 |
Jun 09 02:10:22 PM PDT 24 |
1487238455 ps |
| T852 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2494672579 |
|
|
Jun 09 02:07:14 PM PDT 24 |
Jun 09 02:07:15 PM PDT 24 |
50219202 ps |
| T853 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2291882917 |
|
|
Jun 09 02:09:09 PM PDT 24 |
Jun 09 02:09:19 PM PDT 24 |
544749604 ps |
| T854 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1274180558 |
|
|
Jun 09 02:07:35 PM PDT 24 |
Jun 09 02:07:36 PM PDT 24 |
46338834 ps |
| T855 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.2598921886 |
|
|
Jun 09 02:08:09 PM PDT 24 |
Jun 09 02:23:32 PM PDT 24 |
19092215935 ps |
| T856 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1173390594 |
|
|
Jun 09 02:07:59 PM PDT 24 |
Jun 09 02:08:00 PM PDT 24 |
48318539 ps |
| T857 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3277846677 |
|
|
Jun 09 02:07:21 PM PDT 24 |
Jun 09 02:08:51 PM PDT 24 |
152741825 ps |
| T858 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.880224096 |
|
|
Jun 09 02:07:11 PM PDT 24 |
Jun 09 02:07:12 PM PDT 24 |
83590233 ps |
| T859 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.25615539 |
|
|
Jun 09 02:09:27 PM PDT 24 |
Jun 09 02:09:28 PM PDT 24 |
104091811 ps |
| T860 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2355714341 |
|
|
Jun 09 02:05:12 PM PDT 24 |
Jun 09 02:05:16 PM PDT 24 |
67746203 ps |
| T861 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.760665541 |
|
|
Jun 09 02:04:50 PM PDT 24 |
Jun 09 02:04:53 PM PDT 24 |
112129064 ps |
| T862 |
/workspace/coverage/default/43.sram_ctrl_executable.3486161813 |
|
|
Jun 09 02:11:25 PM PDT 24 |
Jun 09 02:31:44 PM PDT 24 |
188226366638 ps |
| T863 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.830747541 |
|
|
Jun 09 02:08:33 PM PDT 24 |
Jun 09 02:08:34 PM PDT 24 |
76976934 ps |
| T864 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.4090350444 |
|
|
Jun 09 02:11:12 PM PDT 24 |
Jun 09 02:11:18 PM PDT 24 |
556299346 ps |
| T865 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2336063605 |
|
|
Jun 09 02:06:05 PM PDT 24 |
Jun 09 02:58:34 PM PDT 24 |
18523976980 ps |
| T866 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3670108253 |
|
|
Jun 09 02:10:14 PM PDT 24 |
Jun 09 02:13:59 PM PDT 24 |
4749357170 ps |
| T867 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.4007297846 |
|
|
Jun 09 02:12:28 PM PDT 24 |
Jun 09 02:13:16 PM PDT 24 |
1585740455 ps |
| T868 |
/workspace/coverage/default/14.sram_ctrl_bijection.1877610261 |
|
|
Jun 09 02:06:20 PM PDT 24 |
Jun 09 02:06:57 PM PDT 24 |
583577473 ps |
| T869 |
/workspace/coverage/default/36.sram_ctrl_smoke.1771288749 |
|
|
Jun 09 02:10:03 PM PDT 24 |
Jun 09 02:10:18 PM PDT 24 |
4544889962 ps |
| T870 |
/workspace/coverage/default/26.sram_ctrl_bijection.3590381495 |
|
|
Jun 09 02:08:17 PM PDT 24 |
Jun 09 02:09:14 PM PDT 24 |
2617153318 ps |
| T871 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.254177308 |
|
|
Jun 09 02:08:56 PM PDT 24 |
Jun 09 02:09:04 PM PDT 24 |
332602134 ps |
| T872 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2193447956 |
|
|
Jun 09 02:03:52 PM PDT 24 |
Jun 09 02:14:40 PM PDT 24 |
9035636285 ps |
| T873 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.73779034 |
|
|
Jun 09 02:11:37 PM PDT 24 |
Jun 09 02:11:44 PM PDT 24 |
810348273 ps |
| T874 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1175501100 |
|
|
Jun 09 02:09:51 PM PDT 24 |
Jun 09 02:16:30 PM PDT 24 |
22646951710 ps |
| T875 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1574110917 |
|
|
Jun 09 02:05:25 PM PDT 24 |
Jun 09 02:06:59 PM PDT 24 |
2907526596 ps |
| T876 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2171149440 |
|
|
Jun 09 02:08:56 PM PDT 24 |
Jun 09 02:08:57 PM PDT 24 |
29323016 ps |
| T877 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.1583522057 |
|
|
Jun 09 02:09:33 PM PDT 24 |
Jun 09 02:10:19 PM PDT 24 |
400305657 ps |
| T878 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1074646263 |
|
|
Jun 09 02:10:15 PM PDT 24 |
Jun 09 02:14:17 PM PDT 24 |
5334138691 ps |
| T879 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1911383787 |
|
|
Jun 09 02:08:26 PM PDT 24 |
Jun 09 02:08:30 PM PDT 24 |
207210860 ps |
| T880 |
/workspace/coverage/default/4.sram_ctrl_bijection.1983714937 |
|
|
Jun 09 02:04:27 PM PDT 24 |
Jun 09 02:04:54 PM PDT 24 |
779580575 ps |
| T881 |
/workspace/coverage/default/15.sram_ctrl_smoke.3546912157 |
|
|
Jun 09 02:06:28 PM PDT 24 |
Jun 09 02:08:10 PM PDT 24 |
2753463839 ps |
| T882 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3297304681 |
|
|
Jun 09 02:06:04 PM PDT 24 |
Jun 09 02:13:14 PM PDT 24 |
27144869214 ps |
| T883 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3256395043 |
|
|
Jun 09 02:12:35 PM PDT 24 |
Jun 09 02:12:38 PM PDT 24 |
105324901 ps |
| T884 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2324103504 |
|
|
Jun 09 02:07:16 PM PDT 24 |
Jun 09 02:07:21 PM PDT 24 |
165882918 ps |
| T885 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.724518999 |
|
|
Jun 09 02:05:06 PM PDT 24 |
Jun 09 02:07:49 PM PDT 24 |
4262268609 ps |
| T886 |
/workspace/coverage/default/10.sram_ctrl_smoke.943313902 |
|
|
Jun 09 02:05:38 PM PDT 24 |
Jun 09 02:05:47 PM PDT 24 |
410841116 ps |
| T887 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1654038873 |
|
|
Jun 09 02:05:14 PM PDT 24 |
Jun 09 02:05:15 PM PDT 24 |
32190989 ps |
| T888 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2875153435 |
|
|
Jun 09 02:08:09 PM PDT 24 |
Jun 09 02:08:10 PM PDT 24 |
37163225 ps |
| T889 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1339643708 |
|
|
Jun 09 02:05:55 PM PDT 24 |
Jun 09 02:06:00 PM PDT 24 |
388103924 ps |
| T890 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2756793171 |
|
|
Jun 09 02:08:22 PM PDT 24 |
Jun 09 02:08:24 PM PDT 24 |
144470614 ps |
| T891 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.999804223 |
|
|
Jun 09 02:09:08 PM PDT 24 |
Jun 09 02:14:44 PM PDT 24 |
2711659974 ps |
| T892 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.889554520 |
|
|
Jun 09 02:07:30 PM PDT 24 |
Jun 09 02:07:45 PM PDT 24 |
80754885 ps |
| T893 |
/workspace/coverage/default/10.sram_ctrl_bijection.3473557086 |
|
|
Jun 09 02:05:36 PM PDT 24 |
Jun 09 02:06:20 PM PDT 24 |
2653247131 ps |
| T894 |
/workspace/coverage/default/2.sram_ctrl_executable.2968895461 |
|
|
Jun 09 02:04:15 PM PDT 24 |
Jun 09 02:15:10 PM PDT 24 |
15675833737 ps |
| T895 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.987670254 |
|
|
Jun 09 02:10:00 PM PDT 24 |
Jun 09 02:15:03 PM PDT 24 |
2992426026 ps |
| T896 |
/workspace/coverage/default/49.sram_ctrl_partial_access.4228980072 |
|
|
Jun 09 02:12:27 PM PDT 24 |
Jun 09 02:12:39 PM PDT 24 |
342435252 ps |
| T897 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2564670520 |
|
|
Jun 09 02:04:27 PM PDT 24 |
Jun 09 02:04:32 PM PDT 24 |
239623516 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1519039175 |
|
|
Jun 09 02:08:22 PM PDT 24 |
Jun 09 02:08:23 PM PDT 24 |
46512474 ps |
| T899 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3317245064 |
|
|
Jun 09 02:10:07 PM PDT 24 |
Jun 09 02:10:16 PM PDT 24 |
137476120 ps |
| T900 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2417345320 |
|
|
Jun 09 02:08:42 PM PDT 24 |
Jun 09 02:11:15 PM PDT 24 |
817033518 ps |
| T901 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2653078436 |
|
|
Jun 09 02:03:51 PM PDT 24 |
Jun 09 02:13:35 PM PDT 24 |
22734337562 ps |
| T902 |
/workspace/coverage/default/4.sram_ctrl_smoke.3622893562 |
|
|
Jun 09 02:04:27 PM PDT 24 |
Jun 09 02:04:28 PM PDT 24 |
39639074 ps |
| T903 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2624366283 |
|
|
Jun 09 02:12:39 PM PDT 24 |
Jun 09 02:12:44 PM PDT 24 |
231484410 ps |
| T904 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.108605423 |
|
|
Jun 09 02:05:15 PM PDT 24 |
Jun 09 02:16:22 PM PDT 24 |
35546063335 ps |
| T905 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2281949543 |
|
|
Jun 09 02:09:54 PM PDT 24 |
Jun 09 02:10:12 PM PDT 24 |
329024671 ps |
| T906 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2989920433 |
|
|
Jun 09 02:06:17 PM PDT 24 |
Jun 09 02:06:18 PM PDT 24 |
13695564 ps |
| T907 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2358690684 |
|
|
Jun 09 02:08:23 PM PDT 24 |
Jun 09 02:08:53 PM PDT 24 |
357525355 ps |
| T908 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1725912187 |
|
|
Jun 09 02:05:01 PM PDT 24 |
Jun 09 02:05:07 PM PDT 24 |
417087939 ps |
| T909 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2998265596 |
|
|
Jun 09 02:04:07 PM PDT 24 |
Jun 09 02:21:25 PM PDT 24 |
3605814608 ps |
| T910 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3452164890 |
|
|
Jun 09 02:09:38 PM PDT 24 |
Jun 09 02:09:41 PM PDT 24 |
229384584 ps |
| T911 |
/workspace/coverage/default/19.sram_ctrl_partial_access.3310168086 |
|
|
Jun 09 02:07:23 PM PDT 24 |
Jun 09 02:07:35 PM PDT 24 |
281348822 ps |
| T912 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1454106251 |
|
|
Jun 09 02:07:41 PM PDT 24 |
Jun 09 02:17:37 PM PDT 24 |
7142363359 ps |
| T913 |
/workspace/coverage/default/15.sram_ctrl_alert_test.3283495321 |
|
|
Jun 09 02:06:38 PM PDT 24 |
Jun 09 02:06:39 PM PDT 24 |
13107203 ps |
| T914 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1262763277 |
|
|
Jun 09 02:05:43 PM PDT 24 |
Jun 09 02:07:24 PM PDT 24 |
541609163 ps |
| T915 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2184313832 |
|
|
Jun 09 02:06:38 PM PDT 24 |
Jun 09 02:06:45 PM PDT 24 |
667489084 ps |
| T916 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3075243118 |
|
|
Jun 09 02:06:37 PM PDT 24 |
Jun 09 02:06:40 PM PDT 24 |
507998601 ps |
| T917 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1424474784 |
|
|
Jun 09 02:07:06 PM PDT 24 |
Jun 09 02:07:21 PM PDT 24 |
842825824 ps |
| T918 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3705498097 |
|
|
Jun 09 02:06:27 PM PDT 24 |
Jun 09 02:19:41 PM PDT 24 |
19342054503 ps |
| T919 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3301255620 |
|
|
Jun 09 02:11:23 PM PDT 24 |
Jun 09 02:11:25 PM PDT 24 |
136133347 ps |
| T920 |
/workspace/coverage/default/42.sram_ctrl_bijection.2861948813 |
|
|
Jun 09 02:11:02 PM PDT 24 |
Jun 09 02:11:49 PM PDT 24 |
5555978745 ps |
| T921 |
/workspace/coverage/default/19.sram_ctrl_executable.1833003532 |
|
|
Jun 09 02:07:22 PM PDT 24 |
Jun 09 02:19:23 PM PDT 24 |
21919827514 ps |
| T922 |
/workspace/coverage/default/3.sram_ctrl_alert_test.1411262456 |
|
|
Jun 09 02:04:28 PM PDT 24 |
Jun 09 02:04:29 PM PDT 24 |
26443307 ps |
| T923 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2171961161 |
|
|
Jun 09 02:07:43 PM PDT 24 |
Jun 09 02:08:55 PM PDT 24 |
1861773815 ps |
| T924 |
/workspace/coverage/default/7.sram_ctrl_bijection.109453537 |
|
|
Jun 09 02:05:05 PM PDT 24 |
Jun 09 02:05:23 PM PDT 24 |
275024883 ps |
| T925 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.504832568 |
|
|
Jun 09 02:04:55 PM PDT 24 |
Jun 09 02:15:58 PM PDT 24 |
10052773681 ps |
| T926 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.629388580 |
|
|
Jun 09 02:11:17 PM PDT 24 |
Jun 09 02:21:10 PM PDT 24 |
5131088287 ps |
| T927 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2159257944 |
|
|
Jun 09 02:06:14 PM PDT 24 |
Jun 09 02:06:16 PM PDT 24 |
41931999 ps |
| T928 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1516886355 |
|
|
Jun 09 02:06:43 PM PDT 24 |
Jun 09 02:13:59 PM PDT 24 |
32734918314 ps |
| T929 |
/workspace/coverage/default/4.sram_ctrl_regwen.3823384576 |
|
|
Jun 09 02:04:45 PM PDT 24 |
Jun 09 02:13:53 PM PDT 24 |
1283352739 ps |
| T930 |
/workspace/coverage/default/26.sram_ctrl_stress_all.3860240768 |
|
|
Jun 09 02:08:29 PM PDT 24 |
Jun 09 02:55:02 PM PDT 24 |
58351179118 ps |
| T55 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1190631086 |
|
|
Jun 09 12:27:38 PM PDT 24 |
Jun 09 12:27:39 PM PDT 24 |
72878789 ps |
| T52 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2905253414 |
|
|
Jun 09 12:27:25 PM PDT 24 |
Jun 09 12:27:27 PM PDT 24 |
569215885 ps |
| T931 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2177144759 |
|
|
Jun 09 12:27:43 PM PDT 24 |
Jun 09 12:27:45 PM PDT 24 |
103145206 ps |
| T56 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.897193591 |
|
|
Jun 09 12:27:13 PM PDT 24 |
Jun 09 12:27:16 PM PDT 24 |
390334422 ps |
| T61 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1534443834 |
|
|
Jun 09 12:27:44 PM PDT 24 |
Jun 09 12:27:48 PM PDT 24 |
415861056 ps |
| T932 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3070507580 |
|
|
Jun 09 12:27:04 PM PDT 24 |
Jun 09 12:27:07 PM PDT 24 |
24759014 ps |
| T53 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1406134221 |
|
|
Jun 09 12:27:42 PM PDT 24 |
Jun 09 12:27:44 PM PDT 24 |
162504946 ps |
| T92 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3498230829 |
|
|
Jun 09 12:27:33 PM PDT 24 |
Jun 09 12:27:35 PM PDT 24 |
44865342 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2744677778 |
|
|
Jun 09 12:27:07 PM PDT 24 |
Jun 09 12:27:10 PM PDT 24 |
56420555 ps |
| T63 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1104549035 |
|
|
Jun 09 12:28:31 PM PDT 24 |
Jun 09 12:28:35 PM PDT 24 |
1601502981 ps |
| T54 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.916279398 |
|
|
Jun 09 12:27:33 PM PDT 24 |
Jun 09 12:27:35 PM PDT 24 |
209161409 ps |
| T933 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4201194568 |
|
|
Jun 09 12:27:14 PM PDT 24 |
Jun 09 12:27:16 PM PDT 24 |
47057049 ps |
| T934 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3218661769 |
|
|
Jun 09 12:27:41 PM PDT 24 |
Jun 09 12:27:46 PM PDT 24 |
266444509 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2226689502 |
|
|
Jun 09 12:27:01 PM PDT 24 |
Jun 09 12:27:02 PM PDT 24 |
136820488 ps |
| T935 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1784853766 |
|
|
Jun 09 12:27:31 PM PDT 24 |
Jun 09 12:27:32 PM PDT 24 |
46769826 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.818834241 |
|
|
Jun 09 12:27:07 PM PDT 24 |
Jun 09 12:27:10 PM PDT 24 |
48007203 ps |
| T65 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1782961353 |
|
|
Jun 09 12:27:03 PM PDT 24 |
Jun 09 12:27:07 PM PDT 24 |
660336495 ps |
| T66 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1731623596 |
|
|
Jun 09 12:27:41 PM PDT 24 |
Jun 09 12:27:42 PM PDT 24 |
44083687 ps |
| T93 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.151440514 |
|
|
Jun 09 12:27:20 PM PDT 24 |
Jun 09 12:27:26 PM PDT 24 |
7679260602 ps |
| T67 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2734940136 |
|
|
Jun 09 12:27:43 PM PDT 24 |
Jun 09 12:27:47 PM PDT 24 |
1495543159 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.754617490 |
|
|
Jun 09 12:27:37 PM PDT 24 |
Jun 09 12:27:38 PM PDT 24 |
32703513 ps |
| T936 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.816079110 |
|
|
Jun 09 12:27:47 PM PDT 24 |
Jun 09 12:27:50 PM PDT 24 |
297538989 ps |
| T937 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1887189491 |
|
|
Jun 09 12:27:24 PM PDT 24 |
Jun 09 12:27:26 PM PDT 24 |
92505691 ps |
| T938 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.170988991 |
|
|
Jun 09 12:27:42 PM PDT 24 |
Jun 09 12:27:43 PM PDT 24 |
16745201 ps |
| T939 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1317333484 |
|
|
Jun 09 12:27:10 PM PDT 24 |
Jun 09 12:27:12 PM PDT 24 |
19718411 ps |
| T940 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1866531804 |
|
|
Jun 09 12:27:10 PM PDT 24 |
Jun 09 12:27:14 PM PDT 24 |
78592089 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3263995997 |
|
|
Jun 09 12:27:06 PM PDT 24 |
Jun 09 12:27:11 PM PDT 24 |
674463047 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2279509216 |
|
|
Jun 09 12:27:03 PM PDT 24 |
Jun 09 12:27:05 PM PDT 24 |
13588051 ps |
| T941 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3913666489 |
|
|
Jun 09 12:27:15 PM PDT 24 |
Jun 09 12:27:18 PM PDT 24 |
66842103 ps |
| T74 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3324893524 |
|
|
Jun 09 12:27:07 PM PDT 24 |
Jun 09 12:27:12 PM PDT 24 |
882746032 ps |
| T942 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.25828714 |
|
|
Jun 09 12:27:31 PM PDT 24 |
Jun 09 12:27:34 PM PDT 24 |
86601734 ps |
| T107 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1189947407 |
|
|
Jun 09 12:27:49 PM PDT 24 |
Jun 09 12:27:52 PM PDT 24 |
207797745 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3950999402 |
|
|
Jun 09 12:27:08 PM PDT 24 |
Jun 09 12:27:11 PM PDT 24 |
33742486 ps |
| T944 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1342742498 |
|
|
Jun 09 12:27:30 PM PDT 24 |
Jun 09 12:27:33 PM PDT 24 |
241317837 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1770325962 |
|
|
Jun 09 12:27:36 PM PDT 24 |
Jun 09 12:27:38 PM PDT 24 |
48888479 ps |
| T85 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2412690421 |
|
|
Jun 09 12:28:46 PM PDT 24 |
Jun 09 12:28:47 PM PDT 24 |
46951924 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1731090703 |
|
|
Jun 09 12:27:00 PM PDT 24 |
Jun 09 12:27:01 PM PDT 24 |
66036511 ps |
| T947 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2734244002 |
|
|
Jun 09 12:27:12 PM PDT 24 |
Jun 09 12:27:14 PM PDT 24 |
28768310 ps |
| T948 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2065292684 |
|
|
Jun 09 12:27:51 PM PDT 24 |
Jun 09 12:27:53 PM PDT 24 |
90917990 ps |
| T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4005699943 |
|
|
Jun 09 12:27:36 PM PDT 24 |
Jun 09 12:27:37 PM PDT 24 |
30354541 ps |
| T949 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.696896538 |
|
|
Jun 09 12:27:07 PM PDT 24 |
Jun 09 12:27:10 PM PDT 24 |
17676821 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.236732025 |
|
|
Jun 09 12:27:21 PM PDT 24 |
Jun 09 12:27:23 PM PDT 24 |
207421944 ps |
| T950 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2238667134 |
|
|
Jun 09 12:28:31 PM PDT 24 |
Jun 09 12:28:36 PM PDT 24 |
129732675 ps |
| T951 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3385610994 |
|
|
Jun 09 12:27:24 PM PDT 24 |
Jun 09 12:27:26 PM PDT 24 |
142194552 ps |
| T952 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.255086770 |
|
|
Jun 09 12:27:43 PM PDT 24 |
Jun 09 12:27:44 PM PDT 24 |
35315041 ps |
| T76 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.660163682 |
|
|
Jun 09 12:27:28 PM PDT 24 |
Jun 09 12:27:29 PM PDT 24 |
19875184 ps |
| T109 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.665147209 |
|
|
Jun 09 12:27:41 PM PDT 24 |
Jun 09 12:27:43 PM PDT 24 |
128624939 ps |
| T77 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3177609002 |
|
|
Jun 09 12:27:35 PM PDT 24 |
Jun 09 12:27:38 PM PDT 24 |
790236977 ps |
| T111 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4067846992 |
|
|
Jun 09 12:27:25 PM PDT 24 |
Jun 09 12:27:27 PM PDT 24 |
175873010 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4151040566 |
|
|
Jun 09 12:28:07 PM PDT 24 |
Jun 09 12:28:08 PM PDT 24 |
26718616 ps |
| T954 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3492213479 |
|
|
Jun 09 12:27:05 PM PDT 24 |
Jun 09 12:27:08 PM PDT 24 |
34903982 ps |
| T91 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2839153901 |
|
|
Jun 09 12:27:08 PM PDT 24 |
Jun 09 12:27:10 PM PDT 24 |
38219947 ps |
| T955 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3136634219 |
|
|
Jun 09 12:27:38 PM PDT 24 |
Jun 09 12:27:40 PM PDT 24 |
42419872 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2159013306 |
|
|
Jun 09 12:27:41 PM PDT 24 |
Jun 09 12:27:43 PM PDT 24 |
14514508 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3529463272 |
|
|
Jun 09 12:27:36 PM PDT 24 |
Jun 09 12:27:39 PM PDT 24 |
60731567 ps |
| T87 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1415343698 |
|
|
Jun 09 12:27:35 PM PDT 24 |
Jun 09 12:27:39 PM PDT 24 |
815869816 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.617845055 |
|
|
Jun 09 12:27:43 PM PDT 24 |
Jun 09 12:27:46 PM PDT 24 |
121986429 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2676129399 |
|
|
Jun 09 12:27:41 PM PDT 24 |
Jun 09 12:27:44 PM PDT 24 |
325042775 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.336808514 |
|
|
Jun 09 12:27:49 PM PDT 24 |
Jun 09 12:27:51 PM PDT 24 |
214022253 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4134411406 |
|
|
Jun 09 12:27:24 PM PDT 24 |
Jun 09 12:27:25 PM PDT 24 |
37469049 ps |
| T959 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.414164380 |
|
|
Jun 09 12:27:50 PM PDT 24 |
Jun 09 12:27:51 PM PDT 24 |
86508543 ps |
| T90 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1123708247 |
|
|
Jun 09 12:28:46 PM PDT 24 |
Jun 09 12:28:47 PM PDT 24 |
45382917 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3696041668 |
|
|
Jun 09 12:28:31 PM PDT 24 |
Jun 09 12:28:33 PM PDT 24 |
280181514 ps |
| T106 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.105576593 |
|
|
Jun 09 12:27:10 PM PDT 24 |
Jun 09 12:27:13 PM PDT 24 |
209552107 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2530851834 |
|
|
Jun 09 12:27:02 PM PDT 24 |
Jun 09 12:27:04 PM PDT 24 |
57797819 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1268896609 |
|
|
Jun 09 12:27:44 PM PDT 24 |
Jun 09 12:27:45 PM PDT 24 |
17825569 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.904531892 |
|
|
Jun 09 12:27:45 PM PDT 24 |
Jun 09 12:27:45 PM PDT 24 |
25459916 ps |
| T964 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1411004913 |
|
|
Jun 09 12:27:48 PM PDT 24 |
Jun 09 12:27:52 PM PDT 24 |
434168138 ps |
| T112 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3582710059 |
|
|
Jun 09 12:27:52 PM PDT 24 |
Jun 09 12:27:55 PM PDT 24 |
275779754 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1434721433 |
|
|
Jun 09 12:27:21 PM PDT 24 |
Jun 09 12:27:25 PM PDT 24 |
500982653 ps |
| T966 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3786702735 |
|
|
Jun 09 12:28:32 PM PDT 24 |
Jun 09 12:28:35 PM PDT 24 |
281215988 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3684703797 |
|
|
Jun 09 12:27:08 PM PDT 24 |
Jun 09 12:27:11 PM PDT 24 |
29671949 ps |
| T123 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2389976045 |
|
|
Jun 09 12:27:34 PM PDT 24 |
Jun 09 12:27:38 PM PDT 24 |
803082503 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2639422194 |
|
|
Jun 09 12:27:22 PM PDT 24 |
Jun 09 12:27:23 PM PDT 24 |
16024521 ps |
| T969 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2090512346 |
|
|
Jun 09 12:27:09 PM PDT 24 |
Jun 09 12:27:14 PM PDT 24 |
100690768 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2465851435 |
|
|
Jun 09 12:27:44 PM PDT 24 |
Jun 09 12:27:46 PM PDT 24 |
29634491 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3610331909 |
|
|
Jun 09 12:27:30 PM PDT 24 |
Jun 09 12:27:31 PM PDT 24 |
16181324 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2039178086 |
|
|
Jun 09 12:28:32 PM PDT 24 |
Jun 09 12:28:33 PM PDT 24 |
206946747 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3026493157 |
|
|
Jun 09 12:27:50 PM PDT 24 |
Jun 09 12:27:52 PM PDT 24 |
66800498 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1137417826 |
|
|
Jun 09 12:27:11 PM PDT 24 |
Jun 09 12:27:13 PM PDT 24 |
21879875 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4168703119 |
|
|
Jun 09 12:27:46 PM PDT 24 |
Jun 09 12:27:48 PM PDT 24 |
35253886 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.411358117 |
|
|
Jun 09 12:27:34 PM PDT 24 |
Jun 09 12:27:37 PM PDT 24 |
784934047 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3269044123 |
|
|
Jun 09 12:27:42 PM PDT 24 |
Jun 09 12:27:43 PM PDT 24 |
110044028 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.632004521 |
|
|
Jun 09 12:27:07 PM PDT 24 |
Jun 09 12:27:13 PM PDT 24 |
121628481 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1495903352 |
|
|
Jun 09 12:27:02 PM PDT 24 |
Jun 09 12:27:04 PM PDT 24 |
68847555 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.289098966 |
|
|
Jun 09 12:27:13 PM PDT 24 |
Jun 09 12:27:14 PM PDT 24 |
86748629 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2703433910 |
|
|
Jun 09 12:28:31 PM PDT 24 |
Jun 09 12:28:34 PM PDT 24 |
201686459 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.350975976 |
|
|
Jun 09 12:27:40 PM PDT 24 |
Jun 09 12:27:42 PM PDT 24 |
261477148 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2588373534 |
|
|
Jun 09 12:27:05 PM PDT 24 |
Jun 09 12:27:11 PM PDT 24 |
232489121 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1043203347 |
|
|
Jun 09 12:27:38 PM PDT 24 |
Jun 09 12:27:42 PM PDT 24 |
502408521 ps |
| T985 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.347265747 |
|
|
Jun 09 12:27:43 PM PDT 24 |
Jun 09 12:27:44 PM PDT 24 |
54208522 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3466713716 |
|
|
Jun 09 12:27:06 PM PDT 24 |
Jun 09 12:27:10 PM PDT 24 |
93970105 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4181821998 |
|
|
Jun 09 12:27:00 PM PDT 24 |
Jun 09 12:27:09 PM PDT 24 |
1510214014 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2127866498 |
|
|
Jun 09 12:27:04 PM PDT 24 |
Jun 09 12:27:16 PM PDT 24 |
138308338 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.167894341 |
|
|
Jun 09 12:27:05 PM PDT 24 |
Jun 09 12:27:08 PM PDT 24 |
17523552 ps |
| T990 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3172837411 |
|
|
Jun 09 12:27:41 PM PDT 24 |
Jun 09 12:27:44 PM PDT 24 |
286118213 ps |
| T991 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1171311807 |
|
|
Jun 09 12:27:10 PM PDT 24 |
Jun 09 12:27:14 PM PDT 24 |
87866074 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.737274114 |
|
|
Jun 09 12:28:46 PM PDT 24 |
Jun 09 12:28:47 PM PDT 24 |
42675656 ps |
| T993 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3375776245 |
|
|
Jun 09 12:27:06 PM PDT 24 |
Jun 09 12:27:11 PM PDT 24 |
154802231 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4108293874 |
|
|
Jun 09 12:27:46 PM PDT 24 |
Jun 09 12:27:48 PM PDT 24 |
249672540 ps |
| T114 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2596774071 |
|
|
Jun 09 12:27:30 PM PDT 24 |
Jun 09 12:27:32 PM PDT 24 |
192424304 ps |
| T995 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.37870391 |
|
|
Jun 09 12:27:50 PM PDT 24 |
Jun 09 12:27:54 PM PDT 24 |
150319317 ps |
| T115 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.638179376 |
|
|
Jun 09 12:28:31 PM PDT 24 |
Jun 09 12:28:34 PM PDT 24 |
175646907 ps |
| T110 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3832915801 |
|
|
Jun 09 12:27:24 PM PDT 24 |
Jun 09 12:27:27 PM PDT 24 |
375102982 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3412073763 |
|
|
Jun 09 12:27:04 PM PDT 24 |
Jun 09 12:27:07 PM PDT 24 |
59960547 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.756647646 |
|
|
Jun 09 12:27:08 PM PDT 24 |
Jun 09 12:27:11 PM PDT 24 |
60824308 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4098970850 |
|
|
Jun 09 12:27:17 PM PDT 24 |
Jun 09 12:27:18 PM PDT 24 |
17316801 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2606801808 |
|
|
Jun 09 12:27:02 PM PDT 24 |
Jun 09 12:27:03 PM PDT 24 |
43402664 ps |
| T1000 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.43768853 |
|
|
Jun 09 12:27:28 PM PDT 24 |
Jun 09 12:27:30 PM PDT 24 |
166864383 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4170746995 |
|
|
Jun 09 12:27:34 PM PDT 24 |
Jun 09 12:27:36 PM PDT 24 |
219342884 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3951867993 |
|
|
Jun 09 12:27:11 PM PDT 24 |
Jun 09 12:27:16 PM PDT 24 |
369645801 ps |