Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147128406	1			T1	330384		T2	7024		T3	1472
instr_valid_dis	114556742	1			T1	330384		T2	7024		T3	1472
instr_en	19769823	1			T5	19892		T24	171066		T47	598874

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9972381	1			T28	73326		T24	18356		T47	191160
sram_ifetch_valid_disable	116419545	1			T1	330384		T2	7024		T3	1472
sram_ifetch_enable	20736480	1			T5	19892		T28	1708		T24	222012

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147128406	1			T1	330384		T2	7024		T3	1472
hw_debug_en_valid_off	116302219	1			T1	330384		T2	7024		T3	1472
hw_debug_en_on	20110714	1			T5	19508		T28	87908		T24	100762

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116419545	1			T1	330384		T2	7024		T3	1472
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	104346485	1			T1	330384		T2	7024		T3	1472
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7359947	1			T24	115126		T47	204040		T65	212992
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3775029	1			T28	82		T24	18356		T47	42108
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1249807	1			T28	82		T18	85530		T169	11102
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1306302	1			T24	18356		T47	42108		T21	6896
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4126330	1			T28	73244		T47	149052		T65	27276
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1410498	1			T28	73244		T47	2146		T65	8798
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1713916	1			T47	146906		T65	18478		T21	162528
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7806950	1			T5	19412		T28	12956		T24	59710
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2961404	1			T5	19412		T28	12956		T24	17412
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2762512	1			T24	28424		T47	27686		T65	81630

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8644870	1			T5	19892		T24	37584		T47	205820
lc_exec_en	8177434	1			T5	96		T28	1708		T24	41052
valid_exec_dis	110003002	1			T1	330384		T2	7024		T3	1472
invalid_exec_dis	30708861	1			T5	19892		T28	75034		T24	240368