Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45268227	1			T1	150196		T2	960		T3	140
triple_byte_access	2507358	1			T1	2964		T2	17		T3	120
halfword_access	3762807	1			T1	4458		T2	15		T3	178
byte_access	5028314	1			T1	6089		T2	40		T3	235
zero_access	1263693	1			T1	1485		T2	11		T3	63

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28857174

1

T1

82398

T2

519

T3

349

auto[1]

28973225

1

T1

82794

T2

524

T3

387

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22582819	1			T1	74907		T2	479		T3	64
auto[0]	triple_byte_access	1249988	1			T1	1469		T2	5		T3	52
auto[0]	halfword_access	1875994	1			T1	2193		T2	11		T3	84
auto[0]	byte_access	2513518	1			T1	3082		T2	19		T3	116
auto[0]	zero_access	634855	1			T1	747		T2	5		T3	33
auto[1]	word_access	22685408	1			T1	75289		T2	481		T3	76
auto[1]	triple_byte_access	1257370	1			T1	1495		T2	12		T3	68
auto[1]	halfword_access	1886813	1			T1	2265		T2	4		T3	94
auto[1]	byte_access	2514796	1			T1	3007		T2	21		T3	119
auto[1]	zero_access	628838	1			T1	738		T2	6		T3	30