| T798 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.453614272 |
|
|
Jun 13 01:14:16 PM PDT 24 |
Jun 13 01:16:20 PM PDT 24 |
2375226736 ps |
| T799 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3245104554 |
|
|
Jun 13 01:14:26 PM PDT 24 |
Jun 13 01:15:53 PM PDT 24 |
113189039 ps |
| T800 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.818864608 |
|
|
Jun 13 01:15:05 PM PDT 24 |
Jun 13 01:15:09 PM PDT 24 |
150838570 ps |
| T801 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3184228411 |
|
|
Jun 13 01:21:18 PM PDT 24 |
Jun 13 01:23:12 PM PDT 24 |
607685929 ps |
| T802 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.4049408476 |
|
|
Jun 13 01:14:50 PM PDT 24 |
Jun 13 01:14:52 PM PDT 24 |
288842642 ps |
| T803 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.125669785 |
|
|
Jun 13 01:17:28 PM PDT 24 |
Jun 13 01:24:04 PM PDT 24 |
10626338593 ps |
| T804 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2527811819 |
|
|
Jun 13 01:14:06 PM PDT 24 |
Jun 13 01:17:01 PM PDT 24 |
1788305099 ps |
| T805 |
/workspace/coverage/default/41.sram_ctrl_bijection.2219443827 |
|
|
Jun 13 02:23:45 PM PDT 24 |
Jun 13 02:24:16 PM PDT 24 |
1356795698 ps |
| T806 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.2640383955 |
|
|
Jun 13 01:15:31 PM PDT 24 |
Jun 13 01:15:38 PM PDT 24 |
1061152488 ps |
| T807 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.935817852 |
|
|
Jun 13 01:13:22 PM PDT 24 |
Jun 13 01:20:49 PM PDT 24 |
20078249947 ps |
| T808 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.2375994918 |
|
|
Jun 13 01:17:08 PM PDT 24 |
Jun 13 01:17:13 PM PDT 24 |
398111587 ps |
| T809 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1312855307 |
|
|
Jun 13 01:15:05 PM PDT 24 |
Jun 13 01:17:46 PM PDT 24 |
1742679686 ps |
| T810 |
/workspace/coverage/default/45.sram_ctrl_smoke.2706922034 |
|
|
Jun 13 02:13:00 PM PDT 24 |
Jun 13 02:13:09 PM PDT 24 |
622176938 ps |
| T811 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1968775645 |
|
|
Jun 13 02:40:57 PM PDT 24 |
Jun 13 02:44:17 PM PDT 24 |
2102165700 ps |
| T812 |
/workspace/coverage/default/4.sram_ctrl_stress_all.3790533226 |
|
|
Jun 13 01:14:05 PM PDT 24 |
Jun 13 02:01:06 PM PDT 24 |
58922319340 ps |
| T813 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.322958224 |
|
|
Jun 13 01:14:42 PM PDT 24 |
Jun 13 01:15:28 PM PDT 24 |
215755524 ps |
| T814 |
/workspace/coverage/default/43.sram_ctrl_executable.2968196079 |
|
|
Jun 13 01:17:54 PM PDT 24 |
Jun 13 01:36:09 PM PDT 24 |
58748737039 ps |
| T815 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3749017259 |
|
|
Jun 13 01:51:11 PM PDT 24 |
Jun 13 01:51:18 PM PDT 24 |
697195125 ps |
| T816 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.1693765813 |
|
|
Jun 13 01:47:27 PM PDT 24 |
Jun 13 01:47:28 PM PDT 24 |
261693884 ps |
| T817 |
/workspace/coverage/default/25.sram_ctrl_alert_test.1948145522 |
|
|
Jun 13 01:16:37 PM PDT 24 |
Jun 13 01:16:38 PM PDT 24 |
47298866 ps |
| T818 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2567060667 |
|
|
Jun 13 01:18:22 PM PDT 24 |
Jun 13 01:18:28 PM PDT 24 |
612817592 ps |
| T819 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3477495802 |
|
|
Jun 13 01:18:01 PM PDT 24 |
Jun 13 01:18:02 PM PDT 24 |
81538567 ps |
| T820 |
/workspace/coverage/default/39.sram_ctrl_partial_access.133965194 |
|
|
Jun 13 01:55:25 PM PDT 24 |
Jun 13 01:55:44 PM PDT 24 |
616005264 ps |
| T821 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1131642418 |
|
|
Jun 13 01:44:05 PM PDT 24 |
Jun 13 01:44:07 PM PDT 24 |
53813344 ps |
| T822 |
/workspace/coverage/default/33.sram_ctrl_executable.3136658514 |
|
|
Jun 13 02:44:51 PM PDT 24 |
Jun 13 02:45:09 PM PDT 24 |
1414258315 ps |
| T823 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.854235060 |
|
|
Jun 13 01:14:01 PM PDT 24 |
Jun 13 01:14:18 PM PDT 24 |
119935800 ps |
| T824 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2161930601 |
|
|
Jun 13 02:29:56 PM PDT 24 |
Jun 13 02:30:04 PM PDT 24 |
670704921 ps |
| T825 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1184951854 |
|
|
Jun 13 01:14:27 PM PDT 24 |
Jun 13 01:14:29 PM PDT 24 |
31312504 ps |
| T826 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.735024020 |
|
|
Jun 13 01:15:32 PM PDT 24 |
Jun 13 01:22:18 PM PDT 24 |
159408850139 ps |
| T827 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.151744939 |
|
|
Jun 13 02:12:58 PM PDT 24 |
Jun 13 02:36:58 PM PDT 24 |
3059643324 ps |
| T828 |
/workspace/coverage/default/11.sram_ctrl_alert_test.4263282690 |
|
|
Jun 13 01:14:35 PM PDT 24 |
Jun 13 01:14:36 PM PDT 24 |
39584152 ps |
| T829 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.373105879 |
|
|
Jun 13 01:13:46 PM PDT 24 |
Jun 13 01:20:27 PM PDT 24 |
3063364305 ps |
| T830 |
/workspace/coverage/default/35.sram_ctrl_alert_test.179175662 |
|
|
Jun 13 01:45:09 PM PDT 24 |
Jun 13 01:45:11 PM PDT 24 |
27772960 ps |
| T831 |
/workspace/coverage/default/37.sram_ctrl_regwen.3780763759 |
|
|
Jun 13 02:12:10 PM PDT 24 |
Jun 13 02:24:50 PM PDT 24 |
9340094453 ps |
| T832 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.589615734 |
|
|
Jun 13 01:16:38 PM PDT 24 |
Jun 13 01:16:52 PM PDT 24 |
276993084 ps |
| T833 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3257025619 |
|
|
Jun 13 01:32:33 PM PDT 24 |
Jun 13 01:32:34 PM PDT 24 |
94445286 ps |
| T834 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1297674082 |
|
|
Jun 13 01:16:44 PM PDT 24 |
Jun 13 01:17:06 PM PDT 24 |
616191288 ps |
| T835 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1547387904 |
|
|
Jun 13 01:17:49 PM PDT 24 |
Jun 13 01:20:16 PM PDT 24 |
5272998177 ps |
| T836 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1603456525 |
|
|
Jun 13 01:18:02 PM PDT 24 |
Jun 13 01:18:12 PM PDT 24 |
254815909 ps |
| T837 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3594686073 |
|
|
Jun 13 01:14:51 PM PDT 24 |
Jun 13 01:27:10 PM PDT 24 |
10940945550 ps |
| T838 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2716009155 |
|
|
Jun 13 01:15:40 PM PDT 24 |
Jun 13 01:18:02 PM PDT 24 |
585657379 ps |
| T839 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3874399376 |
|
|
Jun 13 01:18:58 PM PDT 24 |
Jun 13 01:23:39 PM PDT 24 |
27169597165 ps |
| T840 |
/workspace/coverage/default/33.sram_ctrl_regwen.3644314733 |
|
|
Jun 13 01:17:26 PM PDT 24 |
Jun 13 01:37:29 PM PDT 24 |
4317369802 ps |
| T841 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1507987993 |
|
|
Jun 13 01:43:55 PM PDT 24 |
Jun 13 01:43:56 PM PDT 24 |
47081797 ps |
| T842 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3644584630 |
|
|
Jun 13 01:15:11 PM PDT 24 |
Jun 13 01:16:48 PM PDT 24 |
1243564229 ps |
| T843 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.2521120137 |
|
|
Jun 13 01:15:46 PM PDT 24 |
Jun 13 01:15:47 PM PDT 24 |
117314783 ps |
| T844 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.1953346587 |
|
|
Jun 13 01:17:09 PM PDT 24 |
Jun 13 01:17:20 PM PDT 24 |
1058828732 ps |
| T845 |
/workspace/coverage/default/32.sram_ctrl_regwen.1471663640 |
|
|
Jun 13 01:17:24 PM PDT 24 |
Jun 13 01:34:46 PM PDT 24 |
120593670467 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1688383549 |
|
|
Jun 13 01:15:16 PM PDT 24 |
Jun 13 01:16:28 PM PDT 24 |
471509531 ps |
| T847 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2180042147 |
|
|
Jun 13 01:17:27 PM PDT 24 |
Jun 13 01:46:53 PM PDT 24 |
22235338063 ps |
| T848 |
/workspace/coverage/default/36.sram_ctrl_smoke.222140246 |
|
|
Jun 13 01:17:37 PM PDT 24 |
Jun 13 01:17:49 PM PDT 24 |
2490802853 ps |
| T849 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.494359764 |
|
|
Jun 13 01:14:22 PM PDT 24 |
Jun 13 01:18:48 PM PDT 24 |
11063691990 ps |
| T850 |
/workspace/coverage/default/38.sram_ctrl_stress_all.1624395676 |
|
|
Jun 13 01:32:36 PM PDT 24 |
Jun 13 02:15:11 PM PDT 24 |
67307322426 ps |
| T851 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1928739339 |
|
|
Jun 13 01:15:54 PM PDT 24 |
Jun 13 01:35:38 PM PDT 24 |
14846555530 ps |
| T852 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2133773398 |
|
|
Jun 13 02:04:31 PM PDT 24 |
Jun 13 02:04:37 PM PDT 24 |
90091496 ps |
| T853 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1742486809 |
|
|
Jun 13 01:18:04 PM PDT 24 |
Jun 13 01:18:10 PM PDT 24 |
486223314 ps |
| T854 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3851430710 |
|
|
Jun 13 01:13:37 PM PDT 24 |
Jun 13 01:15:34 PM PDT 24 |
552177191 ps |
| T855 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2909483451 |
|
|
Jun 13 01:29:43 PM PDT 24 |
Jun 13 01:30:02 PM PDT 24 |
6018263601 ps |
| T856 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1023300680 |
|
|
Jun 13 01:26:03 PM PDT 24 |
Jun 13 01:27:54 PM PDT 24 |
140178416 ps |
| T857 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3366513402 |
|
|
Jun 13 01:16:02 PM PDT 24 |
Jun 13 01:22:00 PM PDT 24 |
34506172795 ps |
| T858 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.639972220 |
|
|
Jun 13 01:15:19 PM PDT 24 |
Jun 13 01:15:37 PM PDT 24 |
1070680391 ps |
| T859 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1001706406 |
|
|
Jun 13 01:14:27 PM PDT 24 |
Jun 13 01:18:29 PM PDT 24 |
26110594801 ps |
| T860 |
/workspace/coverage/default/40.sram_ctrl_alert_test.389101507 |
|
|
Jun 13 02:40:18 PM PDT 24 |
Jun 13 02:40:23 PM PDT 24 |
45505790 ps |
| T861 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1809752640 |
|
|
Jun 13 01:17:36 PM PDT 24 |
Jun 13 01:22:23 PM PDT 24 |
1088339363 ps |
| T862 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1949120050 |
|
|
Jun 13 01:37:40 PM PDT 24 |
Jun 13 01:42:08 PM PDT 24 |
3647643779 ps |
| T863 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.3650343091 |
|
|
Jun 13 01:26:29 PM PDT 24 |
Jun 13 01:26:34 PM PDT 24 |
131324452 ps |
| T864 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.176504516 |
|
|
Jun 13 01:48:24 PM PDT 24 |
Jun 13 01:48:26 PM PDT 24 |
48688949 ps |
| T865 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3819962378 |
|
|
Jun 13 01:14:05 PM PDT 24 |
Jun 13 01:14:15 PM PDT 24 |
574855430 ps |
| T866 |
/workspace/coverage/default/44.sram_ctrl_alert_test.776872651 |
|
|
Jun 13 01:23:14 PM PDT 24 |
Jun 13 01:23:15 PM PDT 24 |
10520379 ps |
| T867 |
/workspace/coverage/default/16.sram_ctrl_stress_all.859745273 |
|
|
Jun 13 01:15:16 PM PDT 24 |
Jun 13 01:52:06 PM PDT 24 |
38013276882 ps |
| T868 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.243786243 |
|
|
Jun 13 01:15:31 PM PDT 24 |
Jun 13 01:15:32 PM PDT 24 |
106175417 ps |
| T869 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1534234038 |
|
|
Jun 13 01:14:57 PM PDT 24 |
Jun 13 01:31:50 PM PDT 24 |
35180125671 ps |
| T870 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3866920910 |
|
|
Jun 13 02:10:42 PM PDT 24 |
Jun 13 02:10:48 PM PDT 24 |
558411693 ps |
| T32 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3133990870 |
|
|
Jun 13 01:14:01 PM PDT 24 |
Jun 13 01:14:05 PM PDT 24 |
669175453 ps |
| T871 |
/workspace/coverage/default/43.sram_ctrl_regwen.1690811269 |
|
|
Jun 13 01:26:45 PM PDT 24 |
Jun 13 01:30:42 PM PDT 24 |
11238277758 ps |
| T872 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.826951489 |
|
|
Jun 13 01:15:35 PM PDT 24 |
Jun 13 01:15:36 PM PDT 24 |
166805261 ps |
| T873 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3420197491 |
|
|
Jun 13 01:15:25 PM PDT 24 |
Jun 13 01:15:32 PM PDT 24 |
197851555 ps |
| T874 |
/workspace/coverage/default/28.sram_ctrl_smoke.1283191644 |
|
|
Jun 13 01:16:57 PM PDT 24 |
Jun 13 01:17:13 PM PDT 24 |
1191726484 ps |
| T875 |
/workspace/coverage/default/42.sram_ctrl_smoke.2840688670 |
|
|
Jun 13 01:58:37 PM PDT 24 |
Jun 13 01:58:43 PM PDT 24 |
359118867 ps |
| T876 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.644299327 |
|
|
Jun 13 02:29:26 PM PDT 24 |
Jun 13 02:29:31 PM PDT 24 |
142955938 ps |
| T877 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1797391483 |
|
|
Jun 13 01:14:34 PM PDT 24 |
Jun 13 01:57:25 PM PDT 24 |
97644048839 ps |
| T878 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1727453760 |
|
|
Jun 13 01:14:07 PM PDT 24 |
Jun 13 01:16:04 PM PDT 24 |
147940634 ps |
| T879 |
/workspace/coverage/default/46.sram_ctrl_executable.2913065730 |
|
|
Jun 13 01:37:31 PM PDT 24 |
Jun 13 01:54:48 PM PDT 24 |
15036909649 ps |
| T880 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.885411823 |
|
|
Jun 13 01:48:34 PM PDT 24 |
Jun 13 01:56:48 PM PDT 24 |
23450548695 ps |
| T881 |
/workspace/coverage/default/17.sram_ctrl_executable.3706440663 |
|
|
Jun 13 01:15:20 PM PDT 24 |
Jun 13 01:15:59 PM PDT 24 |
1586449160 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3313782929 |
|
|
Jun 13 01:17:33 PM PDT 24 |
Jun 13 01:44:33 PM PDT 24 |
5272100725 ps |
| T883 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1919885655 |
|
|
Jun 13 01:13:32 PM PDT 24 |
Jun 13 01:25:31 PM PDT 24 |
3024145138 ps |
| T884 |
/workspace/coverage/default/19.sram_ctrl_bijection.2437581028 |
|
|
Jun 13 01:15:27 PM PDT 24 |
Jun 13 01:15:52 PM PDT 24 |
1392155221 ps |
| T885 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.339907340 |
|
|
Jun 13 01:19:30 PM PDT 24 |
Jun 13 01:22:55 PM PDT 24 |
2838776734 ps |
| T886 |
/workspace/coverage/default/46.sram_ctrl_bijection.4145651635 |
|
|
Jun 13 01:18:10 PM PDT 24 |
Jun 13 01:19:09 PM PDT 24 |
3809649090 ps |
| T887 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2629975993 |
|
|
Jun 13 01:14:17 PM PDT 24 |
Jun 13 01:14:19 PM PDT 24 |
17388086 ps |
| T888 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3367776880 |
|
|
Jun 13 01:16:59 PM PDT 24 |
Jun 13 01:17:01 PM PDT 24 |
44145384 ps |
| T889 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1573408299 |
|
|
Jun 13 01:31:14 PM PDT 24 |
Jun 13 01:31:26 PM PDT 24 |
3259715175 ps |
| T890 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.825526547 |
|
|
Jun 13 02:11:25 PM PDT 24 |
Jun 13 02:17:40 PM PDT 24 |
21206282163 ps |
| T891 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2277678138 |
|
|
Jun 13 01:53:06 PM PDT 24 |
Jun 13 01:55:10 PM PDT 24 |
133829330 ps |
| T892 |
/workspace/coverage/default/33.sram_ctrl_stress_all.311476614 |
|
|
Jun 13 01:51:54 PM PDT 24 |
Jun 13 02:20:35 PM PDT 24 |
14787797887 ps |
| T893 |
/workspace/coverage/default/48.sram_ctrl_bijection.1270091185 |
|
|
Jun 13 01:18:19 PM PDT 24 |
Jun 13 01:19:23 PM PDT 24 |
1963209686 ps |
| T894 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2765441582 |
|
|
Jun 13 02:21:31 PM PDT 24 |
Jun 13 02:23:43 PM PDT 24 |
847171154 ps |
| T895 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1575455241 |
|
|
Jun 13 01:14:27 PM PDT 24 |
Jun 13 01:34:41 PM PDT 24 |
13765468579 ps |
| T896 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2430276203 |
|
|
Jun 13 01:15:23 PM PDT 24 |
Jun 13 01:18:09 PM PDT 24 |
7215852536 ps |
| T897 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3884920243 |
|
|
Jun 13 01:36:04 PM PDT 24 |
Jun 13 01:36:13 PM PDT 24 |
2196207348 ps |
| T898 |
/workspace/coverage/default/47.sram_ctrl_stress_all.2434700068 |
|
|
Jun 13 02:03:41 PM PDT 24 |
Jun 13 02:35:48 PM PDT 24 |
13649473337 ps |
| T899 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3839708058 |
|
|
Jun 13 01:13:52 PM PDT 24 |
Jun 13 01:14:02 PM PDT 24 |
2600954485 ps |
| T900 |
/workspace/coverage/default/33.sram_ctrl_partial_access.784230139 |
|
|
Jun 13 02:20:12 PM PDT 24 |
Jun 13 02:20:27 PM PDT 24 |
1015727316 ps |
| T901 |
/workspace/coverage/default/5.sram_ctrl_bijection.2848758927 |
|
|
Jun 13 01:14:02 PM PDT 24 |
Jun 13 01:14:41 PM PDT 24 |
7509321494 ps |
| T902 |
/workspace/coverage/default/34.sram_ctrl_executable.2111231359 |
|
|
Jun 13 02:23:20 PM PDT 24 |
Jun 13 02:33:57 PM PDT 24 |
12576657484 ps |
| T903 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3433530063 |
|
|
Jun 13 01:52:56 PM PDT 24 |
Jun 13 01:53:20 PM PDT 24 |
1277230598 ps |
| T904 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2093705543 |
|
|
Jun 13 01:30:39 PM PDT 24 |
Jun 13 01:48:54 PM PDT 24 |
3069339766 ps |
| T905 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2068193386 |
|
|
Jun 13 01:14:57 PM PDT 24 |
Jun 13 01:14:58 PM PDT 24 |
26143844 ps |
| T906 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2971030299 |
|
|
Jun 13 01:17:27 PM PDT 24 |
Jun 13 01:20:01 PM PDT 24 |
1650860032 ps |
| T907 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3413341787 |
|
|
Jun 13 01:16:08 PM PDT 24 |
Jun 13 01:16:26 PM PDT 24 |
286472197 ps |
| T908 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1737870112 |
|
|
Jun 13 01:17:22 PM PDT 24 |
Jun 13 01:19:40 PM PDT 24 |
158612156 ps |
| T909 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.1402263629 |
|
|
Jun 13 01:14:03 PM PDT 24 |
Jun 13 01:14:18 PM PDT 24 |
11385932010 ps |
| T910 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.241823462 |
|
|
Jun 13 01:18:09 PM PDT 24 |
Jun 13 01:20:22 PM PDT 24 |
1876158506 ps |
| T911 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2399919918 |
|
|
Jun 13 01:40:24 PM PDT 24 |
Jun 13 01:43:34 PM PDT 24 |
21484385463 ps |
| T912 |
/workspace/coverage/default/43.sram_ctrl_smoke.634808120 |
|
|
Jun 13 01:17:55 PM PDT 24 |
Jun 13 01:18:12 PM PDT 24 |
774987540 ps |
| T913 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3706505760 |
|
|
Jun 13 01:14:57 PM PDT 24 |
Jun 13 01:15:00 PM PDT 24 |
454198036 ps |
| T914 |
/workspace/coverage/default/28.sram_ctrl_regwen.843896995 |
|
|
Jun 13 01:17:12 PM PDT 24 |
Jun 13 01:30:43 PM PDT 24 |
17697227667 ps |
| T915 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2196352986 |
|
|
Jun 13 01:16:15 PM PDT 24 |
Jun 13 01:33:54 PM PDT 24 |
117128361664 ps |
| T916 |
/workspace/coverage/default/1.sram_ctrl_regwen.974427334 |
|
|
Jun 13 01:13:37 PM PDT 24 |
Jun 13 01:22:09 PM PDT 24 |
7073917120 ps |
| T917 |
/workspace/coverage/default/26.sram_ctrl_stress_all.1438312114 |
|
|
Jun 13 01:16:46 PM PDT 24 |
Jun 13 02:43:37 PM PDT 24 |
357318866997 ps |
| T918 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.923497926 |
|
|
Jun 13 02:15:04 PM PDT 24 |
Jun 13 02:24:17 PM PDT 24 |
2420164387 ps |
| T919 |
/workspace/coverage/default/11.sram_ctrl_bijection.739944163 |
|
|
Jun 13 01:14:30 PM PDT 24 |
Jun 13 01:15:54 PM PDT 24 |
15075306616 ps |
| T920 |
/workspace/coverage/default/20.sram_ctrl_bijection.1165317272 |
|
|
Jun 13 01:15:40 PM PDT 24 |
Jun 13 01:17:09 PM PDT 24 |
8631190078 ps |
| T921 |
/workspace/coverage/default/8.sram_ctrl_executable.2186901228 |
|
|
Jun 13 01:14:26 PM PDT 24 |
Jun 13 01:36:23 PM PDT 24 |
10417720723 ps |
| T922 |
/workspace/coverage/default/16.sram_ctrl_bijection.143673636 |
|
|
Jun 13 01:15:10 PM PDT 24 |
Jun 13 01:16:17 PM PDT 24 |
4111684818 ps |
| T923 |
/workspace/coverage/default/46.sram_ctrl_regwen.2318892169 |
|
|
Jun 13 02:42:59 PM PDT 24 |
Jun 13 03:17:08 PM PDT 24 |
20396170523 ps |
| T924 |
/workspace/coverage/default/22.sram_ctrl_regwen.2015050774 |
|
|
Jun 13 01:16:02 PM PDT 24 |
Jun 13 01:26:08 PM PDT 24 |
1014728652 ps |
| T925 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1089863927 |
|
|
Jun 13 01:14:22 PM PDT 24 |
Jun 13 01:14:25 PM PDT 24 |
414366484 ps |
| T926 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3098987914 |
|
|
Jun 13 01:13:59 PM PDT 24 |
Jun 13 01:19:32 PM PDT 24 |
3583611082 ps |
| T927 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.667317033 |
|
|
Jun 13 01:16:00 PM PDT 24 |
Jun 13 01:16:07 PM PDT 24 |
724276119 ps |
| T928 |
/workspace/coverage/default/5.sram_ctrl_regwen.905949676 |
|
|
Jun 13 01:14:07 PM PDT 24 |
Jun 13 01:29:50 PM PDT 24 |
6431146594 ps |
| T929 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.2551171341 |
|
|
Jun 13 01:15:37 PM PDT 24 |
Jun 13 01:15:48 PM PDT 24 |
1173930371 ps |
| T930 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1102928408 |
|
|
Jun 13 02:58:05 PM PDT 24 |
Jun 13 03:13:30 PM PDT 24 |
59019202482 ps |
| T931 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3149509431 |
|
|
Jun 13 01:14:35 PM PDT 24 |
Jun 13 01:14:38 PM PDT 24 |
44690483 ps |
| T932 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4053273250 |
|
|
Jun 13 01:16:20 PM PDT 24 |
Jun 13 01:21:49 PM PDT 24 |
9383769055 ps |
| T933 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3453766180 |
|
|
Jun 13 02:18:01 PM PDT 24 |
Jun 13 02:21:34 PM PDT 24 |
2188841944 ps |
| T934 |
/workspace/coverage/default/4.sram_ctrl_executable.3767651511 |
|
|
Jun 13 01:14:01 PM PDT 24 |
Jun 13 01:18:58 PM PDT 24 |
42218615322 ps |
| T935 |
/workspace/coverage/default/20.sram_ctrl_smoke.216509209 |
|
|
Jun 13 01:15:40 PM PDT 24 |
Jun 13 01:15:57 PM PDT 24 |
735631606 ps |
| T936 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2018459107 |
|
|
Jun 13 01:14:31 PM PDT 24 |
Jun 13 01:14:37 PM PDT 24 |
805998547 ps |
| T937 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2409468123 |
|
|
Jun 13 01:35:23 PM PDT 24 |
Jun 13 01:35:28 PM PDT 24 |
252647156 ps |
| T938 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3854354169 |
|
|
Jun 13 01:15:43 PM PDT 24 |
Jun 13 01:19:37 PM PDT 24 |
17833603425 ps |
| T939 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.649883610 |
|
|
Jun 13 01:13:52 PM PDT 24 |
Jun 13 01:14:25 PM PDT 24 |
233936625 ps |
| T940 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3295448137 |
|
|
Jun 13 01:14:05 PM PDT 24 |
Jun 13 01:21:26 PM PDT 24 |
1472805236 ps |
| T941 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4189975666 |
|
|
Jun 13 01:14:23 PM PDT 24 |
Jun 13 01:15:00 PM PDT 24 |
676961887 ps |
| T942 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.749023801 |
|
|
Jun 13 01:14:48 PM PDT 24 |
Jun 13 01:33:52 PM PDT 24 |
4723321991 ps |
| T943 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3660031219 |
|
|
Jun 13 01:16:42 PM PDT 24 |
Jun 13 01:16:43 PM PDT 24 |
40752183 ps |
| T944 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3952575390 |
|
|
Jun 13 01:15:55 PM PDT 24 |
Jun 13 01:16:02 PM PDT 24 |
309484030 ps |
| T945 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3195750068 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:16 PM PDT 24 |
80948937 ps |
| T67 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3134077985 |
|
|
Jun 13 02:31:24 PM PDT 24 |
Jun 13 02:31:30 PM PDT 24 |
410596302 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.543866476 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:16 PM PDT 24 |
48837861 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3538899344 |
|
|
Jun 13 02:31:25 PM PDT 24 |
Jun 13 02:31:31 PM PDT 24 |
34690795 ps |
| T948 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3242827987 |
|
|
Jun 13 02:31:18 PM PDT 24 |
Jun 13 02:31:23 PM PDT 24 |
60746888 ps |
| T68 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2301911248 |
|
|
Jun 13 02:31:09 PM PDT 24 |
Jun 13 02:31:13 PM PDT 24 |
622228206 ps |
| T949 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3781708458 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
151768950 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2457895656 |
|
|
Jun 13 02:31:06 PM PDT 24 |
Jun 13 02:31:08 PM PDT 24 |
26372969 ps |
| T160 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2909155815 |
|
|
Jun 13 02:31:05 PM PDT 24 |
Jun 13 02:31:09 PM PDT 24 |
233365594 ps |
| T950 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.425890233 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:14 PM PDT 24 |
62087574 ps |
| T126 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2388157426 |
|
|
Jun 13 02:30:57 PM PDT 24 |
Jun 13 02:30:59 PM PDT 24 |
34387537 ps |
| T127 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.659354788 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:17 PM PDT 24 |
34898435 ps |
| T106 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1914484916 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:17 PM PDT 24 |
24969251 ps |
| T62 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.850393486 |
|
|
Jun 13 02:30:57 PM PDT 24 |
Jun 13 02:31:00 PM PDT 24 |
287461307 ps |
| T80 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.184510123 |
|
|
Jun 13 02:31:22 PM PDT 24 |
Jun 13 02:31:30 PM PDT 24 |
1602106271 ps |
| T63 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3050248100 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:18 PM PDT 24 |
153113579 ps |
| T81 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.126757225 |
|
|
Jun 13 02:31:22 PM PDT 24 |
Jun 13 02:31:26 PM PDT 24 |
15573914 ps |
| T64 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4272900437 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
102248431 ps |
| T82 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1902290136 |
|
|
Jun 13 02:31:22 PM PDT 24 |
Jun 13 02:31:26 PM PDT 24 |
40797247 ps |
| T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3432274240 |
|
|
Jun 13 02:31:07 PM PDT 24 |
Jun 13 02:31:09 PM PDT 24 |
28849257 ps |
| T83 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.213034470 |
|
|
Jun 13 02:31:30 PM PDT 24 |
Jun 13 02:31:38 PM PDT 24 |
939144805 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3074777781 |
|
|
Jun 13 02:31:04 PM PDT 24 |
Jun 13 02:31:05 PM PDT 24 |
18500964 ps |
| T146 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3301603765 |
|
|
Jun 13 02:31:00 PM PDT 24 |
Jun 13 02:31:04 PM PDT 24 |
330324438 ps |
| T108 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.973448186 |
|
|
Jun 13 02:31:21 PM PDT 24 |
Jun 13 02:31:24 PM PDT 24 |
71020561 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1929572501 |
|
|
Jun 13 02:31:37 PM PDT 24 |
Jun 13 02:31:43 PM PDT 24 |
64681909 ps |
| T84 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3669118834 |
|
|
Jun 13 02:31:33 PM PDT 24 |
Jun 13 02:31:42 PM PDT 24 |
395548313 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.952182757 |
|
|
Jun 13 02:31:12 PM PDT 24 |
Jun 13 02:31:17 PM PDT 24 |
57391088 ps |
| T954 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4082018592 |
|
|
Jun 13 02:31:32 PM PDT 24 |
Jun 13 02:31:41 PM PDT 24 |
61964804 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3987623660 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:17 PM PDT 24 |
21836793 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.794138217 |
|
|
Jun 13 02:30:56 PM PDT 24 |
Jun 13 02:30:59 PM PDT 24 |
4073088628 ps |
| T86 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.275454930 |
|
|
Jun 13 02:31:14 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
846238903 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2895189835 |
|
|
Jun 13 02:31:26 PM PDT 24 |
Jun 13 02:31:32 PM PDT 24 |
63260609 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.488212792 |
|
|
Jun 13 02:31:14 PM PDT 24 |
Jun 13 02:31:19 PM PDT 24 |
120755323 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2183276764 |
|
|
Jun 13 02:31:01 PM PDT 24 |
Jun 13 02:31:03 PM PDT 24 |
147749156 ps |
| T97 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.545287123 |
|
|
Jun 13 02:30:57 PM PDT 24 |
Jun 13 02:30:59 PM PDT 24 |
29960588 ps |
| T958 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4175923104 |
|
|
Jun 13 02:31:17 PM PDT 24 |
Jun 13 02:31:26 PM PDT 24 |
26198450 ps |
| T959 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1097213770 |
|
|
Jun 13 02:31:25 PM PDT 24 |
Jun 13 02:31:33 PM PDT 24 |
65789547 ps |
| T150 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1465737008 |
|
|
Jun 13 02:31:20 PM PDT 24 |
Jun 13 02:31:24 PM PDT 24 |
310579935 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.65751514 |
|
|
Jun 13 02:31:17 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
13565891 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3535199880 |
|
|
Jun 13 02:31:22 PM PDT 24 |
Jun 13 02:31:27 PM PDT 24 |
67886092 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.279606564 |
|
|
Jun 13 02:31:03 PM PDT 24 |
Jun 13 02:31:06 PM PDT 24 |
48021869 ps |
| T962 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.719905902 |
|
|
Jun 13 02:31:41 PM PDT 24 |
Jun 13 02:31:46 PM PDT 24 |
28113577 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3274578171 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:17 PM PDT 24 |
35107000 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2274825942 |
|
|
Jun 13 02:31:25 PM PDT 24 |
Jun 13 02:31:32 PM PDT 24 |
107883265 ps |
| T965 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.361114447 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:12 PM PDT 24 |
29754281 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2290704424 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:19 PM PDT 24 |
565134272 ps |
| T152 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1753685908 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:18 PM PDT 24 |
263389818 ps |
| T966 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.239557825 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:16 PM PDT 24 |
80035585 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2703736193 |
|
|
Jun 13 02:31:30 PM PDT 24 |
Jun 13 02:31:38 PM PDT 24 |
120229362 ps |
| T968 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.447127330 |
|
|
Jun 13 02:31:07 PM PDT 24 |
Jun 13 02:31:09 PM PDT 24 |
14671985 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2188216343 |
|
|
Jun 13 02:31:12 PM PDT 24 |
Jun 13 02:31:18 PM PDT 24 |
1649655918 ps |
| T969 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3128270102 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
13561416 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3115871547 |
|
|
Jun 13 02:31:30 PM PDT 24 |
Jun 13 02:31:37 PM PDT 24 |
43411211 ps |
| T971 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3724871948 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:24 PM PDT 24 |
118009277 ps |
| T972 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2451536686 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:17 PM PDT 24 |
2055332307 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2281583413 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:21 PM PDT 24 |
331373358 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2057146525 |
|
|
Jun 13 02:31:18 PM PDT 24 |
Jun 13 02:31:22 PM PDT 24 |
15450507 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.957385231 |
|
|
Jun 13 02:31:06 PM PDT 24 |
Jun 13 02:31:09 PM PDT 24 |
822858471 ps |
| T976 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2277586833 |
|
|
Jun 13 02:31:25 PM PDT 24 |
Jun 13 02:31:32 PM PDT 24 |
63816233 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1159899505 |
|
|
Jun 13 02:31:14 PM PDT 24 |
Jun 13 02:31:18 PM PDT 24 |
35619938 ps |
| T98 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2256262843 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:22 PM PDT 24 |
1714528444 ps |
| T978 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3906418629 |
|
|
Jun 13 02:31:15 PM PDT 24 |
Jun 13 02:31:22 PM PDT 24 |
290018318 ps |
| T147 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3131963680 |
|
|
Jun 13 02:31:30 PM PDT 24 |
Jun 13 02:31:43 PM PDT 24 |
150051636 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3058141620 |
|
|
Jun 13 02:31:12 PM PDT 24 |
Jun 13 02:31:16 PM PDT 24 |
75205713 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.80284680 |
|
|
Jun 13 02:31:09 PM PDT 24 |
Jun 13 02:31:13 PM PDT 24 |
1648328786 ps |
| T980 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1699963945 |
|
|
Jun 13 02:31:14 PM PDT 24 |
Jun 13 02:31:22 PM PDT 24 |
262605741 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4266616362 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:14 PM PDT 24 |
13582455 ps |
| T100 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2798818707 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
678723478 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1936284046 |
|
|
Jun 13 02:31:05 PM PDT 24 |
Jun 13 02:31:08 PM PDT 24 |
29552251 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2288033486 |
|
|
Jun 13 02:31:20 PM PDT 24 |
Jun 13 02:31:24 PM PDT 24 |
90496118 ps |
| T984 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2444605478 |
|
|
Jun 13 02:31:21 PM PDT 24 |
Jun 13 02:31:25 PM PDT 24 |
15928089 ps |
| T985 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2413894144 |
|
|
Jun 13 02:31:17 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
13490817 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.374521083 |
|
|
Jun 13 02:31:31 PM PDT 24 |
Jun 13 02:31:37 PM PDT 24 |
13109436 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4273133924 |
|
|
Jun 13 02:30:57 PM PDT 24 |
Jun 13 02:30:58 PM PDT 24 |
50561300 ps |
| T153 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2026346274 |
|
|
Jun 13 02:31:24 PM PDT 24 |
Jun 13 02:31:32 PM PDT 24 |
2562696389 ps |
| T156 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3851157505 |
|
|
Jun 13 02:31:23 PM PDT 24 |
Jun 13 02:31:30 PM PDT 24 |
771440346 ps |
| T151 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.297150059 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:21 PM PDT 24 |
387890533 ps |
| T148 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2015992973 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:21 PM PDT 24 |
1848995400 ps |
| T101 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1621703447 |
|
|
Jun 13 02:31:10 PM PDT 24 |
Jun 13 02:31:14 PM PDT 24 |
812968093 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1288485134 |
|
|
Jun 13 02:31:06 PM PDT 24 |
Jun 13 02:31:08 PM PDT 24 |
17790110 ps |
| T149 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1970571993 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
588849651 ps |
| T155 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3264609205 |
|
|
Jun 13 02:31:14 PM PDT 24 |
Jun 13 02:31:20 PM PDT 24 |
483118052 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4028424478 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:14 PM PDT 24 |
12158870 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1434828557 |
|
|
Jun 13 02:31:08 PM PDT 24 |
Jun 13 02:31:10 PM PDT 24 |
31666791 ps |
| T991 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3850588796 |
|
|
Jun 13 02:31:12 PM PDT 24 |
Jun 13 02:31:16 PM PDT 24 |
32597219 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3787077038 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:19 PM PDT 24 |
29354969 ps |
| T993 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3507544588 |
|
|
Jun 13 02:31:11 PM PDT 24 |
Jun 13 02:31:13 PM PDT 24 |
43695795 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3477408453 |
|
|
Jun 13 02:30:56 PM PDT 24 |
Jun 13 02:30:58 PM PDT 24 |
222787979 ps |
| T995 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.555674140 |
|
|
Jun 13 02:31:10 PM PDT 24 |
Jun 13 02:31:13 PM PDT 24 |
33986521 ps |
| T996 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2207091803 |
|
|
Jun 13 02:31:16 PM PDT 24 |
Jun 13 02:31:24 PM PDT 24 |
1619838442 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3843980101 |
|
|
Jun 13 02:30:57 PM PDT 24 |
Jun 13 02:31:00 PM PDT 24 |
89969357 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.435698292 |
|
|
Jun 13 02:31:22 PM PDT 24 |
Jun 13 02:31:27 PM PDT 24 |
82417358 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2743169208 |
|
|
Jun 13 02:31:00 PM PDT 24 |
Jun 13 02:31:02 PM PDT 24 |
13246394 ps |
| T1000 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.394710586 |
|
|
Jun 13 02:31:13 PM PDT 24 |
Jun 13 02:31:18 PM PDT 24 |
20504814 ps |
| T102 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1215913442 |
|
|
Jun 13 02:31:10 PM PDT 24 |
Jun 13 02:31:13 PM PDT 24 |
396178358 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1359531085 |
|
|
Jun 13 02:30:58 PM PDT 24 |
Jun 13 02:31:00 PM PDT 24 |
31029267 ps |
| T1002 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3490719202 |
|
|
Jun 13 02:31:23 PM PDT 24 |
Jun 13 02:31:29 PM PDT 24 |
371869212 ps |
| T1003 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2302893262 |
|
|
Jun 13 02:30:58 PM PDT 24 |
Jun 13 02:31:01 PM PDT 24 |
242997322 ps |
| T154 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4226354361 |
|
|
Jun 13 02:31:10 PM PDT 24 |
Jun 13 02:31:12 PM PDT 24 |
770305048 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2697015336 |
|
|
Jun 13 02:31:01 PM PDT 24 |
Jun 13 02:31:05 PM PDT 24 |
542118469 ps |
| T1005 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1239944432 |
|
|
Jun 13 02:31:26 PM PDT 24 |
Jun 13 02:31:35 PM PDT 24 |
305177875 ps |
| T1006 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4035364494 |
|
|
Jun 13 02:31:32 PM PDT 24 |
Jun 13 02:31:40 PM PDT 24 |
793062315 ps |