Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	142743550	1			T1	2980		T2	338104		T3	68678
instr_valid_dis	114786425	1			T1	2980		T2	213458		T3	68678
instr_en	18908424	1			T2	88182		T12	62368		T26	208108

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9710251	1			T2	32176		T26	100820		T25	120478
sram_ifetch_valid_disable	112654654	1			T1	2980		T2	228048		T3	68678
sram_ifetch_enable	20378645	1			T2	77880		T12	62368		T26	175408

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	142743550	1			T1	2980		T2	338104		T3	68678
hw_debug_en_valid_off	113184126	1			T1	2980		T2	96342		T3	68678
hw_debug_en_on	19823090	1			T2	174718		T12	82296		T26	43270

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	112654654	1			T1	2980		T2	228048		T3	68678
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101992730	1			T1	2980		T2	175726		T3	68678
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7027225	1			T2	52322		T26	35768		T25	107184
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3840073	1			T2	19744		T26	48476		T25	92704
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1537654	1			T2	19744		T26	48476		T61	17566
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1584313	1			T25	92704		T21	1308		T64	20346
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3551484	1			T2	12432		T26	16986		T25	27774
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1536010	1			T20	15020		T61	7860		T63	7240
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1318348	1			T2	12432		T26	16986		T25	27774
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7795158	1			T2	120870		T12	19928		T26	6230
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3783098	1			T2	108466		T12	19928		T20	6446
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2613484	1			T2	12404		T26	6230		T25	31190

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8238704	1			T2	23428		T12	62368		T26	155354
lc_exec_en	8476448	1			T2	41416		T12	62368		T26	20054
valid_exec_dis	109908111	1			T1	2980		T2	94586		T3	68678
invalid_exec_dis	30088896	1			T2	110056		T12	62368		T26	276228