Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43899853	1			T1	1358		T2	61791		T3	31349
triple_byte_access	2437976	1			T1	25		T2	1222		T3	573
halfword_access	3662411	1			T1	43		T2	1897		T3	932
byte_access	4892424	1			T1	49		T2	2532		T3	1202
zero_access	1231417	1			T1	15		T2	580		T3	283

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28011574

1

T1

756

T2

33961

T3

17044

auto[1]

28112507

1

T1

734

T2

34061

T3

17295

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21904676	1			T1	690		T2	30868		T3	15564
auto[0]	triple_byte_access	1216732	1			T1	14		T2	656		T3	293
auto[0]	halfword_access	1826432	1			T1	19		T2	918		T3	440
auto[0]	byte_access	2445012	1			T1	27		T2	1232		T3	606
auto[0]	zero_access	618722	1			T1	6		T2	287		T3	141
auto[1]	word_access	21995177	1			T1	668		T2	30923		T3	15785
auto[1]	triple_byte_access	1221244	1			T1	11		T2	566		T3	280
auto[1]	halfword_access	1835979	1			T1	24		T2	979		T3	492
auto[1]	byte_access	2447412	1			T1	22		T2	1300		T3	596
auto[1]	zero_access	612695	1			T1	9		T2	293		T3	142