Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149673868	1			T1	346472		T2	5536		T3	206636
instr_valid_dis	121097621	1			T1	346472		T2	5536		T3	206636
instr_en	19969803	1			T6	130776		T9	262278		T41	81338

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10659505	1			T3	14198		T5	43530		T6	98628
sram_ifetch_valid_disable	115356103	1			T1	346472		T2	5536		T3	100350
sram_ifetch_enable	23658260	1			T3	92088		T5	103406		T6	147378

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149673868	1			T1	346472		T2	5536		T3	206636
hw_debug_en_valid_off	114233340	1			T1	346472		T2	5536		T3	66568
hw_debug_en_on	24473696	1			T3	62992		T5	10064		T6	136314

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115356103	1			T1	346472		T2	5536		T3	100350
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103591221	1			T1	346472		T2	5536		T3	100350
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7848263	1			T6	37390		T9	153484		T41	41580
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3799814	1			T5	10648		T6	28248		T9	45224
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1951504	1			T5	10648		T9	27868		T16	14668
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1423238	1			T6	28248		T9	17356		T41	26612
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4276699	1			T3	14198		T6	496		T9	69138
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2300184	1			T3	14198		T6	496		T9	15786
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1261848	1			T9	53352		T146	98		T147	27566
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9770809	1			T3	30136		T5	10064		T6	113818
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4650354	1			T3	30136		T5	10064		T6	92750
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3169554	1			T6	21068		T9	86144		T16	88

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8903676	1			T6	2000		T9	38086		T145	85622
lc_exec_en	10426188	1			T3	18658		T6	22000		T9	111290
valid_exec_dis	112947536	1			T1	346472		T2	5536		T3	105558
invalid_exec_dis	34317765	1			T3	106286		T5	146936		T6	246006