Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44848669	1			T1	157389		T2	193		T3	37553
triple_byte_access	2599471	1			T1	3152		T2	4		T3	749
halfword_access	3895710	1			T1	4727		T2	9		T3	1128
byte_access	5204479	1			T1	6365		T2	7		T3	1474
zero_access	1309885	1			T1	1603		T2	5		T3	391

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28866495

1

T1

86194

T2

105

T3

20604

auto[1]

28991719

1

T1

87042

T2

113

T3

20691

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22366366	1			T1	78396		T2	96		T3	18728
auto[0]	triple_byte_access	1296490	1			T1	1571		T2	1		T3	393
auto[0]	halfword_access	1944117	1			T1	2320		T2	4		T3	570
auto[0]	byte_access	2600261	1			T1	3114		T2	3		T3	720
auto[0]	zero_access	659261	1			T1	793		T2	1		T3	193
auto[1]	word_access	22482303	1			T1	78993		T2	97		T3	18825
auto[1]	triple_byte_access	1302981	1			T1	1581		T2	3		T3	356
auto[1]	halfword_access	1951593	1			T1	2407		T2	5		T3	558
auto[1]	byte_access	2604218	1			T1	3251		T2	4		T3	754
auto[1]	zero_access	650624	1			T1	810		T2	4		T3	198