| T27 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3605697833 |
|
|
Jul 09 07:04:55 PM PDT 24 |
Jul 09 07:04:59 PM PDT 24 |
444650190 ps |
| T799 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.333414917 |
|
|
Jul 09 07:07:05 PM PDT 24 |
Jul 09 07:07:13 PM PDT 24 |
97906073 ps |
| T800 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1941723290 |
|
|
Jul 09 07:09:42 PM PDT 24 |
Jul 09 07:11:19 PM PDT 24 |
1980357534 ps |
| T801 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3624329624 |
|
|
Jul 09 07:08:26 PM PDT 24 |
Jul 09 07:08:32 PM PDT 24 |
301177589 ps |
| T802 |
/workspace/coverage/default/39.sram_ctrl_partial_access.33901762 |
|
|
Jul 09 07:10:10 PM PDT 24 |
Jul 09 07:10:41 PM PDT 24 |
1162830328 ps |
| T803 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3073306540 |
|
|
Jul 09 07:06:30 PM PDT 24 |
Jul 09 07:06:34 PM PDT 24 |
46701711 ps |
| T804 |
/workspace/coverage/default/43.sram_ctrl_regwen.899219820 |
|
|
Jul 09 07:10:58 PM PDT 24 |
Jul 09 07:17:12 PM PDT 24 |
3667825667 ps |
| T805 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2566758998 |
|
|
Jul 09 07:04:35 PM PDT 24 |
Jul 09 07:33:12 PM PDT 24 |
15163860962 ps |
| T806 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1569643563 |
|
|
Jul 09 07:10:46 PM PDT 24 |
Jul 09 07:12:41 PM PDT 24 |
1416833404 ps |
| T807 |
/workspace/coverage/default/37.sram_ctrl_smoke.3628466833 |
|
|
Jul 09 07:09:38 PM PDT 24 |
Jul 09 07:09:43 PM PDT 24 |
213961908 ps |
| T808 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3458325965 |
|
|
Jul 09 07:09:39 PM PDT 24 |
Jul 09 07:09:46 PM PDT 24 |
393535886 ps |
| T809 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3418844876 |
|
|
Jul 09 07:09:17 PM PDT 24 |
Jul 09 07:17:07 PM PDT 24 |
154702975528 ps |
| T810 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2810990152 |
|
|
Jul 09 07:07:08 PM PDT 24 |
Jul 09 07:08:48 PM PDT 24 |
1022354316 ps |
| T811 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4045586285 |
|
|
Jul 09 07:12:35 PM PDT 24 |
Jul 09 07:29:33 PM PDT 24 |
8500046775 ps |
| T812 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.4128632704 |
|
|
Jul 09 07:05:45 PM PDT 24 |
Jul 09 07:07:58 PM PDT 24 |
491885034 ps |
| T813 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2654969988 |
|
|
Jul 09 07:04:41 PM PDT 24 |
Jul 09 07:04:43 PM PDT 24 |
30718297 ps |
| T814 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2997456352 |
|
|
Jul 09 07:06:21 PM PDT 24 |
Jul 09 07:06:22 PM PDT 24 |
74192131 ps |
| T815 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3652384755 |
|
|
Jul 09 07:06:00 PM PDT 24 |
Jul 09 07:06:03 PM PDT 24 |
21962094 ps |
| T816 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3079592545 |
|
|
Jul 09 07:04:30 PM PDT 24 |
Jul 09 07:08:01 PM PDT 24 |
8302892599 ps |
| T817 |
/workspace/coverage/default/27.sram_ctrl_smoke.1775129920 |
|
|
Jul 09 07:07:45 PM PDT 24 |
Jul 09 07:08:50 PM PDT 24 |
1811786471 ps |
| T818 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2920287625 |
|
|
Jul 09 07:05:56 PM PDT 24 |
Jul 09 07:06:55 PM PDT 24 |
869409987 ps |
| T819 |
/workspace/coverage/default/21.sram_ctrl_executable.2755312084 |
|
|
Jul 09 07:06:49 PM PDT 24 |
Jul 09 07:21:33 PM PDT 24 |
28785994823 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1437432130 |
|
|
Jul 09 07:07:39 PM PDT 24 |
Jul 09 07:07:40 PM PDT 24 |
25796509 ps |
| T821 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.524354800 |
|
|
Jul 09 07:05:50 PM PDT 24 |
Jul 09 07:09:08 PM PDT 24 |
2164872978 ps |
| T822 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.595774186 |
|
|
Jul 09 07:05:14 PM PDT 24 |
Jul 09 07:05:23 PM PDT 24 |
2995540037 ps |
| T823 |
/workspace/coverage/default/43.sram_ctrl_executable.4236650235 |
|
|
Jul 09 07:10:57 PM PDT 24 |
Jul 09 07:20:24 PM PDT 24 |
10497138057 ps |
| T824 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3542737506 |
|
|
Jul 09 07:06:15 PM PDT 24 |
Jul 09 07:08:57 PM PDT 24 |
1585960569 ps |
| T825 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.460349782 |
|
|
Jul 09 07:11:52 PM PDT 24 |
Jul 09 07:18:33 PM PDT 24 |
1785828466 ps |
| T826 |
/workspace/coverage/default/32.sram_ctrl_bijection.2865903193 |
|
|
Jul 09 07:08:39 PM PDT 24 |
Jul 09 07:09:12 PM PDT 24 |
667865235 ps |
| T124 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2737920533 |
|
|
Jul 09 07:05:03 PM PDT 24 |
Jul 09 07:05:21 PM PDT 24 |
2166569461 ps |
| T827 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1980235978 |
|
|
Jul 09 07:09:28 PM PDT 24 |
Jul 09 07:13:09 PM PDT 24 |
2345841140 ps |
| T828 |
/workspace/coverage/default/43.sram_ctrl_smoke.848376924 |
|
|
Jul 09 07:10:51 PM PDT 24 |
Jul 09 07:12:04 PM PDT 24 |
760987712 ps |
| T829 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2574103011 |
|
|
Jul 09 07:07:11 PM PDT 24 |
Jul 09 07:07:13 PM PDT 24 |
103598790 ps |
| T830 |
/workspace/coverage/default/31.sram_ctrl_regwen.3517204360 |
|
|
Jul 09 07:08:39 PM PDT 24 |
Jul 09 07:12:27 PM PDT 24 |
27916305704 ps |
| T831 |
/workspace/coverage/default/12.sram_ctrl_smoke.2957885204 |
|
|
Jul 09 07:05:44 PM PDT 24 |
Jul 09 07:05:49 PM PDT 24 |
463647820 ps |
| T832 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3633230094 |
|
|
Jul 09 07:09:08 PM PDT 24 |
Jul 09 07:11:22 PM PDT 24 |
1410686438 ps |
| T833 |
/workspace/coverage/default/2.sram_ctrl_smoke.3137676819 |
|
|
Jul 09 07:04:46 PM PDT 24 |
Jul 09 07:05:00 PM PDT 24 |
176509241 ps |
| T834 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3222744110 |
|
|
Jul 09 07:04:46 PM PDT 24 |
Jul 09 07:49:51 PM PDT 24 |
5279641731 ps |
| T835 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3388974466 |
|
|
Jul 09 07:10:30 PM PDT 24 |
Jul 09 07:10:52 PM PDT 24 |
310274775 ps |
| T836 |
/workspace/coverage/default/9.sram_ctrl_smoke.1200868211 |
|
|
Jul 09 07:05:24 PM PDT 24 |
Jul 09 07:05:45 PM PDT 24 |
2031061451 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1776521443 |
|
|
Jul 09 07:09:09 PM PDT 24 |
Jul 09 07:15:01 PM PDT 24 |
63387017227 ps |
| T838 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.355146623 |
|
|
Jul 09 07:07:13 PM PDT 24 |
Jul 09 07:07:20 PM PDT 24 |
214895408 ps |
| T839 |
/workspace/coverage/default/24.sram_ctrl_partial_access.187597295 |
|
|
Jul 09 07:07:14 PM PDT 24 |
Jul 09 07:07:21 PM PDT 24 |
266257807 ps |
| T840 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2273186642 |
|
|
Jul 09 07:07:44 PM PDT 24 |
Jul 09 07:24:56 PM PDT 24 |
18287121583 ps |
| T841 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3929806600 |
|
|
Jul 09 07:05:44 PM PDT 24 |
Jul 09 07:08:46 PM PDT 24 |
19372448788 ps |
| T842 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.247206603 |
|
|
Jul 09 07:04:58 PM PDT 24 |
Jul 09 07:12:49 PM PDT 24 |
33653287848 ps |
| T843 |
/workspace/coverage/default/15.sram_ctrl_regwen.2274043796 |
|
|
Jul 09 07:06:05 PM PDT 24 |
Jul 09 07:13:08 PM PDT 24 |
39407587878 ps |
| T844 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3900464373 |
|
|
Jul 09 07:06:17 PM PDT 24 |
Jul 09 07:22:02 PM PDT 24 |
11864616104 ps |
| T845 |
/workspace/coverage/default/39.sram_ctrl_bijection.1247763250 |
|
|
Jul 09 07:10:11 PM PDT 24 |
Jul 09 07:10:53 PM PDT 24 |
770734579 ps |
| T846 |
/workspace/coverage/default/40.sram_ctrl_executable.3966344226 |
|
|
Jul 09 07:10:25 PM PDT 24 |
Jul 09 07:20:39 PM PDT 24 |
9768280869 ps |
| T847 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3449807962 |
|
|
Jul 09 07:05:48 PM PDT 24 |
Jul 09 07:08:59 PM PDT 24 |
1562082558 ps |
| T848 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.449536852 |
|
|
Jul 09 07:05:19 PM PDT 24 |
Jul 09 07:05:24 PM PDT 24 |
100274859 ps |
| T849 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.787190850 |
|
|
Jul 09 07:06:14 PM PDT 24 |
Jul 09 07:15:19 PM PDT 24 |
72320684756 ps |
| T850 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2019889847 |
|
|
Jul 09 07:04:59 PM PDT 24 |
Jul 09 07:05:06 PM PDT 24 |
185285677 ps |
| T851 |
/workspace/coverage/default/33.sram_ctrl_partial_access.4141888741 |
|
|
Jul 09 07:08:57 PM PDT 24 |
Jul 09 07:11:42 PM PDT 24 |
1484883563 ps |
| T852 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3806522001 |
|
|
Jul 09 07:10:42 PM PDT 24 |
Jul 09 07:31:22 PM PDT 24 |
6681849227 ps |
| T853 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3713002821 |
|
|
Jul 09 07:04:41 PM PDT 24 |
Jul 09 07:10:29 PM PDT 24 |
23882575248 ps |
| T854 |
/workspace/coverage/default/29.sram_ctrl_smoke.2698292155 |
|
|
Jul 09 07:08:04 PM PDT 24 |
Jul 09 07:08:10 PM PDT 24 |
104529350 ps |
| T855 |
/workspace/coverage/default/34.sram_ctrl_executable.3450296234 |
|
|
Jul 09 07:09:13 PM PDT 24 |
Jul 09 07:29:08 PM PDT 24 |
31967937643 ps |
| T856 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1469758656 |
|
|
Jul 09 07:06:06 PM PDT 24 |
Jul 09 07:06:21 PM PDT 24 |
1429822239 ps |
| T857 |
/workspace/coverage/default/30.sram_ctrl_alert_test.4037418339 |
|
|
Jul 09 07:08:30 PM PDT 24 |
Jul 09 07:08:32 PM PDT 24 |
22705907 ps |
| T858 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.338508822 |
|
|
Jul 09 07:05:28 PM PDT 24 |
Jul 09 07:05:30 PM PDT 24 |
57661139 ps |
| T859 |
/workspace/coverage/default/21.sram_ctrl_bijection.1664524725 |
|
|
Jul 09 07:06:46 PM PDT 24 |
Jul 09 07:07:10 PM PDT 24 |
934529719 ps |
| T860 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3763579823 |
|
|
Jul 09 07:12:35 PM PDT 24 |
Jul 09 07:14:14 PM PDT 24 |
118700558 ps |
| T861 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3328692510 |
|
|
Jul 09 07:06:51 PM PDT 24 |
Jul 09 07:06:53 PM PDT 24 |
87276676 ps |
| T862 |
/workspace/coverage/default/8.sram_ctrl_executable.1626687887 |
|
|
Jul 09 07:05:23 PM PDT 24 |
Jul 09 07:35:38 PM PDT 24 |
14883457574 ps |
| T863 |
/workspace/coverage/default/32.sram_ctrl_stress_all.814285498 |
|
|
Jul 09 07:08:51 PM PDT 24 |
Jul 09 07:22:57 PM PDT 24 |
20934090813 ps |
| T864 |
/workspace/coverage/default/10.sram_ctrl_bijection.2188776480 |
|
|
Jul 09 07:05:32 PM PDT 24 |
Jul 09 07:06:52 PM PDT 24 |
3534758370 ps |
| T865 |
/workspace/coverage/default/9.sram_ctrl_regwen.1625625906 |
|
|
Jul 09 07:05:29 PM PDT 24 |
Jul 09 07:27:47 PM PDT 24 |
70381933619 ps |
| T866 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.4096744883 |
|
|
Jul 09 07:06:06 PM PDT 24 |
Jul 09 07:19:11 PM PDT 24 |
5705274242 ps |
| T867 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2989640348 |
|
|
Jul 09 07:11:07 PM PDT 24 |
Jul 09 07:15:20 PM PDT 24 |
1855378958 ps |
| T28 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3978489704 |
|
|
Jul 09 07:04:45 PM PDT 24 |
Jul 09 07:04:51 PM PDT 24 |
3002904067 ps |
| T868 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3050068400 |
|
|
Jul 09 07:06:45 PM PDT 24 |
Jul 09 07:06:47 PM PDT 24 |
34794421 ps |
| T869 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1458731402 |
|
|
Jul 09 07:04:36 PM PDT 24 |
Jul 09 07:50:27 PM PDT 24 |
157817061849 ps |
| T870 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1282664933 |
|
|
Jul 09 07:05:17 PM PDT 24 |
Jul 09 07:23:36 PM PDT 24 |
218594129589 ps |
| T871 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2969590661 |
|
|
Jul 09 07:06:44 PM PDT 24 |
Jul 09 07:06:51 PM PDT 24 |
641665787 ps |
| T872 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2852169148 |
|
|
Jul 09 07:06:35 PM PDT 24 |
Jul 09 07:19:46 PM PDT 24 |
3997528127 ps |
| T873 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.94818719 |
|
|
Jul 09 07:07:10 PM PDT 24 |
Jul 09 07:07:16 PM PDT 24 |
93135147 ps |
| T874 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2605196369 |
|
|
Jul 09 07:07:40 PM PDT 24 |
Jul 09 07:07:51 PM PDT 24 |
459265346 ps |
| T875 |
/workspace/coverage/default/21.sram_ctrl_smoke.3987339645 |
|
|
Jul 09 07:06:43 PM PDT 24 |
Jul 09 07:07:01 PM PDT 24 |
1560504504 ps |
| T876 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1255316033 |
|
|
Jul 09 07:09:21 PM PDT 24 |
Jul 09 07:11:55 PM PDT 24 |
610481302 ps |
| T877 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.4210480605 |
|
|
Jul 09 07:04:56 PM PDT 24 |
Jul 09 07:05:03 PM PDT 24 |
185362122 ps |
| T878 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1703796289 |
|
|
Jul 09 07:11:41 PM PDT 24 |
Jul 09 07:18:24 PM PDT 24 |
9919943359 ps |
| T879 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1039912199 |
|
|
Jul 09 07:10:02 PM PDT 24 |
Jul 09 07:30:13 PM PDT 24 |
74221485350 ps |
| T880 |
/workspace/coverage/default/10.sram_ctrl_partial_access.4064413102 |
|
|
Jul 09 07:05:33 PM PDT 24 |
Jul 09 07:05:40 PM PDT 24 |
210424852 ps |
| T881 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.888661135 |
|
|
Jul 09 07:05:19 PM PDT 24 |
Jul 09 07:05:27 PM PDT 24 |
924614622 ps |
| T882 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1841153302 |
|
|
Jul 09 07:11:58 PM PDT 24 |
Jul 09 07:15:52 PM PDT 24 |
7292051802 ps |
| T883 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3260298384 |
|
|
Jul 09 07:11:29 PM PDT 24 |
Jul 09 07:12:44 PM PDT 24 |
723805566 ps |
| T884 |
/workspace/coverage/default/5.sram_ctrl_executable.3571028476 |
|
|
Jul 09 07:05:08 PM PDT 24 |
Jul 09 07:16:04 PM PDT 24 |
22757256434 ps |
| T885 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3558324084 |
|
|
Jul 09 07:09:39 PM PDT 24 |
Jul 09 07:09:41 PM PDT 24 |
34188544 ps |
| T886 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.2639258522 |
|
|
Jul 09 07:11:16 PM PDT 24 |
Jul 09 07:12:25 PM PDT 24 |
916676915 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3088643893 |
|
|
Jul 09 07:08:47 PM PDT 24 |
Jul 09 07:09:54 PM PDT 24 |
228296516 ps |
| T888 |
/workspace/coverage/default/16.sram_ctrl_smoke.3111895076 |
|
|
Jul 09 07:06:08 PM PDT 24 |
Jul 09 07:07:33 PM PDT 24 |
1094741952 ps |
| T889 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2445313597 |
|
|
Jul 09 07:07:50 PM PDT 24 |
Jul 09 07:07:54 PM PDT 24 |
1094973476 ps |
| T890 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1450644959 |
|
|
Jul 09 07:05:59 PM PDT 24 |
Jul 09 07:07:49 PM PDT 24 |
2267330902 ps |
| T891 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.643460560 |
|
|
Jul 09 07:06:36 PM PDT 24 |
Jul 09 07:06:58 PM PDT 24 |
342925065 ps |
| T892 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2919874877 |
|
|
Jul 09 07:08:51 PM PDT 24 |
Jul 09 07:09:12 PM PDT 24 |
1382582594 ps |
| T893 |
/workspace/coverage/default/40.sram_ctrl_smoke.2746275455 |
|
|
Jul 09 07:10:15 PM PDT 24 |
Jul 09 07:10:18 PM PDT 24 |
90657581 ps |
| T894 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1079412619 |
|
|
Jul 09 07:05:40 PM PDT 24 |
Jul 09 07:05:43 PM PDT 24 |
41676017 ps |
| T895 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2099454 |
|
|
Jul 09 07:08:27 PM PDT 24 |
Jul 09 07:58:52 PM PDT 24 |
43520472340 ps |
| T896 |
/workspace/coverage/default/2.sram_ctrl_partial_access.4106319880 |
|
|
Jul 09 07:04:46 PM PDT 24 |
Jul 09 07:06:38 PM PDT 24 |
687287642 ps |
| T897 |
/workspace/coverage/default/24.sram_ctrl_regwen.1444746520 |
|
|
Jul 09 07:07:20 PM PDT 24 |
Jul 09 07:27:52 PM PDT 24 |
21447979965 ps |
| T898 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2977726564 |
|
|
Jul 09 07:05:22 PM PDT 24 |
Jul 09 07:05:25 PM PDT 24 |
402641896 ps |
| T899 |
/workspace/coverage/default/5.sram_ctrl_smoke.1914203657 |
|
|
Jul 09 07:05:02 PM PDT 24 |
Jul 09 07:05:18 PM PDT 24 |
505529657 ps |
| T900 |
/workspace/coverage/default/42.sram_ctrl_regwen.1291334066 |
|
|
Jul 09 07:10:45 PM PDT 24 |
Jul 09 07:23:13 PM PDT 24 |
1732658691 ps |
| T901 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3395479746 |
|
|
Jul 09 07:06:44 PM PDT 24 |
Jul 09 07:59:09 PM PDT 24 |
82165996944 ps |
| T902 |
/workspace/coverage/default/31.sram_ctrl_bijection.91374043 |
|
|
Jul 09 07:08:31 PM PDT 24 |
Jul 09 07:09:46 PM PDT 24 |
9507596293 ps |
| T903 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2086322477 |
|
|
Jul 09 07:08:10 PM PDT 24 |
Jul 09 07:08:24 PM PDT 24 |
242250614 ps |
| T904 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2845756170 |
|
|
Jul 09 07:04:52 PM PDT 24 |
Jul 09 07:04:58 PM PDT 24 |
390650402 ps |
| T905 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1064414886 |
|
|
Jul 09 07:06:14 PM PDT 24 |
Jul 09 07:08:19 PM PDT 24 |
2653081716 ps |
| T906 |
/workspace/coverage/default/1.sram_ctrl_bijection.152170288 |
|
|
Jul 09 07:04:45 PM PDT 24 |
Jul 09 07:06:05 PM PDT 24 |
3822133362 ps |
| T907 |
/workspace/coverage/default/47.sram_ctrl_stress_all.4061670867 |
|
|
Jul 09 07:12:26 PM PDT 24 |
Jul 09 07:16:03 PM PDT 24 |
2120818943 ps |
| T908 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1958585753 |
|
|
Jul 09 07:07:15 PM PDT 24 |
Jul 09 07:25:51 PM PDT 24 |
57770035235 ps |
| T909 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1319352367 |
|
|
Jul 09 07:04:31 PM PDT 24 |
Jul 09 07:04:40 PM PDT 24 |
1632858834 ps |
| T910 |
/workspace/coverage/default/44.sram_ctrl_executable.38293148 |
|
|
Jul 09 07:11:10 PM PDT 24 |
Jul 09 07:17:36 PM PDT 24 |
16302405567 ps |
| T911 |
/workspace/coverage/default/10.sram_ctrl_executable.623767483 |
|
|
Jul 09 07:05:40 PM PDT 24 |
Jul 09 07:20:31 PM PDT 24 |
3120327109 ps |
| T912 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2334370052 |
|
|
Jul 09 07:08:13 PM PDT 24 |
Jul 09 07:16:14 PM PDT 24 |
67313100774 ps |
| T913 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.4128990035 |
|
|
Jul 09 07:10:03 PM PDT 24 |
Jul 09 07:12:03 PM PDT 24 |
131115127 ps |
| T914 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.130825012 |
|
|
Jul 09 07:06:35 PM PDT 24 |
Jul 09 07:10:19 PM PDT 24 |
3141336280 ps |
| T915 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1311152458 |
|
|
Jul 09 07:05:13 PM PDT 24 |
Jul 09 07:05:16 PM PDT 24 |
14486153 ps |
| T916 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3721134971 |
|
|
Jul 09 07:12:49 PM PDT 24 |
Jul 09 07:21:03 PM PDT 24 |
76331987342 ps |
| T917 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3230259092 |
|
|
Jul 09 07:06:03 PM PDT 24 |
Jul 09 07:06:12 PM PDT 24 |
524265157 ps |
| T918 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3870721013 |
|
|
Jul 09 07:07:27 PM PDT 24 |
Jul 09 07:48:47 PM PDT 24 |
7726932747 ps |
| T919 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.4159997664 |
|
|
Jul 09 07:12:13 PM PDT 24 |
Jul 09 07:18:53 PM PDT 24 |
1160223813 ps |
| T920 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.3946064387 |
|
|
Jul 09 07:07:22 PM PDT 24 |
Jul 09 07:07:23 PM PDT 24 |
73663463 ps |
| T921 |
/workspace/coverage/default/49.sram_ctrl_executable.93128995 |
|
|
Jul 09 07:12:48 PM PDT 24 |
Jul 09 07:21:14 PM PDT 24 |
13528000324 ps |
| T922 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1040406740 |
|
|
Jul 09 07:10:10 PM PDT 24 |
Jul 09 07:10:17 PM PDT 24 |
95160337 ps |
| T923 |
/workspace/coverage/default/27.sram_ctrl_regwen.3617494884 |
|
|
Jul 09 07:07:49 PM PDT 24 |
Jul 09 07:10:02 PM PDT 24 |
5036561710 ps |
| T924 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3974933801 |
|
|
Jul 09 07:05:29 PM PDT 24 |
Jul 09 07:31:20 PM PDT 24 |
29281946063 ps |
| T925 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.4189244875 |
|
|
Jul 09 07:07:25 PM PDT 24 |
Jul 09 07:07:28 PM PDT 24 |
436379016 ps |
| T926 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1694543984 |
|
|
Jul 09 07:07:29 PM PDT 24 |
Jul 09 08:11:05 PM PDT 24 |
11930825331 ps |
| T927 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.926335463 |
|
|
Jul 09 07:06:12 PM PDT 24 |
Jul 09 07:10:18 PM PDT 24 |
14747892553 ps |
| T928 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1973615891 |
|
|
Jul 09 07:09:08 PM PDT 24 |
Jul 09 07:11:20 PM PDT 24 |
122638648 ps |
| T929 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1027633322 |
|
|
Jul 09 07:08:46 PM PDT 24 |
Jul 09 07:14:14 PM PDT 24 |
19832179868 ps |
| T930 |
/workspace/coverage/default/40.sram_ctrl_stress_all.3697526317 |
|
|
Jul 09 07:10:25 PM PDT 24 |
Jul 09 08:05:32 PM PDT 24 |
15298868538 ps |
| T931 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1054939262 |
|
|
Jul 09 07:05:14 PM PDT 24 |
Jul 09 07:20:40 PM PDT 24 |
40708831964 ps |
| T932 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.367337091 |
|
|
Jul 09 07:08:31 PM PDT 24 |
Jul 09 07:10:12 PM PDT 24 |
13371594097 ps |
| T69 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3040503382 |
|
|
Jul 09 05:11:22 PM PDT 24 |
Jul 09 05:11:28 PM PDT 24 |
198834849 ps |
| T933 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1844266436 |
|
|
Jul 09 05:11:17 PM PDT 24 |
Jul 09 05:11:24 PM PDT 24 |
412698000 ps |
| T74 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.385625501 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
26225054 ps |
| T934 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1511154828 |
|
|
Jul 09 05:11:21 PM PDT 24 |
Jul 09 05:11:29 PM PDT 24 |
296759594 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1214942013 |
|
|
Jul 09 05:11:06 PM PDT 24 |
Jul 09 05:11:09 PM PDT 24 |
115907160 ps |
| T935 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1200105327 |
|
|
Jul 09 05:11:13 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
102410757 ps |
| T109 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3358009076 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
72265747 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4216573798 |
|
|
Jul 09 05:11:09 PM PDT 24 |
Jul 09 05:11:16 PM PDT 24 |
4907830584 ps |
| T144 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.910494677 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:17 PM PDT 24 |
13395939 ps |
| T936 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1985509302 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:18 PM PDT 24 |
24455651 ps |
| T937 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.725595067 |
|
|
Jul 09 05:11:24 PM PDT 24 |
Jul 09 05:11:28 PM PDT 24 |
49023048 ps |
| T938 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2579797760 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:20 PM PDT 24 |
75663838 ps |
| T939 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2804477132 |
|
|
Jul 09 05:11:22 PM PDT 24 |
Jul 09 05:11:30 PM PDT 24 |
624435429 ps |
| T116 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4198515253 |
|
|
Jul 09 05:11:04 PM PDT 24 |
Jul 09 05:11:08 PM PDT 24 |
15260571 ps |
| T117 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2958338589 |
|
|
Jul 09 05:11:02 PM PDT 24 |
Jul 09 05:11:08 PM PDT 24 |
152532056 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4034809250 |
|
|
Jul 09 05:11:00 PM PDT 24 |
Jul 09 05:11:04 PM PDT 24 |
24061199 ps |
| T940 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.933342238 |
|
|
Jul 09 05:11:05 PM PDT 24 |
Jul 09 05:11:09 PM PDT 24 |
83300727 ps |
| T87 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.130674834 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:14 PM PDT 24 |
86553687 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1397180513 |
|
|
Jul 09 05:11:11 PM PDT 24 |
Jul 09 05:11:17 PM PDT 24 |
47307321 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2190755105 |
|
|
Jul 09 05:11:17 PM PDT 24 |
Jul 09 05:11:24 PM PDT 24 |
48070821 ps |
| T70 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1514563157 |
|
|
Jul 09 05:11:16 PM PDT 24 |
Jul 09 05:11:23 PM PDT 24 |
364363808 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.711317553 |
|
|
Jul 09 05:11:13 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
29252271 ps |
| T942 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1300542815 |
|
|
Jul 09 05:11:19 PM PDT 24 |
Jul 09 05:11:24 PM PDT 24 |
95373561 ps |
| T90 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1085318454 |
|
|
Jul 09 05:11:06 PM PDT 24 |
Jul 09 05:11:09 PM PDT 24 |
45028667 ps |
| T110 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3885832051 |
|
|
Jul 09 05:11:17 PM PDT 24 |
Jul 09 05:11:23 PM PDT 24 |
25378096 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1400318927 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
30106938 ps |
| T92 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2247193004 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:23 PM PDT 24 |
1346097192 ps |
| T93 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2906348590 |
|
|
Jul 09 05:11:22 PM PDT 24 |
Jul 09 05:11:26 PM PDT 24 |
31460363 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3709130904 |
|
|
Jul 09 05:11:09 PM PDT 24 |
Jul 09 05:11:15 PM PDT 24 |
651251417 ps |
| T133 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2509112579 |
|
|
Jul 09 05:11:09 PM PDT 24 |
Jul 09 05:11:14 PM PDT 24 |
195935053 ps |
| T94 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3179365764 |
|
|
Jul 09 05:11:24 PM PDT 24 |
Jul 09 05:11:30 PM PDT 24 |
462638556 ps |
| T943 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2066132036 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
120549775 ps |
| T95 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2826070554 |
|
|
Jul 09 05:11:11 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
1684479144 ps |
| T96 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.243337574 |
|
|
Jul 09 05:11:11 PM PDT 24 |
Jul 09 05:11:18 PM PDT 24 |
413617279 ps |
| T130 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.335422595 |
|
|
Jul 09 05:11:17 PM PDT 24 |
Jul 09 05:11:24 PM PDT 24 |
201169269 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.343444491 |
|
|
Jul 09 05:11:20 PM PDT 24 |
Jul 09 05:11:25 PM PDT 24 |
16206592 ps |
| T97 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2355718353 |
|
|
Jul 09 05:11:01 PM PDT 24 |
Jul 09 05:11:08 PM PDT 24 |
781288320 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3433731707 |
|
|
Jul 09 05:11:07 PM PDT 24 |
Jul 09 05:11:09 PM PDT 24 |
125186497 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1634285081 |
|
|
Jul 09 05:11:11 PM PDT 24 |
Jul 09 05:11:17 PM PDT 24 |
28797004 ps |
| T946 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3522103000 |
|
|
Jul 09 05:11:02 PM PDT 24 |
Jul 09 05:11:05 PM PDT 24 |
76028123 ps |
| T947 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1996085839 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:18 PM PDT 24 |
195146579 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2268181404 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:11 PM PDT 24 |
17999328 ps |
| T138 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1333840191 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:20 PM PDT 24 |
490454745 ps |
| T949 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3353411580 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
36118767 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3084711862 |
|
|
Jul 09 05:11:02 PM PDT 24 |
Jul 09 05:11:07 PM PDT 24 |
28039942 ps |
| T951 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1654679576 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:11 PM PDT 24 |
13379952 ps |
| T134 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3561473521 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:17 PM PDT 24 |
208432630 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4026186419 |
|
|
Jul 09 05:11:13 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
116552423 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.173032375 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
94633121 ps |
| T135 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1362859827 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:16 PM PDT 24 |
178045943 ps |
| T98 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3719848646 |
|
|
Jul 09 05:11:13 PM PDT 24 |
Jul 09 05:11:22 PM PDT 24 |
791152132 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1353033838 |
|
|
Jul 09 05:11:14 PM PDT 24 |
Jul 09 05:11:22 PM PDT 24 |
33042396 ps |
| T139 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3369852196 |
|
|
Jul 09 05:11:19 PM PDT 24 |
Jul 09 05:11:26 PM PDT 24 |
1415639119 ps |
| T955 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4155895847 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
27013377 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3771529499 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:14 PM PDT 24 |
93881322 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3780063235 |
|
|
Jul 09 05:11:00 PM PDT 24 |
Jul 09 05:11:05 PM PDT 24 |
67891615 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.618789673 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:17 PM PDT 24 |
69237081 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2741028512 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:13 PM PDT 24 |
32210378 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.581137122 |
|
|
Jul 09 05:11:11 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
1640580020 ps |
| T105 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1616155753 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:20 PM PDT 24 |
1515582480 ps |
| T960 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.726700769 |
|
|
Jul 09 05:11:21 PM PDT 24 |
Jul 09 05:11:27 PM PDT 24 |
421727258 ps |
| T106 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1584375241 |
|
|
Jul 09 05:11:13 PM PDT 24 |
Jul 09 05:11:20 PM PDT 24 |
895199000 ps |
| T961 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1838376752 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:20 PM PDT 24 |
141210429 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3943142606 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
20444282 ps |
| T141 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1364590485 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:22 PM PDT 24 |
474952226 ps |
| T963 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3138689472 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:18 PM PDT 24 |
117184455 ps |
| T964 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.645355798 |
|
|
Jul 09 05:11:18 PM PDT 24 |
Jul 09 05:11:23 PM PDT 24 |
14374947 ps |
| T965 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4036217983 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:18 PM PDT 24 |
68342130 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1078006884 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:18 PM PDT 24 |
17214780 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3821422872 |
|
|
Jul 09 05:11:06 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
112049289 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1508735188 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:22 PM PDT 24 |
224679206 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3081249367 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
30829168 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1285750144 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:17 PM PDT 24 |
751640662 ps |
| T971 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3694127089 |
|
|
Jul 09 05:11:25 PM PDT 24 |
Jul 09 05:11:30 PM PDT 24 |
594253293 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2086888422 |
|
|
Jul 09 05:11:06 PM PDT 24 |
Jul 09 05:11:10 PM PDT 24 |
114106225 ps |
| T142 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2683248266 |
|
|
Jul 09 05:11:22 PM PDT 24 |
Jul 09 05:11:27 PM PDT 24 |
146050221 ps |
| T143 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3208341201 |
|
|
Jul 09 05:11:14 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
261098966 ps |
| T103 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.870382799 |
|
|
Jul 09 05:11:10 PM PDT 24 |
Jul 09 05:11:14 PM PDT 24 |
35297609 ps |
| T973 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1068503902 |
|
|
Jul 09 05:11:14 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
52739841 ps |
| T974 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.87082875 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
62997965 ps |
| T975 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2695466433 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
128344198 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2227968230 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:25 PM PDT 24 |
438044211 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3287176819 |
|
|
Jul 09 05:11:22 PM PDT 24 |
Jul 09 05:11:26 PM PDT 24 |
27654103 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2710085122 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:21 PM PDT 24 |
26286308 ps |
| T979 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.997663719 |
|
|
Jul 09 05:11:16 PM PDT 24 |
Jul 09 05:11:22 PM PDT 24 |
382493115 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.477653389 |
|
|
Jul 09 05:11:13 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
20306458 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1901789043 |
|
|
Jul 09 05:11:17 PM PDT 24 |
Jul 09 05:11:24 PM PDT 24 |
807710279 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3394993420 |
|
|
Jul 09 05:11:04 PM PDT 24 |
Jul 09 05:11:07 PM PDT 24 |
14521990 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3875901755 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:11 PM PDT 24 |
17801705 ps |
| T140 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1213291531 |
|
|
Jul 09 05:11:16 PM PDT 24 |
Jul 09 05:11:23 PM PDT 24 |
627186800 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2093382886 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
21149914 ps |
| T131 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2635609920 |
|
|
Jul 09 05:11:01 PM PDT 24 |
Jul 09 05:11:07 PM PDT 24 |
442690946 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1412255840 |
|
|
Jul 09 05:11:02 PM PDT 24 |
Jul 09 05:11:06 PM PDT 24 |
223677295 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4190134879 |
|
|
Jul 09 05:11:04 PM PDT 24 |
Jul 09 05:11:07 PM PDT 24 |
11215867 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2325384455 |
|
|
Jul 09 05:11:09 PM PDT 24 |
Jul 09 05:11:15 PM PDT 24 |
774695757 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3814973257 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
73645161 ps |
| T987 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3845820704 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:20 PM PDT 24 |
39169605 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1123771437 |
|
|
Jul 09 05:11:18 PM PDT 24 |
Jul 09 05:11:25 PM PDT 24 |
1406166842 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.241906725 |
|
|
Jul 09 05:11:04 PM PDT 24 |
Jul 09 05:11:08 PM PDT 24 |
176657002 ps |
| T990 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1114055863 |
|
|
Jul 09 05:11:12 PM PDT 24 |
Jul 09 05:11:19 PM PDT 24 |
585878693 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3581108202 |
|
|
Jul 09 05:11:17 PM PDT 24 |
Jul 09 05:11:22 PM PDT 24 |
42526593 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.610991646 |
|
|
Jul 09 05:11:09 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
16928459 ps |
| T993 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1187706208 |
|
|
Jul 09 05:11:20 PM PDT 24 |
Jul 09 05:11:27 PM PDT 24 |
119947265 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.247409026 |
|
|
Jul 09 05:11:21 PM PDT 24 |
Jul 09 05:11:25 PM PDT 24 |
15706829 ps |
| T136 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2930210232 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
1198883381 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4143519941 |
|
|
Jul 09 05:11:06 PM PDT 24 |
Jul 09 05:11:09 PM PDT 24 |
14175947 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3398478662 |
|
|
Jul 09 05:11:24 PM PDT 24 |
Jul 09 05:11:28 PM PDT 24 |
159842370 ps |
| T997 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4271381251 |
|
|
Jul 09 05:11:08 PM PDT 24 |
Jul 09 05:11:13 PM PDT 24 |
196379070 ps |
| T998 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1960513958 |
|
|
Jul 09 05:11:15 PM PDT 24 |
Jul 09 05:11:24 PM PDT 24 |
622848650 ps |
| T132 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1385364599 |
|
|
Jul 09 05:11:17 PM PDT 24 |
Jul 09 05:11:24 PM PDT 24 |
115146416 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.666495581 |
|
|
Jul 09 05:11:05 PM PDT 24 |
Jul 09 05:11:12 PM PDT 24 |
39158590 ps |
| T1000 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.284149334 |
|
|
Jul 09 05:11:14 PM PDT 24 |
Jul 09 05:11:20 PM PDT 24 |
33911384 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1183050832 |
|
|
Jul 09 05:11:07 PM PDT 24 |
Jul 09 05:11:10 PM PDT 24 |
19281601 ps |