Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148021428	1			T2	17918		T3	180346		T4	229026
instr_valid_dis	115464025	1			T2	17918		T3	180346		T4	229026
instr_en	21440633	1			T9	123074		T12	17612		T19	297734

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9677661	1			T9	117886		T19	98550		T35	1524
sram_ifetch_valid_disable	114461266	1			T2	17918		T3	180346		T4	229026
sram_ifetch_enable	23882501	1			T9	72462		T12	31770		T19	144430

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148021428	1			T2	17918		T3	180346		T4	229026
hw_debug_en_valid_off	116585264	1			T2	17918		T3	180346		T4	229026
hw_debug_en_on	20371431	1			T9	32906		T12	28630		T19	136112

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114461266	1			T2	17918		T3	180346		T4	229026
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102186163	1			T2	17918		T3	180346		T4	229026
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8209721	1			T9	12486		T19	72600		T35	171660
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3707417	1			T9	58126		T19	76586		T35	920
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1381658	1			T64	19316		T68	15690		T134	112576
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1482810	1			T9	58126		T19	76586		T35	920
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3730340	1			T19	8926		T64	40120		T60	25928
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1651272	1			T64	16228		T68	2386		T133	18196
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1528804	1			T19	8926		T64	23892		T68	43196
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8630237	1			T9	12486		T12	28630		T19	53314
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3763097	1			T12	28630		T64	37756		T67	77638
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3213284	1			T9	12486		T19	53314		T35	130578

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9282082	1			T9	52462		T12	17612		T19	126584
lc_exec_en	8010854	1			T9	20420		T19	73872		T64	109898
valid_exec_dis	111307747	1			T2	17918		T3	180346		T4	229026
invalid_exec_dis	33560162	1			T9	190348		T12	31770		T19	242980