Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44582462	1			T2	8135		T3	69183		T4	104082
triple_byte_access	2539651	1			T2	164		T3	724		T4	2036
halfword_access	3812581	1			T2	251		T3	1023		T4	3123
byte_access	5093326	1			T2	350		T3	1463		T4	4213
zero_access	1280485	1			T2	59		T3	354		T4	1059

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28600462

1

T2

4505

T3

36445

T4

57410

auto[1]

28708043

1

T2

4454

T3

36302

T4

57103

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22240106	1			T2	4096		T3	34636		T4	52087
auto[0]	triple_byte_access	1267332	1			T2	89		T3	350		T4	1070
auto[0]	halfword_access	1903345	1			T2	121		T3	522		T4	1566
auto[0]	byte_access	2545641	1			T2	164		T3	759		T4	2130
auto[0]	zero_access	644038	1			T2	35		T3	178		T4	557
auto[1]	word_access	22342356	1			T2	4039		T3	34547		T4	51995
auto[1]	triple_byte_access	1272319	1			T2	75		T3	374		T4	966
auto[1]	halfword_access	1909236	1			T2	130		T3	501		T4	1557
auto[1]	byte_access	2547685	1			T2	186		T3	704		T4	2083
auto[1]	zero_access	636447	1			T2	24		T3	176		T4	502