| T802 |
/workspace/coverage/default/33.sram_ctrl_stress_all.760174618 |
|
|
Jul 19 06:01:39 PM PDT 24 |
Jul 19 06:26:11 PM PDT 24 |
10635316591 ps |
| T803 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1580532674 |
|
|
Jul 19 06:00:21 PM PDT 24 |
Jul 19 06:48:23 PM PDT 24 |
92175409111 ps |
| T804 |
/workspace/coverage/default/11.sram_ctrl_executable.2585820860 |
|
|
Jul 19 05:59:50 PM PDT 24 |
Jul 19 06:20:00 PM PDT 24 |
15718266430 ps |
| T805 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2548854915 |
|
|
Jul 19 05:59:58 PM PDT 24 |
Jul 19 06:00:02 PM PDT 24 |
108168643 ps |
| T806 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2582173575 |
|
|
Jul 19 06:00:20 PM PDT 24 |
Jul 19 06:20:06 PM PDT 24 |
3108941770 ps |
| T807 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1324498886 |
|
|
Jul 19 06:01:39 PM PDT 24 |
Jul 19 06:07:03 PM PDT 24 |
13135833637 ps |
| T808 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3230191012 |
|
|
Jul 19 06:03:05 PM PDT 24 |
Jul 19 06:03:10 PM PDT 24 |
327768214 ps |
| T809 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1560307438 |
|
|
Jul 19 05:59:39 PM PDT 24 |
Jul 19 06:01:27 PM PDT 24 |
198553466 ps |
| T810 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.171854236 |
|
|
Jul 19 06:00:30 PM PDT 24 |
Jul 19 06:00:33 PM PDT 24 |
76374241 ps |
| T811 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1293338448 |
|
|
Jul 19 06:01:56 PM PDT 24 |
Jul 19 06:03:39 PM PDT 24 |
125621409 ps |
| T812 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.903074889 |
|
|
Jul 19 05:59:35 PM PDT 24 |
Jul 19 06:23:31 PM PDT 24 |
17109195267 ps |
| T813 |
/workspace/coverage/default/31.sram_ctrl_bijection.3965019575 |
|
|
Jul 19 06:01:24 PM PDT 24 |
Jul 19 06:02:24 PM PDT 24 |
2069193218 ps |
| T814 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1737724090 |
|
|
Jul 19 06:00:52 PM PDT 24 |
Jul 19 06:05:44 PM PDT 24 |
6441457782 ps |
| T815 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3661105275 |
|
|
Jul 19 05:59:22 PM PDT 24 |
Jul 19 06:03:27 PM PDT 24 |
48840489937 ps |
| T816 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3773470127 |
|
|
Jul 19 05:59:04 PM PDT 24 |
Jul 19 06:03:07 PM PDT 24 |
18539868206 ps |
| T817 |
/workspace/coverage/default/36.sram_ctrl_executable.2221230825 |
|
|
Jul 19 06:01:57 PM PDT 24 |
Jul 19 06:02:34 PM PDT 24 |
4014077554 ps |
| T818 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.138868546 |
|
|
Jul 19 06:01:30 PM PDT 24 |
Jul 19 06:19:58 PM PDT 24 |
48586699479 ps |
| T819 |
/workspace/coverage/default/30.sram_ctrl_regwen.2181328901 |
|
|
Jul 19 06:01:23 PM PDT 24 |
Jul 19 06:09:07 PM PDT 24 |
1822984443 ps |
| T820 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3972600894 |
|
|
Jul 19 06:01:40 PM PDT 24 |
Jul 19 06:01:54 PM PDT 24 |
243425970 ps |
| T821 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2961478142 |
|
|
Jul 19 05:59:30 PM PDT 24 |
Jul 19 06:05:25 PM PDT 24 |
13708052844 ps |
| T822 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.630118196 |
|
|
Jul 19 06:02:17 PM PDT 24 |
Jul 19 06:02:23 PM PDT 24 |
184538355 ps |
| T823 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2979940160 |
|
|
Jul 19 05:59:24 PM PDT 24 |
Jul 19 05:59:32 PM PDT 24 |
6634125949 ps |
| T824 |
/workspace/coverage/default/35.sram_ctrl_alert_test.859298222 |
|
|
Jul 19 06:01:57 PM PDT 24 |
Jul 19 06:01:59 PM PDT 24 |
15784944 ps |
| T825 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.914862835 |
|
|
Jul 19 06:00:53 PM PDT 24 |
Jul 19 06:01:00 PM PDT 24 |
780077242 ps |
| T826 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1777619678 |
|
|
Jul 19 06:01:16 PM PDT 24 |
Jul 19 06:12:21 PM PDT 24 |
3439522607 ps |
| T827 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2150649875 |
|
|
Jul 19 06:02:03 PM PDT 24 |
Jul 19 06:02:05 PM PDT 24 |
102545705 ps |
| T47 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2481736751 |
|
|
Jul 19 06:02:33 PM PDT 24 |
Jul 19 06:07:17 PM PDT 24 |
12686113803 ps |
| T828 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.3878920546 |
|
|
Jul 19 06:00:12 PM PDT 24 |
Jul 19 06:00:14 PM PDT 24 |
63851779 ps |
| T829 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2184521838 |
|
|
Jul 19 06:02:25 PM PDT 24 |
Jul 19 06:02:31 PM PDT 24 |
368509324 ps |
| T830 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2694063994 |
|
|
Jul 19 05:59:41 PM PDT 24 |
Jul 19 05:59:51 PM PDT 24 |
258750535 ps |
| T831 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.4258334488 |
|
|
Jul 19 06:00:00 PM PDT 24 |
Jul 19 06:00:01 PM PDT 24 |
96237505 ps |
| T832 |
/workspace/coverage/default/30.sram_ctrl_bijection.4236002550 |
|
|
Jul 19 06:01:13 PM PDT 24 |
Jul 19 06:01:47 PM PDT 24 |
1554532697 ps |
| T833 |
/workspace/coverage/default/4.sram_ctrl_stress_all.4038696898 |
|
|
Jul 19 05:59:21 PM PDT 24 |
Jul 19 06:50:34 PM PDT 24 |
7094002281 ps |
| T834 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1270758759 |
|
|
Jul 19 05:59:14 PM PDT 24 |
Jul 19 05:59:18 PM PDT 24 |
27536605 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3428259856 |
|
|
Jul 19 06:01:13 PM PDT 24 |
Jul 19 06:01:19 PM PDT 24 |
97514248 ps |
| T836 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3169148428 |
|
|
Jul 19 05:59:12 PM PDT 24 |
Jul 19 05:59:18 PM PDT 24 |
52473298 ps |
| T837 |
/workspace/coverage/default/4.sram_ctrl_executable.268498446 |
|
|
Jul 19 05:59:14 PM PDT 24 |
Jul 19 06:16:00 PM PDT 24 |
14814364361 ps |
| T838 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1212664877 |
|
|
Jul 19 06:01:09 PM PDT 24 |
Jul 19 06:01:51 PM PDT 24 |
245464820 ps |
| T839 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1686011148 |
|
|
Jul 19 05:59:22 PM PDT 24 |
Jul 19 05:59:31 PM PDT 24 |
2501349654 ps |
| T840 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3292934639 |
|
|
Jul 19 05:59:59 PM PDT 24 |
Jul 19 06:00:10 PM PDT 24 |
241545860 ps |
| T841 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1785612435 |
|
|
Jul 19 06:02:14 PM PDT 24 |
Jul 19 06:04:25 PM PDT 24 |
140688401 ps |
| T842 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1816260929 |
|
|
Jul 19 05:59:39 PM PDT 24 |
Jul 19 06:02:17 PM PDT 24 |
7221842657 ps |
| T843 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1412392602 |
|
|
Jul 19 05:59:16 PM PDT 24 |
Jul 19 06:01:19 PM PDT 24 |
1759120086 ps |
| T844 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.1314160140 |
|
|
Jul 19 06:01:38 PM PDT 24 |
Jul 19 06:17:31 PM PDT 24 |
61129139938 ps |
| T845 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2092236380 |
|
|
Jul 19 06:00:53 PM PDT 24 |
Jul 19 06:03:26 PM PDT 24 |
4050845531 ps |
| T846 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2467297573 |
|
|
Jul 19 06:00:06 PM PDT 24 |
Jul 19 06:00:45 PM PDT 24 |
205183110 ps |
| T847 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2589790460 |
|
|
Jul 19 06:01:57 PM PDT 24 |
Jul 19 06:02:05 PM PDT 24 |
2274256537 ps |
| T848 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1568905722 |
|
|
Jul 19 05:59:00 PM PDT 24 |
Jul 19 05:59:08 PM PDT 24 |
686699735 ps |
| T849 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2421517297 |
|
|
Jul 19 05:59:39 PM PDT 24 |
Jul 19 05:59:41 PM PDT 24 |
20357783 ps |
| T850 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.66507275 |
|
|
Jul 19 05:59:49 PM PDT 24 |
Jul 19 06:04:08 PM PDT 24 |
9887618199 ps |
| T851 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1603448740 |
|
|
Jul 19 06:00:59 PM PDT 24 |
Jul 19 06:25:00 PM PDT 24 |
37072504264 ps |
| T852 |
/workspace/coverage/default/38.sram_ctrl_partial_access.3699190470 |
|
|
Jul 19 06:02:10 PM PDT 24 |
Jul 19 06:02:30 PM PDT 24 |
19767461842 ps |
| T853 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3599493721 |
|
|
Jul 19 05:59:33 PM PDT 24 |
Jul 19 06:00:14 PM PDT 24 |
365247779 ps |
| T854 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.739131454 |
|
|
Jul 19 06:02:50 PM PDT 24 |
Jul 19 06:03:01 PM PDT 24 |
265594618 ps |
| T855 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3662348846 |
|
|
Jul 19 06:00:46 PM PDT 24 |
Jul 19 06:05:33 PM PDT 24 |
5721531738 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2445398871 |
|
|
Jul 19 06:00:42 PM PDT 24 |
Jul 19 06:05:14 PM PDT 24 |
3840692602 ps |
| T857 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2362552819 |
|
|
Jul 19 06:00:20 PM PDT 24 |
Jul 19 06:04:51 PM PDT 24 |
2859711534 ps |
| T858 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2324741231 |
|
|
Jul 19 06:00:16 PM PDT 24 |
Jul 19 06:03:34 PM PDT 24 |
5374203183 ps |
| T859 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.163540008 |
|
|
Jul 19 05:59:57 PM PDT 24 |
Jul 19 05:59:59 PM PDT 24 |
33389328 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.3410703914 |
|
|
Jul 19 06:00:30 PM PDT 24 |
Jul 19 06:00:37 PM PDT 24 |
429250118 ps |
| T861 |
/workspace/coverage/default/19.sram_ctrl_partial_access.3577537855 |
|
|
Jul 19 06:00:20 PM PDT 24 |
Jul 19 06:00:27 PM PDT 24 |
120704257 ps |
| T862 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1883672959 |
|
|
Jul 19 06:01:29 PM PDT 24 |
Jul 19 06:01:30 PM PDT 24 |
13460681 ps |
| T863 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3858267953 |
|
|
Jul 19 06:02:18 PM PDT 24 |
Jul 19 06:03:14 PM PDT 24 |
450051926 ps |
| T864 |
/workspace/coverage/default/18.sram_ctrl_smoke.4293199671 |
|
|
Jul 19 06:00:22 PM PDT 24 |
Jul 19 06:00:32 PM PDT 24 |
256042613 ps |
| T865 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3825426157 |
|
|
Jul 19 06:03:14 PM PDT 24 |
Jul 19 06:18:22 PM PDT 24 |
9982160643 ps |
| T866 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1733885959 |
|
|
Jul 19 06:00:14 PM PDT 24 |
Jul 19 06:00:23 PM PDT 24 |
136279698 ps |
| T867 |
/workspace/coverage/default/37.sram_ctrl_executable.1803509982 |
|
|
Jul 19 06:02:02 PM PDT 24 |
Jul 19 06:04:37 PM PDT 24 |
608696813 ps |
| T868 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3576734969 |
|
|
Jul 19 05:59:31 PM PDT 24 |
Jul 19 05:59:33 PM PDT 24 |
25301357 ps |
| T869 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1303204147 |
|
|
Jul 19 05:59:48 PM PDT 24 |
Jul 19 05:59:53 PM PDT 24 |
78842500 ps |
| T870 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3757754800 |
|
|
Jul 19 06:00:05 PM PDT 24 |
Jul 19 06:00:10 PM PDT 24 |
73491421 ps |
| T871 |
/workspace/coverage/default/35.sram_ctrl_regwen.764433132 |
|
|
Jul 19 06:01:55 PM PDT 24 |
Jul 19 06:20:13 PM PDT 24 |
11250217239 ps |
| T872 |
/workspace/coverage/default/43.sram_ctrl_smoke.3973613110 |
|
|
Jul 19 06:02:42 PM PDT 24 |
Jul 19 06:05:09 PM PDT 24 |
2385425897 ps |
| T873 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3522210616 |
|
|
Jul 19 05:59:15 PM PDT 24 |
Jul 19 05:59:18 PM PDT 24 |
117099914 ps |
| T25 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.1958015461 |
|
|
Jul 19 05:59:08 PM PDT 24 |
Jul 19 05:59:13 PM PDT 24 |
1061402652 ps |
| T874 |
/workspace/coverage/default/43.sram_ctrl_regwen.829409791 |
|
|
Jul 19 06:02:52 PM PDT 24 |
Jul 19 06:24:45 PM PDT 24 |
24767834362 ps |
| T875 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3646930209 |
|
|
Jul 19 06:01:39 PM PDT 24 |
Jul 19 06:02:49 PM PDT 24 |
2827317473 ps |
| T876 |
/workspace/coverage/default/41.sram_ctrl_executable.535899812 |
|
|
Jul 19 06:02:36 PM PDT 24 |
Jul 19 06:17:11 PM PDT 24 |
12696444962 ps |
| T877 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1058523401 |
|
|
Jul 19 06:00:44 PM PDT 24 |
Jul 19 06:06:20 PM PDT 24 |
7940548037 ps |
| T878 |
/workspace/coverage/default/33.sram_ctrl_smoke.1647579530 |
|
|
Jul 19 06:01:40 PM PDT 24 |
Jul 19 06:01:44 PM PDT 24 |
45786778 ps |
| T879 |
/workspace/coverage/default/44.sram_ctrl_bijection.690142890 |
|
|
Jul 19 06:02:57 PM PDT 24 |
Jul 19 06:03:40 PM PDT 24 |
944979304 ps |
| T880 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2938038681 |
|
|
Jul 19 06:00:46 PM PDT 24 |
Jul 19 06:00:51 PM PDT 24 |
2607289684 ps |
| T881 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.542984387 |
|
|
Jul 19 06:02:57 PM PDT 24 |
Jul 19 06:02:59 PM PDT 24 |
50633177 ps |
| T882 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.928491350 |
|
|
Jul 19 06:03:34 PM PDT 24 |
Jul 19 06:15:02 PM PDT 24 |
2578825817 ps |
| T883 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1444214387 |
|
|
Jul 19 06:00:30 PM PDT 24 |
Jul 19 06:50:37 PM PDT 24 |
8332559981 ps |
| T884 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2058152476 |
|
|
Jul 19 06:02:19 PM PDT 24 |
Jul 19 06:12:18 PM PDT 24 |
3906713833 ps |
| T885 |
/workspace/coverage/default/38.sram_ctrl_smoke.110440501 |
|
|
Jul 19 06:02:11 PM PDT 24 |
Jul 19 06:03:03 PM PDT 24 |
182244337 ps |
| T886 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3959527884 |
|
|
Jul 19 05:59:51 PM PDT 24 |
Jul 19 06:24:59 PM PDT 24 |
75171627264 ps |
| T887 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.166382694 |
|
|
Jul 19 06:01:17 PM PDT 24 |
Jul 19 06:01:25 PM PDT 24 |
2330868381 ps |
| T888 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.1105441369 |
|
|
Jul 19 06:00:54 PM PDT 24 |
Jul 19 06:01:03 PM PDT 24 |
242255904 ps |
| T889 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3416920556 |
|
|
Jul 19 06:00:00 PM PDT 24 |
Jul 19 06:00:01 PM PDT 24 |
19475855 ps |
| T890 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1825402308 |
|
|
Jul 19 05:59:56 PM PDT 24 |
Jul 19 06:02:03 PM PDT 24 |
601116723 ps |
| T891 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2991806125 |
|
|
Jul 19 06:00:28 PM PDT 24 |
Jul 19 06:03:31 PM PDT 24 |
1953737494 ps |
| T892 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.67842866 |
|
|
Jul 19 05:59:58 PM PDT 24 |
Jul 19 06:09:05 PM PDT 24 |
42082730718 ps |
| T893 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3698202681 |
|
|
Jul 19 06:00:54 PM PDT 24 |
Jul 19 06:00:57 PM PDT 24 |
83352790 ps |
| T894 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.1672843792 |
|
|
Jul 19 06:01:08 PM PDT 24 |
Jul 19 06:14:52 PM PDT 24 |
5675625832 ps |
| T895 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.3405913203 |
|
|
Jul 19 06:02:03 PM PDT 24 |
Jul 19 06:02:12 PM PDT 24 |
1375238633 ps |
| T896 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3720990413 |
|
|
Jul 19 06:00:35 PM PDT 24 |
Jul 19 06:00:39 PM PDT 24 |
1010470290 ps |
| T897 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2107780961 |
|
|
Jul 19 06:01:07 PM PDT 24 |
Jul 19 06:09:29 PM PDT 24 |
131248778095 ps |
| T898 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2457853670 |
|
|
Jul 19 06:03:28 PM PDT 24 |
Jul 19 06:27:18 PM PDT 24 |
9960554953 ps |
| T899 |
/workspace/coverage/default/17.sram_ctrl_bijection.224461690 |
|
|
Jul 19 06:00:14 PM PDT 24 |
Jul 19 06:01:22 PM PDT 24 |
6427242440 ps |
| T900 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.942482333 |
|
|
Jul 19 06:02:18 PM PDT 24 |
Jul 19 06:09:23 PM PDT 24 |
18496621630 ps |
| T901 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3798341322 |
|
|
Jul 19 06:02:51 PM PDT 24 |
Jul 19 06:02:56 PM PDT 24 |
248474781 ps |
| T902 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.2960172068 |
|
|
Jul 19 06:01:20 PM PDT 24 |
Jul 19 06:01:31 PM PDT 24 |
722577052 ps |
| T903 |
/workspace/coverage/default/24.sram_ctrl_executable.3720506818 |
|
|
Jul 19 06:00:52 PM PDT 24 |
Jul 19 06:12:15 PM PDT 24 |
2758276638 ps |
| T904 |
/workspace/coverage/default/45.sram_ctrl_alert_test.713630005 |
|
|
Jul 19 06:03:13 PM PDT 24 |
Jul 19 06:03:14 PM PDT 24 |
18563914 ps |
| T905 |
/workspace/coverage/default/20.sram_ctrl_smoke.1819878811 |
|
|
Jul 19 06:00:30 PM PDT 24 |
Jul 19 06:00:38 PM PDT 24 |
380027621 ps |
| T906 |
/workspace/coverage/default/19.sram_ctrl_bijection.656472559 |
|
|
Jul 19 06:00:22 PM PDT 24 |
Jul 19 06:01:21 PM PDT 24 |
3240256581 ps |
| T907 |
/workspace/coverage/default/6.sram_ctrl_regwen.150555228 |
|
|
Jul 19 05:59:23 PM PDT 24 |
Jul 19 06:02:23 PM PDT 24 |
5678177170 ps |
| T908 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.270545072 |
|
|
Jul 19 06:02:25 PM PDT 24 |
Jul 19 06:02:27 PM PDT 24 |
31820732 ps |
| T909 |
/workspace/coverage/default/36.sram_ctrl_smoke.2318590482 |
|
|
Jul 19 06:01:58 PM PDT 24 |
Jul 19 06:02:10 PM PDT 24 |
243533625 ps |
| T910 |
/workspace/coverage/default/9.sram_ctrl_alert_test.264626507 |
|
|
Jul 19 05:59:47 PM PDT 24 |
Jul 19 05:59:48 PM PDT 24 |
30699787 ps |
| T911 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2928667896 |
|
|
Jul 19 06:00:22 PM PDT 24 |
Jul 19 06:00:24 PM PDT 24 |
44506552 ps |
| T912 |
/workspace/coverage/default/7.sram_ctrl_bijection.384477916 |
|
|
Jul 19 05:59:39 PM PDT 24 |
Jul 19 06:00:42 PM PDT 24 |
7312200931 ps |
| T913 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2154593221 |
|
|
Jul 19 06:01:18 PM PDT 24 |
Jul 19 06:03:33 PM PDT 24 |
511254246 ps |
| T914 |
/workspace/coverage/default/42.sram_ctrl_partial_access.664221826 |
|
|
Jul 19 06:02:43 PM PDT 24 |
Jul 19 06:03:02 PM PDT 24 |
617830102 ps |
| T915 |
/workspace/coverage/default/28.sram_ctrl_smoke.511260533 |
|
|
Jul 19 06:01:12 PM PDT 24 |
Jul 19 06:02:44 PM PDT 24 |
129051640 ps |
| T916 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2041621493 |
|
|
Jul 19 06:02:27 PM PDT 24 |
Jul 19 06:19:11 PM PDT 24 |
13918030793 ps |
| T917 |
/workspace/coverage/default/16.sram_ctrl_smoke.2304298960 |
|
|
Jul 19 06:00:08 PM PDT 24 |
Jul 19 06:00:15 PM PDT 24 |
787412248 ps |
| T918 |
/workspace/coverage/default/10.sram_ctrl_regwen.2766073498 |
|
|
Jul 19 05:59:41 PM PDT 24 |
Jul 19 06:02:59 PM PDT 24 |
1287249958 ps |
| T919 |
/workspace/coverage/default/24.sram_ctrl_smoke.396060722 |
|
|
Jul 19 06:00:51 PM PDT 24 |
Jul 19 06:00:58 PM PDT 24 |
1025797531 ps |
| T920 |
/workspace/coverage/default/42.sram_ctrl_smoke.1297718957 |
|
|
Jul 19 06:02:44 PM PDT 24 |
Jul 19 06:03:00 PM PDT 24 |
719142391 ps |
| T921 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3253071263 |
|
|
Jul 19 05:59:31 PM PDT 24 |
Jul 19 06:05:14 PM PDT 24 |
12616806667 ps |
| T922 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2883724105 |
|
|
Jul 19 06:01:08 PM PDT 24 |
Jul 19 06:02:42 PM PDT 24 |
582808379 ps |
| T923 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1898022352 |
|
|
Jul 19 05:59:25 PM PDT 24 |
Jul 19 06:16:29 PM PDT 24 |
3613868820 ps |
| T924 |
/workspace/coverage/default/25.sram_ctrl_partial_access.883214550 |
|
|
Jul 19 06:00:54 PM PDT 24 |
Jul 19 06:01:13 PM PDT 24 |
377353591 ps |
| T925 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3287428957 |
|
|
Jul 19 06:01:16 PM PDT 24 |
Jul 19 06:01:18 PM PDT 24 |
160502019 ps |
| T926 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2260887762 |
|
|
Jul 19 06:02:38 PM PDT 24 |
Jul 19 06:02:39 PM PDT 24 |
25830981 ps |
| T927 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1345834295 |
|
|
Jul 19 05:59:30 PM PDT 24 |
Jul 19 06:21:44 PM PDT 24 |
13632077200 ps |
| T928 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2410906163 |
|
|
Jul 19 06:00:03 PM PDT 24 |
Jul 19 06:10:23 PM PDT 24 |
16116777858 ps |
| T929 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2386833697 |
|
|
Jul 19 06:01:07 PM PDT 24 |
Jul 19 06:01:48 PM PDT 24 |
2669748372 ps |
| T86 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2667283100 |
|
|
Jul 19 06:01:30 PM PDT 24 |
Jul 19 06:01:36 PM PDT 24 |
93670272 ps |
| T930 |
/workspace/coverage/default/11.sram_ctrl_smoke.911205677 |
|
|
Jul 19 05:59:55 PM PDT 24 |
Jul 19 06:01:47 PM PDT 24 |
579644687 ps |
| T931 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2121791929 |
|
|
Jul 19 06:00:06 PM PDT 24 |
Jul 19 06:04:44 PM PDT 24 |
5880713834 ps |
| T932 |
/workspace/coverage/default/3.sram_ctrl_bijection.2537142325 |
|
|
Jul 19 05:59:16 PM PDT 24 |
Jul 19 06:00:35 PM PDT 24 |
3581694363 ps |
| T933 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3980719458 |
|
|
Jul 19 06:02:53 PM PDT 24 |
Jul 19 06:02:54 PM PDT 24 |
85578984 ps |
| T934 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.1023716492 |
|
|
Jul 19 06:00:37 PM PDT 24 |
Jul 19 06:03:04 PM PDT 24 |
250592198 ps |
| T935 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2976980449 |
|
|
Jul 19 06:00:05 PM PDT 24 |
Jul 19 06:01:42 PM PDT 24 |
579891488 ps |
| T936 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2105224993 |
|
|
Jul 19 05:59:59 PM PDT 24 |
Jul 19 06:02:31 PM PDT 24 |
311165813 ps |
| T61 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2410780171 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
415204232 ps |
| T937 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4150234448 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:40 PM PDT 24 |
34617949 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2220506418 |
|
|
Jul 19 04:42:34 PM PDT 24 |
Jul 19 04:42:47 PM PDT 24 |
351753199 ps |
| T63 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2958883006 |
|
|
Jul 19 04:42:21 PM PDT 24 |
Jul 19 04:42:28 PM PDT 24 |
1709581902 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3987819090 |
|
|
Jul 19 04:42:38 PM PDT 24 |
Jul 19 04:42:49 PM PDT 24 |
18004075 ps |
| T938 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1356754418 |
|
|
Jul 19 04:42:40 PM PDT 24 |
Jul 19 04:42:53 PM PDT 24 |
123292713 ps |
| T132 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1173487994 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:40 PM PDT 24 |
68106682 ps |
| T70 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3844287404 |
|
|
Jul 19 04:42:40 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
31823585 ps |
| T57 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.665064762 |
|
|
Jul 19 04:42:50 PM PDT 24 |
Jul 19 04:42:57 PM PDT 24 |
276413371 ps |
| T103 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2759755240 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
14431489 ps |
| T939 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4290750651 |
|
|
Jul 19 04:42:38 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
109067030 ps |
| T58 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.792923048 |
|
|
Jul 19 04:42:36 PM PDT 24 |
Jul 19 04:42:49 PM PDT 24 |
740771742 ps |
| T940 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3149637819 |
|
|
Jul 19 04:42:34 PM PDT 24 |
Jul 19 04:42:48 PM PDT 24 |
79626481 ps |
| T59 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2119430032 |
|
|
Jul 19 04:42:21 PM PDT 24 |
Jul 19 04:42:29 PM PDT 24 |
940962737 ps |
| T71 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2607674450 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
18245277 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1596708603 |
|
|
Jul 19 04:42:31 PM PDT 24 |
Jul 19 04:42:43 PM PDT 24 |
32578499 ps |
| T72 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1845701454 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
37971756 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1604075987 |
|
|
Jul 19 04:42:33 PM PDT 24 |
Jul 19 04:42:46 PM PDT 24 |
72935686 ps |
| T104 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.937664919 |
|
|
Jul 19 04:42:27 PM PDT 24 |
Jul 19 04:42:37 PM PDT 24 |
51902327 ps |
| T97 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1247442918 |
|
|
Jul 19 04:42:23 PM PDT 24 |
Jul 19 04:42:30 PM PDT 24 |
15585376 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1847613513 |
|
|
Jul 19 04:42:32 PM PDT 24 |
Jul 19 04:42:46 PM PDT 24 |
2419656229 ps |
| T74 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1728101747 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
14828912 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2663422293 |
|
|
Jul 19 04:42:35 PM PDT 24 |
Jul 19 04:42:46 PM PDT 24 |
15053248 ps |
| T943 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3439708184 |
|
|
Jul 19 04:42:40 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
111146677 ps |
| T944 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1685191043 |
|
|
Jul 19 04:42:31 PM PDT 24 |
Jul 19 04:42:43 PM PDT 24 |
19461386 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2433624844 |
|
|
Jul 19 04:42:25 PM PDT 24 |
Jul 19 04:42:34 PM PDT 24 |
48736693 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.720054905 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:38 PM PDT 24 |
15718011 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3677368106 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
477339574 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3761786166 |
|
|
Jul 19 04:42:31 PM PDT 24 |
Jul 19 04:42:44 PM PDT 24 |
928451255 ps |
| T98 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.65467417 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
67189175 ps |
| T99 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3623970576 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
911619445 ps |
| T100 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.304221876 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:38 PM PDT 24 |
15198549 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1831749062 |
|
|
Jul 19 04:42:40 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
32060347 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1735504303 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
172077912 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2503443001 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
12632814 ps |
| T949 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1722350987 |
|
|
Jul 19 04:42:48 PM PDT 24 |
Jul 19 04:42:57 PM PDT 24 |
64386437 ps |
| T950 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1161739515 |
|
|
Jul 19 04:42:38 PM PDT 24 |
Jul 19 04:42:51 PM PDT 24 |
145122026 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1790602363 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
17404522 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4106984482 |
|
|
Jul 19 04:42:25 PM PDT 24 |
Jul 19 04:42:34 PM PDT 24 |
35564421 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.40392802 |
|
|
Jul 19 04:42:21 PM PDT 24 |
Jul 19 04:42:28 PM PDT 24 |
46361572 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1461055782 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:38 PM PDT 24 |
51566975 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3210319100 |
|
|
Jul 19 04:42:26 PM PDT 24 |
Jul 19 04:42:39 PM PDT 24 |
768988730 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1240871104 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:55 PM PDT 24 |
163085630 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.209191176 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
74640077 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3682369470 |
|
|
Jul 19 04:42:46 PM PDT 24 |
Jul 19 04:42:55 PM PDT 24 |
57404331 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3429633885 |
|
|
Jul 19 04:42:31 PM PDT 24 |
Jul 19 04:42:44 PM PDT 24 |
378686454 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1291330165 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
54010291 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2764411626 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
211619395 ps |
| T957 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.268977894 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
73743765 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3993663040 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
90072816 ps |
| T81 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2935531661 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
216382389 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1302089060 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:38 PM PDT 24 |
18282000 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2266157308 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:38 PM PDT 24 |
40902562 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3439675739 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:53 PM PDT 24 |
255040935 ps |
| T962 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2472952197 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
95438087 ps |
| T89 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4087899180 |
|
|
Jul 19 04:42:23 PM PDT 24 |
Jul 19 04:42:30 PM PDT 24 |
29797244 ps |
| T963 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2593473558 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:40 PM PDT 24 |
37422064 ps |
| T130 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.307112935 |
|
|
Jul 19 04:42:38 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
184909864 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1478174094 |
|
|
Jul 19 04:42:35 PM PDT 24 |
Jul 19 04:42:47 PM PDT 24 |
157414415 ps |
| T965 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4183007574 |
|
|
Jul 19 04:42:41 PM PDT 24 |
Jul 19 04:42:51 PM PDT 24 |
74194688 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1523601343 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
13792710 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2196027226 |
|
|
Jul 19 04:42:37 PM PDT 24 |
Jul 19 04:42:49 PM PDT 24 |
63558068 ps |
| T131 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.652535188 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
157009677 ps |
| T968 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.197440424 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
13250945 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1273723886 |
|
|
Jul 19 04:42:23 PM PDT 24 |
Jul 19 04:42:31 PM PDT 24 |
479206100 ps |
| T122 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3375349499 |
|
|
Jul 19 04:42:45 PM PDT 24 |
Jul 19 04:42:55 PM PDT 24 |
665814405 ps |
| T90 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2254090525 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:51 PM PDT 24 |
223348575 ps |
| T970 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.733407812 |
|
|
Jul 19 04:42:33 PM PDT 24 |
Jul 19 04:42:45 PM PDT 24 |
53118260 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3481563974 |
|
|
Jul 19 04:42:27 PM PDT 24 |
Jul 19 04:42:38 PM PDT 24 |
57131642 ps |
| T972 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3091111512 |
|
|
Jul 19 04:42:31 PM PDT 24 |
Jul 19 04:42:43 PM PDT 24 |
36993967 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.583061700 |
|
|
Jul 19 04:42:37 PM PDT 24 |
Jul 19 04:42:49 PM PDT 24 |
277028892 ps |
| T974 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.179867611 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
21692925 ps |
| T91 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2346298796 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:53 PM PDT 24 |
211826468 ps |
| T975 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1717548590 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
21920357 ps |
| T92 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1400751503 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
435809825 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.87179734 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
169163578 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3402508818 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:53 PM PDT 24 |
1205597561 ps |
| T978 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2622358267 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
107837641 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2406030802 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
38153961 ps |
| T95 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3924531281 |
|
|
Jul 19 04:42:42 PM PDT 24 |
Jul 19 04:42:53 PM PDT 24 |
224475740 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1353206432 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:43 PM PDT 24 |
434575435 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4113731219 |
|
|
Jul 19 04:42:24 PM PDT 24 |
Jul 19 04:42:31 PM PDT 24 |
14812715 ps |
| T127 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3085573428 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:51 PM PDT 24 |
187697581 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1106243230 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:39 PM PDT 24 |
62062629 ps |
| T124 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1305301297 |
|
|
Jul 19 04:42:40 PM PDT 24 |
Jul 19 04:42:52 PM PDT 24 |
751917562 ps |
| T129 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.205050676 |
|
|
Jul 19 04:42:27 PM PDT 24 |
Jul 19 04:42:40 PM PDT 24 |
253847584 ps |
| T125 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1158239606 |
|
|
Jul 19 04:42:32 PM PDT 24 |
Jul 19 04:42:46 PM PDT 24 |
330234788 ps |
| T982 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4002315560 |
|
|
Jul 19 04:42:34 PM PDT 24 |
Jul 19 04:42:48 PM PDT 24 |
228248084 ps |
| T126 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.103786109 |
|
|
Jul 19 04:42:40 PM PDT 24 |
Jul 19 04:42:51 PM PDT 24 |
292628520 ps |
| T983 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3916029435 |
|
|
Jul 19 04:42:44 PM PDT 24 |
Jul 19 04:42:54 PM PDT 24 |
352584328 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.202310156 |
|
|
Jul 19 04:42:40 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
15727089 ps |
| T123 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.763318731 |
|
|
Jul 19 04:42:39 PM PDT 24 |
Jul 19 04:42:50 PM PDT 24 |
556498691 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2913831502 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
245279629 ps |
| T986 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.580265110 |
|
|
Jul 19 04:42:33 PM PDT 24 |
Jul 19 04:42:47 PM PDT 24 |
31533651 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1869872444 |
|
|
Jul 19 04:42:26 PM PDT 24 |
Jul 19 04:42:37 PM PDT 24 |
130901073 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1144631630 |
|
|
Jul 19 04:42:27 PM PDT 24 |
Jul 19 04:42:37 PM PDT 24 |
14700116 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2192466351 |
|
|
Jul 19 04:42:42 PM PDT 24 |
Jul 19 04:42:54 PM PDT 24 |
491599938 ps |
| T119 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4169220810 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:42 PM PDT 24 |
341719759 ps |
| T94 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2126092840 |
|
|
Jul 19 04:42:48 PM PDT 24 |
Jul 19 04:42:58 PM PDT 24 |
1587955880 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1358084579 |
|
|
Jul 19 04:42:27 PM PDT 24 |
Jul 19 04:42:37 PM PDT 24 |
51659097 ps |
| T990 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3843162723 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:39 PM PDT 24 |
564372085 ps |
| T991 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2217204343 |
|
|
Jul 19 04:42:44 PM PDT 24 |
Jul 19 04:42:54 PM PDT 24 |
228537163 ps |
| T992 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3216914269 |
|
|
Jul 19 04:42:49 PM PDT 24 |
Jul 19 04:42:59 PM PDT 24 |
83357659 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.47462262 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:54 PM PDT 24 |
133009073 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.461999382 |
|
|
Jul 19 04:42:25 PM PDT 24 |
Jul 19 04:42:36 PM PDT 24 |
925196315 ps |
| T120 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3122405557 |
|
|
Jul 19 04:42:27 PM PDT 24 |
Jul 19 04:42:40 PM PDT 24 |
949122572 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3226795549 |
|
|
Jul 19 04:42:29 PM PDT 24 |
Jul 19 04:42:40 PM PDT 24 |
35479911 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2207007384 |
|
|
Jul 19 04:42:55 PM PDT 24 |
Jul 19 04:42:57 PM PDT 24 |
15749512 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.590894793 |
|
|
Jul 19 04:42:30 PM PDT 24 |
Jul 19 04:42:41 PM PDT 24 |
24623943 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1937563772 |
|
|
Jul 19 04:42:43 PM PDT 24 |
Jul 19 04:42:54 PM PDT 24 |
340470321 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3891011440 |
|
|
Jul 19 04:42:28 PM PDT 24 |
Jul 19 04:42:38 PM PDT 24 |
43588132 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2086058915 |
|
|
Jul 19 04:42:33 PM PDT 24 |
Jul 19 04:42:45 PM PDT 24 |
38066376 ps |