Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	154166062	1			T1	2464		T2	15658		T3	51018
instr_valid_dis	116138840	1			T1	2464		T2	15658		T7	314
instr_en	29178898	1			T3	51018		T8	126612		T11	363014

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11390454	1			T11	43214		T38	38282		T52	165234
sram_ifetch_valid_disable	117591076	1			T1	2464		T2	15658		T3	34290
sram_ifetch_enable	25184532	1			T3	16728		T8	42688		T11	121044

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	154166062	1			T1	2464		T2	15658		T3	51018
hw_debug_en_valid_off	117481366	1			T1	2464		T2	15658		T3	352
hw_debug_en_on	24945676	1			T3	16728		T8	17258		T11	103188

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117591076	1			T1	2464		T2	15658		T3	34290
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102660008	1			T1	2464		T2	15658		T7	314
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11287888	1			T3	34290		T8	84808		T11	198756
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4239700	1			T52	106970		T61	20000		T80	10724
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1412514	1			T118	12600		T135	13322		T6	30776
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2275502	1			T52	106970		T61	20000		T80	10724
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4984980	1			T11	19458		T38	38282		T52	58264
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1918892	1			T38	38282		T60	39162		T118	8374
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2368012	1			T11	19458		T52	58264		T80	39340
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10609118	1			T8	9710		T11	23844		T38	30260
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4333832	1			T38	30260		T80	177872		T18	8540
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4600016	1			T8	9710		T11	23844		T52	142700

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12225760	1			T3	16728		T8	41804		T11	121044
lc_exec_en	9351578	1			T3	16728		T8	7548		T11	59886
valid_exec_dis	111947074	1			T1	2464		T2	15658		T3	352
invalid_exec_dis	36574986	1			T3	16728		T8	42688		T11	164258