Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146534430	1			T1	32768		T2	143536		T3	442026
instr_valid_dis	113343961	1			T1	32768		T2	845122		T3	442026
instr_en	20017566	1			T2	505754		T7	25232		T10	56

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11357590	1			T2	108580		T10	97422		T11	32040
sram_ifetch_valid_disable	112686144	1			T1	32768		T2	106948		T3	442026
sram_ifetch_enable	22490696	1			T2	257298		T7	66438		T10	164632

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146534430	1			T1	32768		T2	143536		T3	442026
hw_debug_en_valid_off	113461204	1			T1	32768		T2	936042		T3	442026
hw_debug_en_on	22278000	1			T2	351822		T7	25232		T10	171048

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	112686144	1			T1	32768		T2	106948		T3	442026
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100143593	1			T1	32768		T2	791454		T3	442026
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7174960	1			T2	278028		T7	25232		T34	36980
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4328958	1			T2	48330		T10	53758		T11	25148
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1613030	1			T10	53758		T34	15846		T62	45298
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1787344	1			T2	48330		T11	25148		T63	51138
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4811510	1			T2	8046		T10	43664		T34	73530
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1771520	1			T2	1020		T10	43664		T76	2242
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1874748	1			T2	5450		T34	17342		T76	13582
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8350114	1			T2	220446		T7	25232		T11	40498
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3189254	1			T2	46770		T62	71700		T63	10146
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2912738	1			T2	173676		T7	25232		T34	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8379820	1			T2	155174		T10	56		T34	39070
lc_exec_en	9116376	1			T2	123330		T10	127384		T11	146172
valid_exec_dis	109545780	1			T1	32768		T2	852752		T3	442026
invalid_exec_dis	33848286	1			T2	365878		T7	66438		T10	262054