Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44161350	1			T1	16384		T2	464326		T3	200871
triple_byte_access	2485692	1			T2	8095		T3	4012		T4	32047
halfword_access	3729982	1			T2	12049		T3	6070		T4	48686
byte_access	4977785	1			T2	16082		T3	7968		T4	64620
zero_access	1254696	1			T2	4045		T3	2092		T4	16232

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28251312

1

T1

8192

T2

252185

T3

110874

auto[1]

28358193

1

T1

8192

T2

252412

T3

110139

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22030773	1			T1	8192		T2	232159		T3	100733
auto[0]	triple_byte_access	1239199	1			T2	4020		T3	2009		T4	15908
auto[0]	halfword_access	1861090	1			T2	5916		T3	3038		T4	24367
auto[0]	byte_access	2489031	1			T2	8041		T3	4049		T4	32349
auto[0]	zero_access	631219	1			T2	2049		T3	1045		T4	8096
auto[1]	word_access	22130577	1			T1	8192		T2	232167		T3	100138
auto[1]	triple_byte_access	1246493	1			T2	4075		T3	2003		T4	16139
auto[1]	halfword_access	1868892	1			T2	6133		T3	3032		T4	24319
auto[1]	byte_access	2488754	1			T2	8041		T3	3919		T4	32271
auto[1]	zero_access	623477	1			T2	1996		T3	1047		T4	8136