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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 99.16 94.27 99.72 100.00 95.95 99.12 97.26


Total test records in report: 1028
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T790 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2523407524 Aug 08 05:20:27 PM PDT 24 Aug 08 05:23:16 PM PDT 24 527845074 ps
T791 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4211991462 Aug 08 05:22:37 PM PDT 24 Aug 08 05:24:19 PM PDT 24 1555368565 ps
T792 /workspace/coverage/default/42.sram_ctrl_regwen.2974464010 Aug 08 05:21:41 PM PDT 24 Aug 08 05:42:48 PM PDT 24 3795635178 ps
T793 /workspace/coverage/default/49.sram_ctrl_bijection.3819376610 Aug 08 05:22:46 PM PDT 24 Aug 08 05:23:08 PM PDT 24 4908335817 ps
T794 /workspace/coverage/default/47.sram_ctrl_ram_cfg.1962823391 Aug 08 05:22:29 PM PDT 24 Aug 08 05:22:29 PM PDT 24 30816641 ps
T795 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2622636406 Aug 08 05:20:27 PM PDT 24 Aug 08 05:21:35 PM PDT 24 911021682 ps
T796 /workspace/coverage/default/21.sram_ctrl_max_throughput.4188805148 Aug 08 05:19:18 PM PDT 24 Aug 08 05:19:19 PM PDT 24 41198637 ps
T797 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.170558552 Aug 08 05:18:10 PM PDT 24 Aug 08 05:22:38 PM PDT 24 1387788832 ps
T798 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1344626917 Aug 08 05:19:19 PM PDT 24 Aug 08 05:27:55 PM PDT 24 2001276783 ps
T799 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1966007394 Aug 08 05:19:11 PM PDT 24 Aug 08 05:28:43 PM PDT 24 24588998149 ps
T800 /workspace/coverage/default/0.sram_ctrl_ram_cfg.3931999008 Aug 08 05:17:57 PM PDT 24 Aug 08 05:17:58 PM PDT 24 77980227 ps
T801 /workspace/coverage/default/11.sram_ctrl_mem_walk.1860128506 Aug 08 05:18:35 PM PDT 24 Aug 08 05:18:47 PM PDT 24 1182945189 ps
T802 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2106121139 Aug 08 05:22:24 PM PDT 24 Aug 08 05:22:30 PM PDT 24 1458972325 ps
T803 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.685137737 Aug 08 05:19:36 PM PDT 24 Aug 08 05:24:15 PM PDT 24 41888780360 ps
T804 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2327847229 Aug 08 05:19:28 PM PDT 24 Aug 08 05:23:15 PM PDT 24 2362095664 ps
T805 /workspace/coverage/default/3.sram_ctrl_bijection.1156912896 Aug 08 05:18:11 PM PDT 24 Aug 08 05:18:53 PM PDT 24 1974787127 ps
T806 /workspace/coverage/default/49.sram_ctrl_executable.2172448213 Aug 08 05:22:56 PM PDT 24 Aug 08 05:45:24 PM PDT 24 9151950871 ps
T807 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.803634260 Aug 08 05:18:46 PM PDT 24 Aug 08 05:18:51 PM PDT 24 355109706 ps
T808 /workspace/coverage/default/30.sram_ctrl_ram_cfg.2836728047 Aug 08 05:20:06 PM PDT 24 Aug 08 05:20:07 PM PDT 24 33918927 ps
T809 /workspace/coverage/default/6.sram_ctrl_ram_cfg.3623859113 Aug 08 05:18:12 PM PDT 24 Aug 08 05:18:13 PM PDT 24 47453162 ps
T810 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.4028281143 Aug 08 05:19:37 PM PDT 24 Aug 08 05:27:57 PM PDT 24 116090051497 ps
T811 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1234816441 Aug 08 05:21:58 PM PDT 24 Aug 08 05:24:54 PM PDT 24 6989900258 ps
T812 /workspace/coverage/default/16.sram_ctrl_regwen.4110248450 Aug 08 05:18:45 PM PDT 24 Aug 08 05:33:37 PM PDT 24 4537991026 ps
T813 /workspace/coverage/default/0.sram_ctrl_executable.3887245200 Aug 08 05:17:51 PM PDT 24 Aug 08 05:33:22 PM PDT 24 11293123342 ps
T814 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2723309298 Aug 08 05:20:47 PM PDT 24 Aug 08 05:29:56 PM PDT 24 14534187015 ps
T815 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4009389054 Aug 08 05:18:34 PM PDT 24 Aug 08 05:18:57 PM PDT 24 226376723 ps
T816 /workspace/coverage/default/49.sram_ctrl_stress_all.396301064 Aug 08 05:22:53 PM PDT 24 Aug 08 05:34:16 PM PDT 24 102751280071 ps
T817 /workspace/coverage/default/21.sram_ctrl_lc_escalation.1332460894 Aug 08 05:19:18 PM PDT 24 Aug 08 05:19:20 PM PDT 24 199276188 ps
T818 /workspace/coverage/default/8.sram_ctrl_ram_cfg.4137571421 Aug 08 05:18:21 PM PDT 24 Aug 08 05:18:22 PM PDT 24 93904960 ps
T819 /workspace/coverage/default/23.sram_ctrl_lc_escalation.1306685128 Aug 08 05:19:26 PM PDT 24 Aug 08 05:19:37 PM PDT 24 3572840612 ps
T820 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1074337797 Aug 08 05:18:13 PM PDT 24 Aug 08 05:35:20 PM PDT 24 3920923279 ps
T821 /workspace/coverage/default/19.sram_ctrl_regwen.3944994775 Aug 08 05:19:05 PM PDT 24 Aug 08 05:33:47 PM PDT 24 26754779932 ps
T822 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1298097588 Aug 08 05:18:02 PM PDT 24 Aug 08 05:19:39 PM PDT 24 4002956263 ps
T823 /workspace/coverage/default/5.sram_ctrl_bijection.2610907288 Aug 08 05:18:12 PM PDT 24 Aug 08 05:19:17 PM PDT 24 16904980033 ps
T824 /workspace/coverage/default/21.sram_ctrl_stress_all.1218984348 Aug 08 05:19:18 PM PDT 24 Aug 08 05:50:46 PM PDT 24 97704240505 ps
T825 /workspace/coverage/default/0.sram_ctrl_mem_walk.3643106338 Aug 08 05:17:52 PM PDT 24 Aug 08 05:17:58 PM PDT 24 985190175 ps
T826 /workspace/coverage/default/34.sram_ctrl_lc_escalation.423339423 Aug 08 05:20:25 PM PDT 24 Aug 08 05:20:31 PM PDT 24 1145857614 ps
T827 /workspace/coverage/default/34.sram_ctrl_executable.2889642931 Aug 08 05:20:27 PM PDT 24 Aug 08 05:36:16 PM PDT 24 2672191104 ps
T828 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.402049192 Aug 08 05:18:21 PM PDT 24 Aug 08 05:20:45 PM PDT 24 289159116 ps
T829 /workspace/coverage/default/36.sram_ctrl_executable.479091634 Aug 08 05:20:43 PM PDT 24 Aug 08 05:36:48 PM PDT 24 13810872499 ps
T830 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1811517653 Aug 08 05:21:07 PM PDT 24 Aug 08 05:36:17 PM PDT 24 11685654729 ps
T831 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1988496374 Aug 08 05:18:48 PM PDT 24 Aug 08 05:18:49 PM PDT 24 60390630 ps
T832 /workspace/coverage/default/15.sram_ctrl_partial_access.8161600 Aug 08 05:18:47 PM PDT 24 Aug 08 05:21:16 PM PDT 24 2205969110 ps
T833 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2960807988 Aug 08 05:20:34 PM PDT 24 Aug 08 05:30:30 PM PDT 24 2171148864 ps
T834 /workspace/coverage/default/16.sram_ctrl_multiple_keys.647942555 Aug 08 05:18:46 PM PDT 24 Aug 08 05:35:19 PM PDT 24 6912896459 ps
T835 /workspace/coverage/default/46.sram_ctrl_alert_test.2332900084 Aug 08 05:22:25 PM PDT 24 Aug 08 05:22:26 PM PDT 24 47065312 ps
T836 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.674344234 Aug 08 05:20:08 PM PDT 24 Aug 08 05:24:45 PM PDT 24 817169275 ps
T837 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2379605679 Aug 08 05:22:25 PM PDT 24 Aug 08 05:41:14 PM PDT 24 3365592650 ps
T838 /workspace/coverage/default/7.sram_ctrl_ram_cfg.382479230 Aug 08 05:18:23 PM PDT 24 Aug 08 05:18:24 PM PDT 24 138516971 ps
T839 /workspace/coverage/default/29.sram_ctrl_bijection.899406038 Aug 08 05:19:54 PM PDT 24 Aug 08 05:20:27 PM PDT 24 776290349 ps
T840 /workspace/coverage/default/31.sram_ctrl_max_throughput.3528999211 Aug 08 05:20:06 PM PDT 24 Aug 08 05:20:59 PM PDT 24 420126101 ps
T841 /workspace/coverage/default/27.sram_ctrl_partial_access.3739322531 Aug 08 05:19:46 PM PDT 24 Aug 08 05:20:03 PM PDT 24 419081354 ps
T842 /workspace/coverage/default/4.sram_ctrl_bijection.3068416874 Aug 08 05:18:03 PM PDT 24 Aug 08 05:18:28 PM PDT 24 1629623758 ps
T843 /workspace/coverage/default/41.sram_ctrl_lc_escalation.4072664178 Aug 08 05:21:30 PM PDT 24 Aug 08 05:21:36 PM PDT 24 733012907 ps
T844 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2987820077 Aug 08 05:21:06 PM PDT 24 Aug 08 05:22:13 PM PDT 24 2280022868 ps
T845 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1503687853 Aug 08 05:20:54 PM PDT 24 Aug 08 05:20:59 PM PDT 24 259872259 ps
T846 /workspace/coverage/default/21.sram_ctrl_executable.3756963364 Aug 08 05:19:17 PM PDT 24 Aug 08 05:45:18 PM PDT 24 134552591016 ps
T847 /workspace/coverage/default/11.sram_ctrl_lc_escalation.934931132 Aug 08 05:18:36 PM PDT 24 Aug 08 05:18:40 PM PDT 24 1084915476 ps
T848 /workspace/coverage/default/38.sram_ctrl_multiple_keys.526483629 Aug 08 05:20:57 PM PDT 24 Aug 08 05:38:37 PM PDT 24 12228887180 ps
T849 /workspace/coverage/default/19.sram_ctrl_smoke.2131447779 Aug 08 05:18:59 PM PDT 24 Aug 08 05:19:10 PM PDT 24 343845469 ps
T850 /workspace/coverage/default/48.sram_ctrl_regwen.1603440450 Aug 08 05:22:45 PM PDT 24 Aug 08 05:42:29 PM PDT 24 9466373149 ps
T851 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1810737738 Aug 08 05:21:58 PM PDT 24 Aug 08 05:24:56 PM PDT 24 550942541 ps
T852 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.4161414022 Aug 08 05:19:54 PM PDT 24 Aug 08 05:19:57 PM PDT 24 376871892 ps
T853 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3086923304 Aug 08 05:22:14 PM PDT 24 Aug 08 05:29:00 PM PDT 24 15523151794 ps
T854 /workspace/coverage/default/37.sram_ctrl_alert_test.2661259079 Aug 08 05:20:57 PM PDT 24 Aug 08 05:20:57 PM PDT 24 16296654 ps
T855 /workspace/coverage/default/32.sram_ctrl_stress_all.4041197655 Aug 08 05:20:16 PM PDT 24 Aug 08 05:52:38 PM PDT 24 50666366315 ps
T856 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.959530502 Aug 08 05:18:46 PM PDT 24 Aug 08 05:18:50 PM PDT 24 118826905 ps
T857 /workspace/coverage/default/3.sram_ctrl_mem_walk.1159400011 Aug 08 05:18:03 PM PDT 24 Aug 08 05:18:08 PM PDT 24 193752865 ps
T858 /workspace/coverage/default/0.sram_ctrl_lc_escalation.974945763 Aug 08 05:17:55 PM PDT 24 Aug 08 05:17:56 PM PDT 24 239819260 ps
T859 /workspace/coverage/default/40.sram_ctrl_smoke.2386249517 Aug 08 05:21:17 PM PDT 24 Aug 08 05:21:27 PM PDT 24 766311843 ps
T860 /workspace/coverage/default/2.sram_ctrl_alert_test.1794822995 Aug 08 05:18:09 PM PDT 24 Aug 08 05:18:10 PM PDT 24 23302108 ps
T861 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.502267 Aug 08 05:19:55 PM PDT 24 Aug 08 05:23:42 PM PDT 24 2437917642 ps
T862 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.4045586438 Aug 08 05:19:55 PM PDT 24 Aug 08 05:22:18 PM PDT 24 15799194523 ps
T863 /workspace/coverage/default/48.sram_ctrl_lc_escalation.1126141848 Aug 08 05:22:35 PM PDT 24 Aug 08 05:22:39 PM PDT 24 207249730 ps
T864 /workspace/coverage/default/29.sram_ctrl_alert_test.876523752 Aug 08 05:19:55 PM PDT 24 Aug 08 05:19:56 PM PDT 24 19598827 ps
T865 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.441258277 Aug 08 05:21:40 PM PDT 24 Aug 08 05:22:24 PM PDT 24 2224190549 ps
T866 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3862244201 Aug 08 05:18:22 PM PDT 24 Aug 08 05:21:27 PM PDT 24 2013453105 ps
T867 /workspace/coverage/default/12.sram_ctrl_stress_all.3715348082 Aug 08 05:18:34 PM PDT 24 Aug 08 05:46:47 PM PDT 24 3671342264 ps
T868 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1773737738 Aug 08 05:20:56 PM PDT 24 Aug 08 05:27:16 PM PDT 24 32829043582 ps
T869 /workspace/coverage/default/30.sram_ctrl_max_throughput.3389952954 Aug 08 05:19:55 PM PDT 24 Aug 08 05:20:35 PM PDT 24 99130977 ps
T870 /workspace/coverage/default/44.sram_ctrl_bijection.4235761043 Aug 08 05:21:58 PM PDT 24 Aug 08 05:22:24 PM PDT 24 395888138 ps
T871 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2379306966 Aug 08 05:18:00 PM PDT 24 Aug 08 05:20:54 PM PDT 24 163992942 ps
T872 /workspace/coverage/default/17.sram_ctrl_ram_cfg.2160214472 Aug 08 05:18:57 PM PDT 24 Aug 08 05:18:58 PM PDT 24 44288208 ps
T873 /workspace/coverage/default/31.sram_ctrl_multiple_keys.2847253895 Aug 08 05:20:05 PM PDT 24 Aug 08 05:26:29 PM PDT 24 2488657188 ps
T874 /workspace/coverage/default/5.sram_ctrl_max_throughput.87367852 Aug 08 05:18:11 PM PDT 24 Aug 08 05:18:15 PM PDT 24 93512033 ps
T875 /workspace/coverage/default/39.sram_ctrl_bijection.3926809830 Aug 08 05:21:07 PM PDT 24 Aug 08 05:21:41 PM PDT 24 4098470450 ps
T876 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1885975939 Aug 08 05:19:07 PM PDT 24 Aug 08 05:37:44 PM PDT 24 10698259126 ps
T877 /workspace/coverage/default/5.sram_ctrl_stress_all.4204672057 Aug 08 05:18:11 PM PDT 24 Aug 08 05:53:54 PM PDT 24 30339035634 ps
T878 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.490994947 Aug 08 05:20:37 PM PDT 24 Aug 08 05:20:47 PM PDT 24 70406935 ps
T879 /workspace/coverage/default/1.sram_ctrl_ram_cfg.2785357450 Aug 08 05:17:56 PM PDT 24 Aug 08 05:17:57 PM PDT 24 27433377 ps
T880 /workspace/coverage/default/45.sram_ctrl_alert_test.2464499157 Aug 08 05:22:17 PM PDT 24 Aug 08 05:22:18 PM PDT 24 121882558 ps
T881 /workspace/coverage/default/6.sram_ctrl_executable.4126884430 Aug 08 05:18:11 PM PDT 24 Aug 08 05:29:32 PM PDT 24 1206941886 ps
T882 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3993836709 Aug 08 05:19:55 PM PDT 24 Aug 08 05:19:55 PM PDT 24 84044837 ps
T883 /workspace/coverage/default/9.sram_ctrl_max_throughput.1497855337 Aug 08 05:18:32 PM PDT 24 Aug 08 05:20:55 PM PDT 24 143554190 ps
T884 /workspace/coverage/default/46.sram_ctrl_bijection.2785056261 Aug 08 05:22:16 PM PDT 24 Aug 08 05:22:52 PM PDT 24 2043787443 ps
T885 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1520809750 Aug 08 05:18:56 PM PDT 24 Aug 08 05:23:12 PM PDT 24 1798179457 ps
T886 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.391955325 Aug 08 05:18:45 PM PDT 24 Aug 08 05:26:50 PM PDT 24 13394334151 ps
T887 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1295830383 Aug 08 05:18:03 PM PDT 24 Aug 08 05:18:28 PM PDT 24 501505528 ps
T888 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2921380382 Aug 08 05:20:54 PM PDT 24 Aug 08 05:25:09 PM PDT 24 2257392055 ps
T889 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.4244818130 Aug 08 05:19:46 PM PDT 24 Aug 08 05:48:23 PM PDT 24 9779821336 ps
T890 /workspace/coverage/default/3.sram_ctrl_alert_test.2634397511 Aug 08 05:18:10 PM PDT 24 Aug 08 05:18:11 PM PDT 24 14436127 ps
T891 /workspace/coverage/default/16.sram_ctrl_stress_all.2090182628 Aug 08 05:18:48 PM PDT 24 Aug 08 06:12:52 PM PDT 24 57563748858 ps
T892 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3292049121 Aug 08 05:19:00 PM PDT 24 Aug 08 05:31:40 PM PDT 24 5480404462 ps
T893 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2417096832 Aug 08 05:18:22 PM PDT 24 Aug 08 05:22:05 PM PDT 24 5810470583 ps
T894 /workspace/coverage/default/43.sram_ctrl_multiple_keys.52092729 Aug 08 05:21:49 PM PDT 24 Aug 08 05:40:53 PM PDT 24 140752538844 ps
T895 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.806877745 Aug 08 05:20:16 PM PDT 24 Aug 08 05:22:41 PM PDT 24 5118067705 ps
T896 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3330177548 Aug 08 05:19:11 PM PDT 24 Aug 08 05:19:22 PM PDT 24 207065383 ps
T897 /workspace/coverage/default/48.sram_ctrl_mem_walk.1619004532 Aug 08 05:22:45 PM PDT 24 Aug 08 05:22:50 PM PDT 24 297721651 ps
T898 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.281107768 Aug 08 05:18:32 PM PDT 24 Aug 08 05:18:52 PM PDT 24 923330553 ps
T899 /workspace/coverage/default/49.sram_ctrl_mem_walk.2579042670 Aug 08 05:22:53 PM PDT 24 Aug 08 05:23:02 PM PDT 24 361088649 ps
T900 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.86107888 Aug 08 05:19:08 PM PDT 24 Aug 08 05:19:13 PM PDT 24 302394463 ps
T901 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.548542536 Aug 08 05:17:54 PM PDT 24 Aug 08 05:25:29 PM PDT 24 82102485890 ps
T902 /workspace/coverage/default/12.sram_ctrl_alert_test.239538063 Aug 08 05:18:33 PM PDT 24 Aug 08 05:18:34 PM PDT 24 43893070 ps
T903 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2359051657 Aug 08 05:18:56 PM PDT 24 Aug 08 05:18:59 PM PDT 24 213075605 ps
T904 /workspace/coverage/default/43.sram_ctrl_max_throughput.1094078670 Aug 08 05:21:50 PM PDT 24 Aug 08 05:21:51 PM PDT 24 42439744 ps
T905 /workspace/coverage/default/6.sram_ctrl_bijection.1004492515 Aug 08 05:18:09 PM PDT 24 Aug 08 05:18:40 PM PDT 24 5432840359 ps
T906 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.147285733 Aug 08 05:18:33 PM PDT 24 Aug 08 05:20:00 PM PDT 24 787173174 ps
T907 /workspace/coverage/default/23.sram_ctrl_stress_all.3538722139 Aug 08 05:19:28 PM PDT 24 Aug 08 05:48:40 PM PDT 24 24408532796 ps
T908 /workspace/coverage/default/23.sram_ctrl_partial_access.3492412724 Aug 08 05:19:24 PM PDT 24 Aug 08 05:19:44 PM PDT 24 7957102640 ps
T909 /workspace/coverage/default/24.sram_ctrl_max_throughput.1907284372 Aug 08 05:19:30 PM PDT 24 Aug 08 05:19:37 PM PDT 24 110894009 ps
T910 /workspace/coverage/default/16.sram_ctrl_alert_test.2919560272 Aug 08 05:18:45 PM PDT 24 Aug 08 05:18:46 PM PDT 24 13631648 ps
T911 /workspace/coverage/default/23.sram_ctrl_ram_cfg.492599230 Aug 08 05:19:25 PM PDT 24 Aug 08 05:19:26 PM PDT 24 47694317 ps
T912 /workspace/coverage/default/4.sram_ctrl_alert_test.363110116 Aug 08 05:18:11 PM PDT 24 Aug 08 05:18:12 PM PDT 24 75156115 ps
T25 /workspace/coverage/default/0.sram_ctrl_sec_cm.942724263 Aug 08 05:17:59 PM PDT 24 Aug 08 05:18:01 PM PDT 24 93433068 ps
T913 /workspace/coverage/default/27.sram_ctrl_lc_escalation.1728950358 Aug 08 05:19:48 PM PDT 24 Aug 08 05:19:50 PM PDT 24 331905203 ps
T914 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1253700343 Aug 08 05:18:46 PM PDT 24 Aug 08 05:19:31 PM PDT 24 454192093 ps
T915 /workspace/coverage/default/36.sram_ctrl_max_throughput.1495826269 Aug 08 05:20:46 PM PDT 24 Aug 08 05:23:14 PM PDT 24 543717767 ps
T916 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.138373265 Aug 08 05:22:07 PM PDT 24 Aug 08 05:30:14 PM PDT 24 69709351298 ps
T917 /workspace/coverage/default/7.sram_ctrl_multiple_keys.880441459 Aug 08 05:18:22 PM PDT 24 Aug 08 05:40:47 PM PDT 24 61231473656 ps
T918 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3873737817 Aug 08 05:18:58 PM PDT 24 Aug 08 05:34:04 PM PDT 24 15622125040 ps
T919 /workspace/coverage/default/10.sram_ctrl_mem_walk.1534471171 Aug 08 05:18:34 PM PDT 24 Aug 08 05:18:42 PM PDT 24 1934277330 ps
T920 /workspace/coverage/default/25.sram_ctrl_mem_walk.1156063472 Aug 08 05:19:40 PM PDT 24 Aug 08 05:19:47 PM PDT 24 1384570693 ps
T921 /workspace/coverage/default/47.sram_ctrl_regwen.2584335351 Aug 08 05:22:24 PM PDT 24 Aug 08 05:23:41 PM PDT 24 579699779 ps
T922 /workspace/coverage/default/6.sram_ctrl_lc_escalation.499366963 Aug 08 05:18:20 PM PDT 24 Aug 08 05:18:27 PM PDT 24 828250752 ps
T923 /workspace/coverage/default/39.sram_ctrl_regwen.4069147300 Aug 08 05:21:17 PM PDT 24 Aug 08 05:46:42 PM PDT 24 18441974615 ps
T924 /workspace/coverage/default/11.sram_ctrl_executable.2666589757 Aug 08 05:18:38 PM PDT 24 Aug 08 05:27:32 PM PDT 24 25548420299 ps
T925 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.4145141432 Aug 08 05:18:24 PM PDT 24 Aug 08 05:18:30 PM PDT 24 2019499192 ps
T926 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.539462803 Aug 08 05:21:17 PM PDT 24 Aug 08 05:21:49 PM PDT 24 155801903 ps
T927 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3152083901 Aug 08 05:22:14 PM PDT 24 Aug 08 05:22:19 PM PDT 24 1775828986 ps
T928 /workspace/coverage/default/5.sram_ctrl_mem_walk.4217101521 Aug 08 05:18:11 PM PDT 24 Aug 08 05:18:16 PM PDT 24 479107748 ps
T929 /workspace/coverage/default/21.sram_ctrl_regwen.1981947502 Aug 08 05:19:18 PM PDT 24 Aug 08 05:29:14 PM PDT 24 2781780641 ps
T930 /workspace/coverage/default/39.sram_ctrl_ram_cfg.2932279307 Aug 08 05:21:17 PM PDT 24 Aug 08 05:21:18 PM PDT 24 30213850 ps
T931 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2868064965 Aug 08 05:19:46 PM PDT 24 Aug 08 05:19:49 PM PDT 24 241774516 ps
T932 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.392240614 Aug 08 05:19:39 PM PDT 24 Aug 08 05:19:42 PM PDT 24 57318529 ps
T933 /workspace/coverage/default/38.sram_ctrl_stress_all.2501388164 Aug 08 05:21:07 PM PDT 24 Aug 08 06:01:14 PM PDT 24 42569210679 ps
T934 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2000371173 Aug 08 04:46:28 PM PDT 24 Aug 08 04:46:30 PM PDT 24 58149441 ps
T59 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.714554175 Aug 08 04:46:16 PM PDT 24 Aug 08 04:46:17 PM PDT 24 27154186 ps
T60 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.453947159 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:02 PM PDT 24 52259732 ps
T61 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2273887209 Aug 08 04:46:11 PM PDT 24 Aug 08 04:46:12 PM PDT 24 22315728 ps
T935 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.670492910 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:28 PM PDT 24 65930688 ps
T936 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3285662021 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:15 PM PDT 24 193189807 ps
T937 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2869658168 Aug 08 04:46:29 PM PDT 24 Aug 08 04:46:30 PM PDT 24 97575953 ps
T56 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3735924694 Aug 08 04:46:02 PM PDT 24 Aug 08 04:46:04 PM PDT 24 173517287 ps
T938 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2857271393 Aug 08 04:46:20 PM PDT 24 Aug 08 04:46:24 PM PDT 24 108115658 ps
T69 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.183318608 Aug 08 04:46:27 PM PDT 24 Aug 08 04:46:28 PM PDT 24 156956270 ps
T57 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.467178465 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:17 PM PDT 24 741475511 ps
T70 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1954298911 Aug 08 04:46:28 PM PDT 24 Aug 08 04:46:32 PM PDT 24 403686560 ps
T109 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2705503507 Aug 08 04:46:32 PM PDT 24 Aug 08 04:46:33 PM PDT 24 35092984 ps
T71 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.557365171 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:19 PM PDT 24 1830714091 ps
T72 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1612451385 Aug 08 04:46:29 PM PDT 24 Aug 08 04:46:31 PM PDT 24 483073374 ps
T110 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3451528562 Aug 08 04:46:29 PM PDT 24 Aug 08 04:46:30 PM PDT 24 22147511 ps
T58 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1148549582 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:28 PM PDT 24 173939073 ps
T73 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.597692980 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:17 PM PDT 24 122586115 ps
T939 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3778142686 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:04 PM PDT 24 43668219 ps
T102 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.87394453 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:04 PM PDT 24 26139085 ps
T74 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2441013081 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:15 PM PDT 24 47735252 ps
T75 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.759503060 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:15 PM PDT 24 34608332 ps
T103 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3427822814 Aug 08 04:46:13 PM PDT 24 Aug 08 04:46:14 PM PDT 24 21614841 ps
T84 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4016144187 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:29 PM PDT 24 269444915 ps
T85 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1807769348 Aug 08 04:46:20 PM PDT 24 Aug 08 04:46:22 PM PDT 24 337362274 ps
T940 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2708766861 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:02 PM PDT 24 46504500 ps
T941 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3704852057 Aug 08 04:46:02 PM PDT 24 Aug 08 04:46:06 PM PDT 24 63915289 ps
T942 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1472479377 Aug 08 04:46:29 PM PDT 24 Aug 08 04:46:30 PM PDT 24 133394470 ps
T131 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2042776396 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:03 PM PDT 24 154447972 ps
T97 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2262073616 Aug 08 04:46:27 PM PDT 24 Aug 08 04:46:28 PM PDT 24 29547946 ps
T132 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3600050661 Aug 08 04:46:27 PM PDT 24 Aug 08 04:46:30 PM PDT 24 188697651 ps
T135 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2482777929 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:17 PM PDT 24 560473763 ps
T86 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3671162508 Aug 08 04:46:04 PM PDT 24 Aug 08 04:46:05 PM PDT 24 27829448 ps
T943 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1447232094 Aug 08 04:46:30 PM PDT 24 Aug 08 04:46:31 PM PDT 24 15276528 ps
T98 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.41284064 Aug 08 04:46:27 PM PDT 24 Aug 08 04:46:30 PM PDT 24 585318604 ps
T87 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2321443344 Aug 08 04:46:00 PM PDT 24 Aug 08 04:46:01 PM PDT 24 51792320 ps
T944 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.387938914 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:15 PM PDT 24 197558182 ps
T945 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.598253631 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:31 PM PDT 24 264551914 ps
T88 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3297961504 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:16 PM PDT 24 456504361 ps
T946 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2732706669 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:16 PM PDT 24 493410418 ps
T947 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1543780427 Aug 08 04:46:04 PM PDT 24 Aug 08 04:46:05 PM PDT 24 23409845 ps
T948 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2764019107 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:19 PM PDT 24 451213166 ps
T139 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1505264305 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:17 PM PDT 24 255908122 ps
T89 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.362022386 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:04 PM PDT 24 230585909 ps
T99 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3164664259 Aug 08 04:46:06 PM PDT 24 Aug 08 04:46:10 PM PDT 24 2896053647 ps
T949 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3050580193 Aug 08 04:46:17 PM PDT 24 Aug 08 04:46:21 PM PDT 24 40634657 ps
T950 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.413220622 Aug 08 04:46:12 PM PDT 24 Aug 08 04:46:13 PM PDT 24 45002250 ps
T951 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2283180155 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:15 PM PDT 24 14689691 ps
T100 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1578354527 Aug 08 04:46:16 PM PDT 24 Aug 08 04:46:19 PM PDT 24 2743585796 ps
T137 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1997491899 Aug 08 04:45:59 PM PDT 24 Aug 08 04:46:02 PM PDT 24 186490857 ps
T952 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3733706202 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:06 PM PDT 24 103711629 ps
T953 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1083776122 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:27 PM PDT 24 43603872 ps
T133 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2823511612 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:17 PM PDT 24 437692711 ps
T954 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2932921132 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:03 PM PDT 24 15479402 ps
T955 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.695566412 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:27 PM PDT 24 44662719 ps
T956 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1092495718 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:05 PM PDT 24 388247921 ps
T957 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3532009815 Aug 08 04:46:02 PM PDT 24 Aug 08 04:46:03 PM PDT 24 55086355 ps
T958 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.443868213 Aug 08 04:46:20 PM PDT 24 Aug 08 04:46:20 PM PDT 24 38361970 ps
T959 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3882527600 Aug 08 04:46:16 PM PDT 24 Aug 08 04:46:16 PM PDT 24 23681113 ps
T960 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1729221824 Aug 08 04:46:17 PM PDT 24 Aug 08 04:46:18 PM PDT 24 81661500 ps
T961 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1154376390 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:16 PM PDT 24 199519163 ps
T962 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1668524676 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:16 PM PDT 24 12096030 ps
T963 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.933062402 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:02 PM PDT 24 137249511 ps
T964 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2424175154 Aug 08 04:46:20 PM PDT 24 Aug 08 04:46:21 PM PDT 24 14122379 ps
T965 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4001722609 Aug 08 04:46:16 PM PDT 24 Aug 08 04:46:18 PM PDT 24 28749588 ps
T966 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.27397033 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:05 PM PDT 24 371680730 ps
T138 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3178750667 Aug 08 04:46:17 PM PDT 24 Aug 08 04:46:20 PM PDT 24 819516002 ps
T967 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1162527435 Aug 08 04:46:07 PM PDT 24 Aug 08 04:46:08 PM PDT 24 30976713 ps
T968 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2363424531 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:27 PM PDT 24 104510620 ps
T969 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2230558750 Aug 08 04:46:13 PM PDT 24 Aug 08 04:46:17 PM PDT 24 126093207 ps
T970 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.446587555 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:17 PM PDT 24 24663505 ps
T971 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3706537196 Aug 08 04:46:17 PM PDT 24 Aug 08 04:46:21 PM PDT 24 125721441 ps
T134 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1171203660 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:16 PM PDT 24 289317156 ps
T972 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2424831105 Aug 08 04:46:02 PM PDT 24 Aug 08 04:46:03 PM PDT 24 21879892 ps
T973 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3203598428 Aug 08 04:46:04 PM PDT 24 Aug 08 04:46:06 PM PDT 24 168792164 ps
T974 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4091280334 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:03 PM PDT 24 36519761 ps
T975 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2356560435 Aug 08 04:46:16 PM PDT 24 Aug 08 04:46:17 PM PDT 24 37164218 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.333334899 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:04 PM PDT 24 47716515 ps
T977 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.558154520 Aug 08 04:46:17 PM PDT 24 Aug 08 04:46:17 PM PDT 24 16718844 ps
T978 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4039624294 Aug 08 04:46:07 PM PDT 24 Aug 08 04:46:11 PM PDT 24 509257144 ps
T979 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3567826743 Aug 08 04:46:16 PM PDT 24 Aug 08 04:46:18 PM PDT 24 72212574 ps
T980 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.462628852 Aug 08 04:46:29 PM PDT 24 Aug 08 04:46:33 PM PDT 24 458131520 ps
T981 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3879082277 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:27 PM PDT 24 69549091 ps
T982 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4146416070 Aug 08 04:46:28 PM PDT 24 Aug 08 04:46:30 PM PDT 24 148075842 ps
T983 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3773102290 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:28 PM PDT 24 150783069 ps
T984 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1582992127 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:16 PM PDT 24 65179637 ps
T985 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.393334264 Aug 08 04:46:18 PM PDT 24 Aug 08 04:46:20 PM PDT 24 365521690 ps
T986 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2159357262 Aug 08 04:46:27 PM PDT 24 Aug 08 04:46:30 PM PDT 24 149233794 ps
T987 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2630555494 Aug 08 04:46:00 PM PDT 24 Aug 08 04:46:02 PM PDT 24 116032465 ps
T988 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1686331016 Aug 08 04:46:14 PM PDT 24 Aug 08 04:46:14 PM PDT 24 39216423 ps
T989 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2746039835 Aug 08 04:46:29 PM PDT 24 Aug 08 04:46:33 PM PDT 24 82764899 ps
T990 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.776895739 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:29 PM PDT 24 139304942 ps
T991 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.598768422 Aug 08 04:46:15 PM PDT 24 Aug 08 04:46:19 PM PDT 24 1387663709 ps
T992 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.336003828 Aug 08 04:46:27 PM PDT 24 Aug 08 04:46:28 PM PDT 24 52316400 ps
T993 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2356946098 Aug 08 04:46:07 PM PDT 24 Aug 08 04:46:12 PM PDT 24 134586371 ps
T994 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2636780158 Aug 08 04:46:01 PM PDT 24 Aug 08 04:46:03 PM PDT 24 31555949 ps
T995 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3002616055 Aug 08 04:46:17 PM PDT 24 Aug 08 04:46:18 PM PDT 24 127704716 ps
T996 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.974777927 Aug 08 04:46:28 PM PDT 24 Aug 08 04:46:30 PM PDT 24 1369056913 ps
T997 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3019017730 Aug 08 04:46:13 PM PDT 24 Aug 08 04:46:14 PM PDT 24 59861803 ps
T998 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3027940273 Aug 08 04:46:28 PM PDT 24 Aug 08 04:46:31 PM PDT 24 1569159554 ps
T999 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2437987159 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:05 PM PDT 24 24826415 ps
T1000 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1365000145 Aug 08 04:46:26 PM PDT 24 Aug 08 04:46:27 PM PDT 24 43335824 ps
T140 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1600233160 Aug 08 04:46:00 PM PDT 24 Aug 08 04:46:02 PM PDT 24 72615453 ps
T1001 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1790736761 Aug 08 04:46:03 PM PDT 24 Aug 08 04:46:06 PM PDT 24 158869171 ps
T1002 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.285554108 Aug 08 04:46:00 PM PDT 24 Aug 08 04:46:02 PM PDT 24 115851807 ps
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