Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150038680	1			T1	276		T2	186424		T3	500284
instr_valid_dis	114106947	1			T1	276		T2	176768		T3	468108
instr_en	27793510	1			T2	9656		T3	16760		T10	92274

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11891985	1			T3	188346		T26	138808		T7	94884
sram_ifetch_valid_disable	112828441	1			T1	276		T2	175312		T3	243084
sram_ifetch_enable	25318254	1			T2	11112		T3	68854		T10	59706

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150038680	1			T1	276		T2	186424		T3	500284
hw_debug_en_valid_off	111204086	1			T1	276		T2	175846		T3	89284
hw_debug_en_on	25138686	1			T2	4340		T3	364352		T10	103726

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	112828441	1			T1	276		T2	175312		T3	243084
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97519998	1			T1	276		T2	175312		T3	211006
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12429891	1			T3	16760		T10	72782		T7	99362
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4701138	1			T3	55406		T26	114690		T7	62418
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2627058	1			T3	55406		T26	114690		T7	18480
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1595992	1			T7	43938		T133	7474		T118	88078
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4822518	1			T3	119584		T26	24118		T7	32466
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1983122	1			T3	119584		T26	3110		T7	10938
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2313566	1			T22	67396		T67	28660		T133	34256
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10655480	1			T3	182804		T10	76320		T7	81598
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4548315	1			T3	166044		T7	13204		T22	85422
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4895488	1			T3	16760		T10	56320		T7	68394

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10660535	1			T2	9656		T10	19492		T22	235550
lc_exec_en	9660688	1			T2	4340		T3	61964		T10	27406
valid_exec_dis	106987573	1			T1	276		T2	170906		T3	95744
invalid_exec_dis	37210239	1			T2	11112		T3	257200		T10	59706