Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43991203	1			T1	120		T2	66120		T3	91239
triple_byte_access	2431682	1			T1	1		T2	364		T3	1844
halfword_access	3649205	1			T1	6		T2	544		T3	2719
byte_access	4870774	1			T1	8		T2	724		T3	3533
zero_access	1226709	1			T1	3		T2	165		T3	853

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28029703

1

T1

64

T2

33623

T3

49922

auto[1]

28139870

1

T1

74

T2

34294

T3

50266

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21946351	1			T1	54		T2	32748		T3	45479
auto[0]	triple_byte_access	1212046	1			T1	1		T2	178		T3	925
auto[0]	halfword_access	1820599	1			T1	4		T2	271		T3	1369
auto[0]	byte_access	2433925	1			T1	3		T2	340		T3	1726
auto[0]	zero_access	616782	1			T1	2		T2	86		T3	423
auto[1]	word_access	22044852	1			T1	66		T2	33372		T3	45760
auto[1]	triple_byte_access	1219636	1			T2	186		T3	919		T4	2239
auto[1]	halfword_access	1828606	1			T1	2		T2	273		T3	1350
auto[1]	byte_access	2436849	1			T1	5		T2	384		T3	1807
auto[1]	zero_access	609927	1			T1	1		T2	79		T3	430