Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150448668	1			T1	7104		T2	12276		T3	17034
instr_valid_dis	117268734	1			T1	7104		T2	12276		T3	17034
instr_en	22707437	1			T10	224440		T27	173952		T8	293572

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9814488	1			T10	89428		T27	41728		T8	171118
sram_ifetch_valid_disable	116310145	1			T1	7104		T2	12276		T3	17034
sram_ifetch_enable	24324035	1			T10	182618		T27	160788		T8	185560

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150448668	1			T1	7104		T2	12276		T3	17034
hw_debug_en_valid_off	117272412	1			T1	7104		T2	12276		T3	17034
hw_debug_en_on	22116780	1			T10	11126		T27	254212		T8	233796

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116310145	1			T1	7104		T2	12276		T3	17034
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102059530	1			T1	7104		T2	12276		T3	17034
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9816141	1			T10	125170		T27	82018		T8	67240
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4053772	1			T10	56336		T27	20000		T8	53872
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1829830	1			T10	56336		T8	10702		T25	6128
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1418594	1			T8	23170		T73	36684		T21	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3870346	1			T27	16214		T8	89522		T63	13112
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1504372	1			T63	13112		T94	3442		T73	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1465784	1			T27	16214		T8	89522		T73	8222
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8434844	1			T10	10378		T27	162926		T8	83592
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3030024	1			T10	10378		T27	152268		T8	17254
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4133888	1			T27	10658		T8	66338		T63	26672

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9215636	1			T10	85568		T27	75720		T8	85916
lc_exec_en	9811590	1			T10	748		T27	75072		T8	60682
valid_exec_dis	113858102	1			T1	7104		T2	12276		T3	17034
invalid_exec_dis	34138523	1			T10	272046		T27	202516		T8	356678